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FSAE VCU Firmware V1.0
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Go to the source code of this file.
Macros | |
| #define | INT_GPIOA 16 |
| #define | INT_GPIOB 17 |
| #define | INT_GPIOC 18 |
| #define | INT_GPIOD 19 |
| #define | INT_GPIOE 20 |
| #define | INT_UART0 21 |
| #define | INT_UART1 22 |
| #define | INT_SSI0 23 |
| #define | INT_I2C0 24 |
| #define | INT_PWM0_FAULT 25 |
| #define | INT_PWM0_0 26 |
| #define | INT_PWM0_1 27 |
| #define | INT_PWM0_2 28 |
| #define | INT_QEI0 29 |
| #define | INT_ADC0SS0 30 |
| #define | INT_ADC0SS1 31 |
| #define | INT_ADC0SS2 32 |
| #define | INT_ADC0SS3 33 |
| #define | INT_WATCHDOG 34 |
| #define | INT_TIMER0A 35 |
| #define | INT_TIMER0B 36 |
| #define | INT_TIMER1A 37 |
| #define | INT_TIMER1B 38 |
| #define | INT_TIMER2A 39 |
| #define | INT_TIMER2B 40 |
| #define | INT_COMP0 41 |
| #define | INT_COMP1 42 |
| #define | INT_COMP2 43 |
| #define | INT_SYSCTL 44 |
| #define | INT_FLASH 45 |
| #define | INT_GPIOF 46 |
| #define | INT_GPIOG 47 |
| #define | INT_GPIOH 48 |
| #define | INT_UART2 49 |
| #define | INT_SSI1 50 |
| #define | INT_TIMER3A 51 |
| #define | INT_TIMER3B 52 |
| #define | INT_I2C1 53 |
| #define | INT_QEI1 54 |
| #define | INT_CAN0 55 |
| #define | INT_CAN1 56 |
| #define | INT_HIBERNATE 59 |
| #define | INT_USB0 60 |
| #define | INT_PWM0_3 61 |
| #define | INT_UDMA 62 |
| #define | INT_UDMAERR 63 |
| #define | INT_ADC1SS0 64 |
| #define | INT_ADC1SS1 65 |
| #define | INT_ADC1SS2 66 |
| #define | INT_ADC1SS3 67 |
| #define | INT_GPIOJ 70 |
| #define | INT_GPIOK 71 |
| #define | INT_GPIOL 72 |
| #define | INT_SSI2 73 |
| #define | INT_SSI3 74 |
| #define | INT_UART3 75 |
| #define | INT_UART4 76 |
| #define | INT_UART5 77 |
| #define | INT_UART6 78 |
| #define | INT_UART7 79 |
| #define | INT_I2C2 84 |
| #define | INT_I2C3 85 |
| #define | INT_TIMER4A 86 |
| #define | INT_TIMER4B 87 |
| #define | INT_TIMER5A 108 |
| #define | INT_TIMER5B 109 |
| #define | INT_WTIMER0A 110 |
| #define | INT_WTIMER0B 111 |
| #define | INT_WTIMER1A 112 |
| #define | INT_WTIMER1B 113 |
| #define | INT_WTIMER2A 114 |
| #define | INT_WTIMER2B 115 |
| #define | INT_WTIMER3A 116 |
| #define | INT_WTIMER3B 117 |
| #define | INT_WTIMER4A 118 |
| #define | INT_WTIMER4B 119 |
| #define | INT_WTIMER5A 120 |
| #define | INT_WTIMER5B 121 |
| #define | INT_SYSEXC 122 |
| #define | INT_I2C4 125 |
| #define | INT_I2C5 126 |
| #define | INT_GPIOM 127 |
| #define | INT_GPION 128 |
| #define | INT_GPIOP0 132 |
| #define | INT_GPIOP1 133 |
| #define | INT_GPIOP2 134 |
| #define | INT_GPIOP3 135 |
| #define | INT_GPIOP4 136 |
| #define | INT_GPIOP5 137 |
| #define | INT_GPIOP6 138 |
| #define | INT_GPIOP7 139 |
| #define | INT_PWM1_0 150 |
| #define | INT_PWM1_1 151 |
| #define | INT_PWM1_2 152 |
| #define | INT_PWM1_3 153 |
| #define | INT_PWM1_FAULT 154 |
| #define | WATCHDOG0_LOAD_R (*((volatile uint32_t *)0x40000000)) |
| #define | WATCHDOG0_VALUE_R (*((volatile uint32_t *)0x40000004)) |
| #define | WATCHDOG0_CTL_R (*((volatile uint32_t *)0x40000008)) |
| #define | WATCHDOG0_ICR_R (*((volatile uint32_t *)0x4000000C)) |
| #define | WATCHDOG0_RIS_R (*((volatile uint32_t *)0x40000010)) |
| #define | WATCHDOG0_MIS_R (*((volatile uint32_t *)0x40000014)) |
| #define | WATCHDOG0_TEST_R (*((volatile uint32_t *)0x40000418)) |
| #define | WATCHDOG0_LOCK_R (*((volatile uint32_t *)0x40000C00)) |
| #define | WATCHDOG1_LOAD_R (*((volatile uint32_t *)0x40001000)) |
| #define | WATCHDOG1_VALUE_R (*((volatile uint32_t *)0x40001004)) |
| #define | WATCHDOG1_CTL_R (*((volatile uint32_t *)0x40001008)) |
| #define | WATCHDOG1_ICR_R (*((volatile uint32_t *)0x4000100C)) |
| #define | WATCHDOG1_RIS_R (*((volatile uint32_t *)0x40001010)) |
| #define | WATCHDOG1_MIS_R (*((volatile uint32_t *)0x40001014)) |
| #define | WATCHDOG1_TEST_R (*((volatile uint32_t *)0x40001418)) |
| #define | WATCHDOG1_LOCK_R (*((volatile uint32_t *)0x40001C00)) |
| #define | GPIO_PORTA_DATA_BITS_R ((volatile uint32_t *)0x40004000) |
| #define | GPIO_PORTA_DATA_R (*((volatile uint32_t *)0x400043FC)) |
| #define | GPIO_PORTA_DIR_R (*((volatile uint32_t *)0x40004400)) |
| #define | GPIO_PORTA_IS_R (*((volatile uint32_t *)0x40004404)) |
| #define | GPIO_PORTA_IBE_R (*((volatile uint32_t *)0x40004408)) |
| #define | GPIO_PORTA_IEV_R (*((volatile uint32_t *)0x4000440C)) |
| #define | GPIO_PORTA_IM_R (*((volatile uint32_t *)0x40004410)) |
| #define | GPIO_PORTA_RIS_R (*((volatile uint32_t *)0x40004414)) |
| #define | GPIO_PORTA_MIS_R (*((volatile uint32_t *)0x40004418)) |
| #define | GPIO_PORTA_ICR_R (*((volatile uint32_t *)0x4000441C)) |
| #define | GPIO_PORTA_AFSEL_R (*((volatile uint32_t *)0x40004420)) |
| #define | GPIO_PORTA_DR2R_R (*((volatile uint32_t *)0x40004500)) |
| #define | GPIO_PORTA_DR4R_R (*((volatile uint32_t *)0x40004504)) |
| #define | GPIO_PORTA_DR8R_R (*((volatile uint32_t *)0x40004508)) |
| #define | GPIO_PORTA_ODR_R (*((volatile uint32_t *)0x4000450C)) |
| #define | GPIO_PORTA_PUR_R (*((volatile uint32_t *)0x40004510)) |
| #define | GPIO_PORTA_PDR_R (*((volatile uint32_t *)0x40004514)) |
| #define | GPIO_PORTA_SLR_R (*((volatile uint32_t *)0x40004518)) |
| #define | GPIO_PORTA_DEN_R (*((volatile uint32_t *)0x4000451C)) |
| #define | GPIO_PORTA_LOCK_R (*((volatile uint32_t *)0x40004520)) |
| #define | GPIO_PORTA_CR_R (*((volatile uint32_t *)0x40004524)) |
| #define | GPIO_PORTA_AMSEL_R (*((volatile uint32_t *)0x40004528)) |
| #define | GPIO_PORTA_PCTL_R (*((volatile uint32_t *)0x4000452C)) |
| #define | GPIO_PORTA_ADCCTL_R (*((volatile uint32_t *)0x40004530)) |
| #define | GPIO_PORTA_DMACTL_R (*((volatile uint32_t *)0x40004534)) |
| #define | GPIO_PORTA_SI_R (*((volatile uint32_t *)0x40004538)) |
| #define | GPIO_PORTB_DATA_BITS_R ((volatile uint32_t *)0x40005000) |
| #define | GPIO_PORTB_DATA_R (*((volatile uint32_t *)0x400053FC)) |
| #define | GPIO_PORTB_DIR_R (*((volatile uint32_t *)0x40005400)) |
| #define | GPIO_PORTB_IS_R (*((volatile uint32_t *)0x40005404)) |
| #define | GPIO_PORTB_IBE_R (*((volatile uint32_t *)0x40005408)) |
| #define | GPIO_PORTB_IEV_R (*((volatile uint32_t *)0x4000540C)) |
| #define | GPIO_PORTB_IM_R (*((volatile uint32_t *)0x40005410)) |
| #define | GPIO_PORTB_RIS_R (*((volatile uint32_t *)0x40005414)) |
| #define | GPIO_PORTB_MIS_R (*((volatile uint32_t *)0x40005418)) |
| #define | GPIO_PORTB_ICR_R (*((volatile uint32_t *)0x4000541C)) |
| #define | GPIO_PORTB_AFSEL_R (*((volatile uint32_t *)0x40005420)) |
| #define | GPIO_PORTB_DR2R_R (*((volatile uint32_t *)0x40005500)) |
| #define | GPIO_PORTB_DR4R_R (*((volatile uint32_t *)0x40005504)) |
| #define | GPIO_PORTB_DR8R_R (*((volatile uint32_t *)0x40005508)) |
| #define | GPIO_PORTB_ODR_R (*((volatile uint32_t *)0x4000550C)) |
| #define | GPIO_PORTB_PUR_R (*((volatile uint32_t *)0x40005510)) |
| #define | GPIO_PORTB_PDR_R (*((volatile uint32_t *)0x40005514)) |
| #define | GPIO_PORTB_SLR_R (*((volatile uint32_t *)0x40005518)) |
| #define | GPIO_PORTB_DEN_R (*((volatile uint32_t *)0x4000551C)) |
| #define | GPIO_PORTB_LOCK_R (*((volatile uint32_t *)0x40005520)) |
| #define | GPIO_PORTB_CR_R (*((volatile uint32_t *)0x40005524)) |
| #define | GPIO_PORTB_AMSEL_R (*((volatile uint32_t *)0x40005528)) |
| #define | GPIO_PORTB_PCTL_R (*((volatile uint32_t *)0x4000552C)) |
| #define | GPIO_PORTB_ADCCTL_R (*((volatile uint32_t *)0x40005530)) |
| #define | GPIO_PORTB_DMACTL_R (*((volatile uint32_t *)0x40005534)) |
| #define | GPIO_PORTB_SI_R (*((volatile uint32_t *)0x40005538)) |
| #define | GPIO_PORTC_DATA_BITS_R ((volatile uint32_t *)0x40006000) |
| #define | GPIO_PORTC_DATA_R (*((volatile uint32_t *)0x400063FC)) |
| #define | GPIO_PORTC_DIR_R (*((volatile uint32_t *)0x40006400)) |
| #define | GPIO_PORTC_IS_R (*((volatile uint32_t *)0x40006404)) |
| #define | GPIO_PORTC_IBE_R (*((volatile uint32_t *)0x40006408)) |
| #define | GPIO_PORTC_IEV_R (*((volatile uint32_t *)0x4000640C)) |
| #define | GPIO_PORTC_IM_R (*((volatile uint32_t *)0x40006410)) |
| #define | GPIO_PORTC_RIS_R (*((volatile uint32_t *)0x40006414)) |
| #define | GPIO_PORTC_MIS_R (*((volatile uint32_t *)0x40006418)) |
| #define | GPIO_PORTC_ICR_R (*((volatile uint32_t *)0x4000641C)) |
| #define | GPIO_PORTC_AFSEL_R (*((volatile uint32_t *)0x40006420)) |
| #define | GPIO_PORTC_DR2R_R (*((volatile uint32_t *)0x40006500)) |
| #define | GPIO_PORTC_DR4R_R (*((volatile uint32_t *)0x40006504)) |
| #define | GPIO_PORTC_DR8R_R (*((volatile uint32_t *)0x40006508)) |
| #define | GPIO_PORTC_ODR_R (*((volatile uint32_t *)0x4000650C)) |
| #define | GPIO_PORTC_PUR_R (*((volatile uint32_t *)0x40006510)) |
| #define | GPIO_PORTC_PDR_R (*((volatile uint32_t *)0x40006514)) |
| #define | GPIO_PORTC_SLR_R (*((volatile uint32_t *)0x40006518)) |
| #define | GPIO_PORTC_DEN_R (*((volatile uint32_t *)0x4000651C)) |
| #define | GPIO_PORTC_LOCK_R (*((volatile uint32_t *)0x40006520)) |
| #define | GPIO_PORTC_CR_R (*((volatile uint32_t *)0x40006524)) |
| #define | GPIO_PORTC_AMSEL_R (*((volatile uint32_t *)0x40006528)) |
| #define | GPIO_PORTC_PCTL_R (*((volatile uint32_t *)0x4000652C)) |
| #define | GPIO_PORTC_ADCCTL_R (*((volatile uint32_t *)0x40006530)) |
| #define | GPIO_PORTC_DMACTL_R (*((volatile uint32_t *)0x40006534)) |
| #define | GPIO_PORTC_SI_R (*((volatile uint32_t *)0x40006538)) |
| #define | GPIO_PORTD_DATA_BITS_R ((volatile uint32_t *)0x40007000) |
| #define | GPIO_PORTD_DATA_R (*((volatile uint32_t *)0x400073FC)) |
| #define | GPIO_PORTD_DIR_R (*((volatile uint32_t *)0x40007400)) |
| #define | GPIO_PORTD_IS_R (*((volatile uint32_t *)0x40007404)) |
| #define | GPIO_PORTD_IBE_R (*((volatile uint32_t *)0x40007408)) |
| #define | GPIO_PORTD_IEV_R (*((volatile uint32_t *)0x4000740C)) |
| #define | GPIO_PORTD_IM_R (*((volatile uint32_t *)0x40007410)) |
| #define | GPIO_PORTD_RIS_R (*((volatile uint32_t *)0x40007414)) |
| #define | GPIO_PORTD_MIS_R (*((volatile uint32_t *)0x40007418)) |
| #define | GPIO_PORTD_ICR_R (*((volatile uint32_t *)0x4000741C)) |
| #define | GPIO_PORTD_AFSEL_R (*((volatile uint32_t *)0x40007420)) |
| #define | GPIO_PORTD_DR2R_R (*((volatile uint32_t *)0x40007500)) |
| #define | GPIO_PORTD_DR4R_R (*((volatile uint32_t *)0x40007504)) |
| #define | GPIO_PORTD_DR8R_R (*((volatile uint32_t *)0x40007508)) |
| #define | GPIO_PORTD_ODR_R (*((volatile uint32_t *)0x4000750C)) |
| #define | GPIO_PORTD_PUR_R (*((volatile uint32_t *)0x40007510)) |
| #define | GPIO_PORTD_PDR_R (*((volatile uint32_t *)0x40007514)) |
| #define | GPIO_PORTD_SLR_R (*((volatile uint32_t *)0x40007518)) |
| #define | GPIO_PORTD_DEN_R (*((volatile uint32_t *)0x4000751C)) |
| #define | GPIO_PORTD_LOCK_R (*((volatile uint32_t *)0x40007520)) |
| #define | GPIO_PORTD_CR_R (*((volatile uint32_t *)0x40007524)) |
| #define | GPIO_PORTD_AMSEL_R (*((volatile uint32_t *)0x40007528)) |
| #define | GPIO_PORTD_PCTL_R (*((volatile uint32_t *)0x4000752C)) |
| #define | GPIO_PORTD_ADCCTL_R (*((volatile uint32_t *)0x40007530)) |
| #define | GPIO_PORTD_DMACTL_R (*((volatile uint32_t *)0x40007534)) |
| #define | GPIO_PORTD_SI_R (*((volatile uint32_t *)0x40007538)) |
| #define | SSI0_CR0_R (*((volatile uint32_t *)0x40008000)) |
| #define | SSI0_CR1_R (*((volatile uint32_t *)0x40008004)) |
| #define | SSI0_DR_R (*((volatile uint32_t *)0x40008008)) |
| #define | SSI0_SR_R (*((volatile uint32_t *)0x4000800C)) |
| #define | SSI0_CPSR_R (*((volatile uint32_t *)0x40008010)) |
| #define | SSI0_IM_R (*((volatile uint32_t *)0x40008014)) |
| #define | SSI0_RIS_R (*((volatile uint32_t *)0x40008018)) |
| #define | SSI0_MIS_R (*((volatile uint32_t *)0x4000801C)) |
| #define | SSI0_ICR_R (*((volatile uint32_t *)0x40008020)) |
| #define | SSI0_DMACTL_R (*((volatile uint32_t *)0x40008024)) |
| #define | SSI0_CC_R (*((volatile uint32_t *)0x40008FC8)) |
| #define | SSI1_CR0_R (*((volatile uint32_t *)0x40009000)) |
| #define | SSI1_CR1_R (*((volatile uint32_t *)0x40009004)) |
| #define | SSI1_DR_R (*((volatile uint32_t *)0x40009008)) |
| #define | SSI1_SR_R (*((volatile uint32_t *)0x4000900C)) |
| #define | SSI1_CPSR_R (*((volatile uint32_t *)0x40009010)) |
| #define | SSI1_IM_R (*((volatile uint32_t *)0x40009014)) |
| #define | SSI1_RIS_R (*((volatile uint32_t *)0x40009018)) |
| #define | SSI1_MIS_R (*((volatile uint32_t *)0x4000901C)) |
| #define | SSI1_ICR_R (*((volatile uint32_t *)0x40009020)) |
| #define | SSI1_DMACTL_R (*((volatile uint32_t *)0x40009024)) |
| #define | SSI1_CC_R (*((volatile uint32_t *)0x40009FC8)) |
| #define | SSI2_CR0_R (*((volatile uint32_t *)0x4000A000)) |
| #define | SSI2_CR1_R (*((volatile uint32_t *)0x4000A004)) |
| #define | SSI2_DR_R (*((volatile uint32_t *)0x4000A008)) |
| #define | SSI2_SR_R (*((volatile uint32_t *)0x4000A00C)) |
| #define | SSI2_CPSR_R (*((volatile uint32_t *)0x4000A010)) |
| #define | SSI2_IM_R (*((volatile uint32_t *)0x4000A014)) |
| #define | SSI2_RIS_R (*((volatile uint32_t *)0x4000A018)) |
| #define | SSI2_MIS_R (*((volatile uint32_t *)0x4000A01C)) |
| #define | SSI2_ICR_R (*((volatile uint32_t *)0x4000A020)) |
| #define | SSI2_DMACTL_R (*((volatile uint32_t *)0x4000A024)) |
| #define | SSI2_CC_R (*((volatile uint32_t *)0x4000AFC8)) |
| #define | SSI3_CR0_R (*((volatile uint32_t *)0x4000B000)) |
| #define | SSI3_CR1_R (*((volatile uint32_t *)0x4000B004)) |
| #define | SSI3_DR_R (*((volatile uint32_t *)0x4000B008)) |
| #define | SSI3_SR_R (*((volatile uint32_t *)0x4000B00C)) |
| #define | SSI3_CPSR_R (*((volatile uint32_t *)0x4000B010)) |
| #define | SSI3_IM_R (*((volatile uint32_t *)0x4000B014)) |
| #define | SSI3_RIS_R (*((volatile uint32_t *)0x4000B018)) |
| #define | SSI3_MIS_R (*((volatile uint32_t *)0x4000B01C)) |
| #define | SSI3_ICR_R (*((volatile uint32_t *)0x4000B020)) |
| #define | SSI3_DMACTL_R (*((volatile uint32_t *)0x4000B024)) |
| #define | SSI3_CC_R (*((volatile uint32_t *)0x4000BFC8)) |
| #define | UART0_DR_R (*((volatile uint32_t *)0x4000C000)) |
| #define | UART0_RSR_R (*((volatile uint32_t *)0x4000C004)) |
| #define | UART0_ECR_R (*((volatile uint32_t *)0x4000C004)) |
| #define | UART0_FR_R (*((volatile uint32_t *)0x4000C018)) |
| #define | UART0_ILPR_R (*((volatile uint32_t *)0x4000C020)) |
| #define | UART0_IBRD_R (*((volatile uint32_t *)0x4000C024)) |
| #define | UART0_FBRD_R (*((volatile uint32_t *)0x4000C028)) |
| #define | UART0_LCRH_R (*((volatile uint32_t *)0x4000C02C)) |
| #define | UART0_CTL_R (*((volatile uint32_t *)0x4000C030)) |
| #define | UART0_IFLS_R (*((volatile uint32_t *)0x4000C034)) |
| #define | UART0_IM_R (*((volatile uint32_t *)0x4000C038)) |
| #define | UART0_RIS_R (*((volatile uint32_t *)0x4000C03C)) |
| #define | UART0_MIS_R (*((volatile uint32_t *)0x4000C040)) |
| #define | UART0_ICR_R (*((volatile uint32_t *)0x4000C044)) |
| #define | UART0_DMACTL_R (*((volatile uint32_t *)0x4000C048)) |
| #define | UART0_9BITADDR_R (*((volatile uint32_t *)0x4000C0A4)) |
| #define | UART0_9BITAMASK_R (*((volatile uint32_t *)0x4000C0A8)) |
| #define | UART0_PP_R (*((volatile uint32_t *)0x4000CFC0)) |
| #define | UART0_CC_R (*((volatile uint32_t *)0x4000CFC8)) |
| #define | UART1_DR_R (*((volatile uint32_t *)0x4000D000)) |
| #define | UART1_RSR_R (*((volatile uint32_t *)0x4000D004)) |
| #define | UART1_ECR_R (*((volatile uint32_t *)0x4000D004)) |
| #define | UART1_FR_R (*((volatile uint32_t *)0x4000D018)) |
| #define | UART1_ILPR_R (*((volatile uint32_t *)0x4000D020)) |
| #define | UART1_IBRD_R (*((volatile uint32_t *)0x4000D024)) |
| #define | UART1_FBRD_R (*((volatile uint32_t *)0x4000D028)) |
| #define | UART1_LCRH_R (*((volatile uint32_t *)0x4000D02C)) |
| #define | UART1_CTL_R (*((volatile uint32_t *)0x4000D030)) |
| #define | UART1_IFLS_R (*((volatile uint32_t *)0x4000D034)) |
| #define | UART1_IM_R (*((volatile uint32_t *)0x4000D038)) |
| #define | UART1_RIS_R (*((volatile uint32_t *)0x4000D03C)) |
| #define | UART1_MIS_R (*((volatile uint32_t *)0x4000D040)) |
| #define | UART1_ICR_R (*((volatile uint32_t *)0x4000D044)) |
| #define | UART1_DMACTL_R (*((volatile uint32_t *)0x4000D048)) |
| #define | UART1_9BITADDR_R (*((volatile uint32_t *)0x4000D0A4)) |
| #define | UART1_9BITAMASK_R (*((volatile uint32_t *)0x4000D0A8)) |
| #define | UART1_PP_R (*((volatile uint32_t *)0x4000DFC0)) |
| #define | UART1_CC_R (*((volatile uint32_t *)0x4000DFC8)) |
| #define | UART2_DR_R (*((volatile uint32_t *)0x4000E000)) |
| #define | UART2_RSR_R (*((volatile uint32_t *)0x4000E004)) |
| #define | UART2_ECR_R (*((volatile uint32_t *)0x4000E004)) |
| #define | UART2_FR_R (*((volatile uint32_t *)0x4000E018)) |
| #define | UART2_ILPR_R (*((volatile uint32_t *)0x4000E020)) |
| #define | UART2_IBRD_R (*((volatile uint32_t *)0x4000E024)) |
| #define | UART2_FBRD_R (*((volatile uint32_t *)0x4000E028)) |
| #define | UART2_LCRH_R (*((volatile uint32_t *)0x4000E02C)) |
| #define | UART2_CTL_R (*((volatile uint32_t *)0x4000E030)) |
| #define | UART2_IFLS_R (*((volatile uint32_t *)0x4000E034)) |
| #define | UART2_IM_R (*((volatile uint32_t *)0x4000E038)) |
| #define | UART2_RIS_R (*((volatile uint32_t *)0x4000E03C)) |
| #define | UART2_MIS_R (*((volatile uint32_t *)0x4000E040)) |
| #define | UART2_ICR_R (*((volatile uint32_t *)0x4000E044)) |
| #define | UART2_DMACTL_R (*((volatile uint32_t *)0x4000E048)) |
| #define | UART2_9BITADDR_R (*((volatile uint32_t *)0x4000E0A4)) |
| #define | UART2_9BITAMASK_R (*((volatile uint32_t *)0x4000E0A8)) |
| #define | UART2_PP_R (*((volatile uint32_t *)0x4000EFC0)) |
| #define | UART2_CC_R (*((volatile uint32_t *)0x4000EFC8)) |
| #define | UART3_DR_R (*((volatile uint32_t *)0x4000F000)) |
| #define | UART3_RSR_R (*((volatile uint32_t *)0x4000F004)) |
| #define | UART3_ECR_R (*((volatile uint32_t *)0x4000F004)) |
| #define | UART3_FR_R (*((volatile uint32_t *)0x4000F018)) |
| #define | UART3_ILPR_R (*((volatile uint32_t *)0x4000F020)) |
| #define | UART3_IBRD_R (*((volatile uint32_t *)0x4000F024)) |
| #define | UART3_FBRD_R (*((volatile uint32_t *)0x4000F028)) |
| #define | UART3_LCRH_R (*((volatile uint32_t *)0x4000F02C)) |
| #define | UART3_CTL_R (*((volatile uint32_t *)0x4000F030)) |
| #define | UART3_IFLS_R (*((volatile uint32_t *)0x4000F034)) |
| #define | UART3_IM_R (*((volatile uint32_t *)0x4000F038)) |
| #define | UART3_RIS_R (*((volatile uint32_t *)0x4000F03C)) |
| #define | UART3_MIS_R (*((volatile uint32_t *)0x4000F040)) |
| #define | UART3_ICR_R (*((volatile uint32_t *)0x4000F044)) |
| #define | UART3_DMACTL_R (*((volatile uint32_t *)0x4000F048)) |
| #define | UART3_9BITADDR_R (*((volatile uint32_t *)0x4000F0A4)) |
| #define | UART3_9BITAMASK_R (*((volatile uint32_t *)0x4000F0A8)) |
| #define | UART3_PP_R (*((volatile uint32_t *)0x4000FFC0)) |
| #define | UART3_CC_R (*((volatile uint32_t *)0x4000FFC8)) |
| #define | UART4_DR_R (*((volatile uint32_t *)0x40010000)) |
| #define | UART4_RSR_R (*((volatile uint32_t *)0x40010004)) |
| #define | UART4_ECR_R (*((volatile uint32_t *)0x40010004)) |
| #define | UART4_FR_R (*((volatile uint32_t *)0x40010018)) |
| #define | UART4_ILPR_R (*((volatile uint32_t *)0x40010020)) |
| #define | UART4_IBRD_R (*((volatile uint32_t *)0x40010024)) |
| #define | UART4_FBRD_R (*((volatile uint32_t *)0x40010028)) |
| #define | UART4_LCRH_R (*((volatile uint32_t *)0x4001002C)) |
| #define | UART4_CTL_R (*((volatile uint32_t *)0x40010030)) |
| #define | UART4_IFLS_R (*((volatile uint32_t *)0x40010034)) |
| #define | UART4_IM_R (*((volatile uint32_t *)0x40010038)) |
| #define | UART4_RIS_R (*((volatile uint32_t *)0x4001003C)) |
| #define | UART4_MIS_R (*((volatile uint32_t *)0x40010040)) |
| #define | UART4_ICR_R (*((volatile uint32_t *)0x40010044)) |
| #define | UART4_DMACTL_R (*((volatile uint32_t *)0x40010048)) |
| #define | UART4_9BITADDR_R (*((volatile uint32_t *)0x400100A4)) |
| #define | UART4_9BITAMASK_R (*((volatile uint32_t *)0x400100A8)) |
| #define | UART4_PP_R (*((volatile uint32_t *)0x40010FC0)) |
| #define | UART4_CC_R (*((volatile uint32_t *)0x40010FC8)) |
| #define | UART5_DR_R (*((volatile uint32_t *)0x40011000)) |
| #define | UART5_RSR_R (*((volatile uint32_t *)0x40011004)) |
| #define | UART5_ECR_R (*((volatile uint32_t *)0x40011004)) |
| #define | UART5_FR_R (*((volatile uint32_t *)0x40011018)) |
| #define | UART5_ILPR_R (*((volatile uint32_t *)0x40011020)) |
| #define | UART5_IBRD_R (*((volatile uint32_t *)0x40011024)) |
| #define | UART5_FBRD_R (*((volatile uint32_t *)0x40011028)) |
| #define | UART5_LCRH_R (*((volatile uint32_t *)0x4001102C)) |
| #define | UART5_CTL_R (*((volatile uint32_t *)0x40011030)) |
| #define | UART5_IFLS_R (*((volatile uint32_t *)0x40011034)) |
| #define | UART5_IM_R (*((volatile uint32_t *)0x40011038)) |
| #define | UART5_RIS_R (*((volatile uint32_t *)0x4001103C)) |
| #define | UART5_MIS_R (*((volatile uint32_t *)0x40011040)) |
| #define | UART5_ICR_R (*((volatile uint32_t *)0x40011044)) |
| #define | UART5_DMACTL_R (*((volatile uint32_t *)0x40011048)) |
| #define | UART5_9BITADDR_R (*((volatile uint32_t *)0x400110A4)) |
| #define | UART5_9BITAMASK_R (*((volatile uint32_t *)0x400110A8)) |
| #define | UART5_PP_R (*((volatile uint32_t *)0x40011FC0)) |
| #define | UART5_CC_R (*((volatile uint32_t *)0x40011FC8)) |
| #define | UART6_DR_R (*((volatile uint32_t *)0x40012000)) |
| #define | UART6_RSR_R (*((volatile uint32_t *)0x40012004)) |
| #define | UART6_ECR_R (*((volatile uint32_t *)0x40012004)) |
| #define | UART6_FR_R (*((volatile uint32_t *)0x40012018)) |
| #define | UART6_ILPR_R (*((volatile uint32_t *)0x40012020)) |
| #define | UART6_IBRD_R (*((volatile uint32_t *)0x40012024)) |
| #define | UART6_FBRD_R (*((volatile uint32_t *)0x40012028)) |
| #define | UART6_LCRH_R (*((volatile uint32_t *)0x4001202C)) |
| #define | UART6_CTL_R (*((volatile uint32_t *)0x40012030)) |
| #define | UART6_IFLS_R (*((volatile uint32_t *)0x40012034)) |
| #define | UART6_IM_R (*((volatile uint32_t *)0x40012038)) |
| #define | UART6_RIS_R (*((volatile uint32_t *)0x4001203C)) |
| #define | UART6_MIS_R (*((volatile uint32_t *)0x40012040)) |
| #define | UART6_ICR_R (*((volatile uint32_t *)0x40012044)) |
| #define | UART6_DMACTL_R (*((volatile uint32_t *)0x40012048)) |
| #define | UART6_9BITADDR_R (*((volatile uint32_t *)0x400120A4)) |
| #define | UART6_9BITAMASK_R (*((volatile uint32_t *)0x400120A8)) |
| #define | UART6_PP_R (*((volatile uint32_t *)0x40012FC0)) |
| #define | UART6_CC_R (*((volatile uint32_t *)0x40012FC8)) |
| #define | UART7_DR_R (*((volatile uint32_t *)0x40013000)) |
| #define | UART7_RSR_R (*((volatile uint32_t *)0x40013004)) |
| #define | UART7_ECR_R (*((volatile uint32_t *)0x40013004)) |
| #define | UART7_FR_R (*((volatile uint32_t *)0x40013018)) |
| #define | UART7_ILPR_R (*((volatile uint32_t *)0x40013020)) |
| #define | UART7_IBRD_R (*((volatile uint32_t *)0x40013024)) |
| #define | UART7_FBRD_R (*((volatile uint32_t *)0x40013028)) |
| #define | UART7_LCRH_R (*((volatile uint32_t *)0x4001302C)) |
| #define | UART7_CTL_R (*((volatile uint32_t *)0x40013030)) |
| #define | UART7_IFLS_R (*((volatile uint32_t *)0x40013034)) |
| #define | UART7_IM_R (*((volatile uint32_t *)0x40013038)) |
| #define | UART7_RIS_R (*((volatile uint32_t *)0x4001303C)) |
| #define | UART7_MIS_R (*((volatile uint32_t *)0x40013040)) |
| #define | UART7_ICR_R (*((volatile uint32_t *)0x40013044)) |
| #define | UART7_DMACTL_R (*((volatile uint32_t *)0x40013048)) |
| #define | UART7_9BITADDR_R (*((volatile uint32_t *)0x400130A4)) |
| #define | UART7_9BITAMASK_R (*((volatile uint32_t *)0x400130A8)) |
| #define | UART7_PP_R (*((volatile uint32_t *)0x40013FC0)) |
| #define | UART7_CC_R (*((volatile uint32_t *)0x40013FC8)) |
| #define | I2C0_MSA_R (*((volatile uint32_t *)0x40020000)) |
| #define | I2C0_MCS_R (*((volatile uint32_t *)0x40020004)) |
| #define | I2C0_MDR_R (*((volatile uint32_t *)0x40020008)) |
| #define | I2C0_MTPR_R (*((volatile uint32_t *)0x4002000C)) |
| #define | I2C0_MIMR_R (*((volatile uint32_t *)0x40020010)) |
| #define | I2C0_MRIS_R (*((volatile uint32_t *)0x40020014)) |
| #define | I2C0_MMIS_R (*((volatile uint32_t *)0x40020018)) |
| #define | I2C0_MICR_R (*((volatile uint32_t *)0x4002001C)) |
| #define | I2C0_MCR_R (*((volatile uint32_t *)0x40020020)) |
| #define | I2C0_MCLKOCNT_R (*((volatile uint32_t *)0x40020024)) |
| #define | I2C0_MBMON_R (*((volatile uint32_t *)0x4002002C)) |
| #define | I2C0_MCR2_R (*((volatile uint32_t *)0x40020038)) |
| #define | I2C0_SOAR_R (*((volatile uint32_t *)0x40020800)) |
| #define | I2C0_SCSR_R (*((volatile uint32_t *)0x40020804)) |
| #define | I2C0_SDR_R (*((volatile uint32_t *)0x40020808)) |
| #define | I2C0_SIMR_R (*((volatile uint32_t *)0x4002080C)) |
| #define | I2C0_SRIS_R (*((volatile uint32_t *)0x40020810)) |
| #define | I2C0_SMIS_R (*((volatile uint32_t *)0x40020814)) |
| #define | I2C0_SICR_R (*((volatile uint32_t *)0x40020818)) |
| #define | I2C0_SOAR2_R (*((volatile uint32_t *)0x4002081C)) |
| #define | I2C0_SACKCTL_R (*((volatile uint32_t *)0x40020820)) |
| #define | I2C0_PP_R (*((volatile uint32_t *)0x40020FC0)) |
| #define | I2C0_PC_R (*((volatile uint32_t *)0x40020FC4)) |
| #define | I2C1_MSA_R (*((volatile uint32_t *)0x40021000)) |
| #define | I2C1_MCS_R (*((volatile uint32_t *)0x40021004)) |
| #define | I2C1_MDR_R (*((volatile uint32_t *)0x40021008)) |
| #define | I2C1_MTPR_R (*((volatile uint32_t *)0x4002100C)) |
| #define | I2C1_MIMR_R (*((volatile uint32_t *)0x40021010)) |
| #define | I2C1_MRIS_R (*((volatile uint32_t *)0x40021014)) |
| #define | I2C1_MMIS_R (*((volatile uint32_t *)0x40021018)) |
| #define | I2C1_MICR_R (*((volatile uint32_t *)0x4002101C)) |
| #define | I2C1_MCR_R (*((volatile uint32_t *)0x40021020)) |
| #define | I2C1_MCLKOCNT_R (*((volatile uint32_t *)0x40021024)) |
| #define | I2C1_MBMON_R (*((volatile uint32_t *)0x4002102C)) |
| #define | I2C1_MCR2_R (*((volatile uint32_t *)0x40021038)) |
| #define | I2C1_SOAR_R (*((volatile uint32_t *)0x40021800)) |
| #define | I2C1_SCSR_R (*((volatile uint32_t *)0x40021804)) |
| #define | I2C1_SDR_R (*((volatile uint32_t *)0x40021808)) |
| #define | I2C1_SIMR_R (*((volatile uint32_t *)0x4002180C)) |
| #define | I2C1_SRIS_R (*((volatile uint32_t *)0x40021810)) |
| #define | I2C1_SMIS_R (*((volatile uint32_t *)0x40021814)) |
| #define | I2C1_SICR_R (*((volatile uint32_t *)0x40021818)) |
| #define | I2C1_SOAR2_R (*((volatile uint32_t *)0x4002181C)) |
| #define | I2C1_SACKCTL_R (*((volatile uint32_t *)0x40021820)) |
| #define | I2C1_PP_R (*((volatile uint32_t *)0x40021FC0)) |
| #define | I2C1_PC_R (*((volatile uint32_t *)0x40021FC4)) |
| #define | I2C2_MSA_R (*((volatile uint32_t *)0x40022000)) |
| #define | I2C2_MCS_R (*((volatile uint32_t *)0x40022004)) |
| #define | I2C2_MDR_R (*((volatile uint32_t *)0x40022008)) |
| #define | I2C2_MTPR_R (*((volatile uint32_t *)0x4002200C)) |
| #define | I2C2_MIMR_R (*((volatile uint32_t *)0x40022010)) |
| #define | I2C2_MRIS_R (*((volatile uint32_t *)0x40022014)) |
| #define | I2C2_MMIS_R (*((volatile uint32_t *)0x40022018)) |
| #define | I2C2_MICR_R (*((volatile uint32_t *)0x4002201C)) |
| #define | I2C2_MCR_R (*((volatile uint32_t *)0x40022020)) |
| #define | I2C2_MCLKOCNT_R (*((volatile uint32_t *)0x40022024)) |
| #define | I2C2_MBMON_R (*((volatile uint32_t *)0x4002202C)) |
| #define | I2C2_MCR2_R (*((volatile uint32_t *)0x40022038)) |
| #define | I2C2_SOAR_R (*((volatile uint32_t *)0x40022800)) |
| #define | I2C2_SCSR_R (*((volatile uint32_t *)0x40022804)) |
| #define | I2C2_SDR_R (*((volatile uint32_t *)0x40022808)) |
| #define | I2C2_SIMR_R (*((volatile uint32_t *)0x4002280C)) |
| #define | I2C2_SRIS_R (*((volatile uint32_t *)0x40022810)) |
| #define | I2C2_SMIS_R (*((volatile uint32_t *)0x40022814)) |
| #define | I2C2_SICR_R (*((volatile uint32_t *)0x40022818)) |
| #define | I2C2_SOAR2_R (*((volatile uint32_t *)0x4002281C)) |
| #define | I2C2_SACKCTL_R (*((volatile uint32_t *)0x40022820)) |
| #define | I2C2_PP_R (*((volatile uint32_t *)0x40022FC0)) |
| #define | I2C2_PC_R (*((volatile uint32_t *)0x40022FC4)) |
| #define | I2C3_MSA_R (*((volatile uint32_t *)0x40023000)) |
| #define | I2C3_MCS_R (*((volatile uint32_t *)0x40023004)) |
| #define | I2C3_MDR_R (*((volatile uint32_t *)0x40023008)) |
| #define | I2C3_MTPR_R (*((volatile uint32_t *)0x4002300C)) |
| #define | I2C3_MIMR_R (*((volatile uint32_t *)0x40023010)) |
| #define | I2C3_MRIS_R (*((volatile uint32_t *)0x40023014)) |
| #define | I2C3_MMIS_R (*((volatile uint32_t *)0x40023018)) |
| #define | I2C3_MICR_R (*((volatile uint32_t *)0x4002301C)) |
| #define | I2C3_MCR_R (*((volatile uint32_t *)0x40023020)) |
| #define | I2C3_MCLKOCNT_R (*((volatile uint32_t *)0x40023024)) |
| #define | I2C3_MBMON_R (*((volatile uint32_t *)0x4002302C)) |
| #define | I2C3_MCR2_R (*((volatile uint32_t *)0x40023038)) |
| #define | I2C3_SOAR_R (*((volatile uint32_t *)0x40023800)) |
| #define | I2C3_SCSR_R (*((volatile uint32_t *)0x40023804)) |
| #define | I2C3_SDR_R (*((volatile uint32_t *)0x40023808)) |
| #define | I2C3_SIMR_R (*((volatile uint32_t *)0x4002380C)) |
| #define | I2C3_SRIS_R (*((volatile uint32_t *)0x40023810)) |
| #define | I2C3_SMIS_R (*((volatile uint32_t *)0x40023814)) |
| #define | I2C3_SICR_R (*((volatile uint32_t *)0x40023818)) |
| #define | I2C3_SOAR2_R (*((volatile uint32_t *)0x4002381C)) |
| #define | I2C3_SACKCTL_R (*((volatile uint32_t *)0x40023820)) |
| #define | I2C3_PP_R (*((volatile uint32_t *)0x40023FC0)) |
| #define | I2C3_PC_R (*((volatile uint32_t *)0x40023FC4)) |
| #define | GPIO_PORTE_DATA_BITS_R ((volatile uint32_t *)0x40024000) |
| #define | GPIO_PORTE_DATA_R (*((volatile uint32_t *)0x400243FC)) |
| #define | GPIO_PORTE_DIR_R (*((volatile uint32_t *)0x40024400)) |
| #define | GPIO_PORTE_IS_R (*((volatile uint32_t *)0x40024404)) |
| #define | GPIO_PORTE_IBE_R (*((volatile uint32_t *)0x40024408)) |
| #define | GPIO_PORTE_IEV_R (*((volatile uint32_t *)0x4002440C)) |
| #define | GPIO_PORTE_IM_R (*((volatile uint32_t *)0x40024410)) |
| #define | GPIO_PORTE_RIS_R (*((volatile uint32_t *)0x40024414)) |
| #define | GPIO_PORTE_MIS_R (*((volatile uint32_t *)0x40024418)) |
| #define | GPIO_PORTE_ICR_R (*((volatile uint32_t *)0x4002441C)) |
| #define | GPIO_PORTE_AFSEL_R (*((volatile uint32_t *)0x40024420)) |
| #define | GPIO_PORTE_DR2R_R (*((volatile uint32_t *)0x40024500)) |
| #define | GPIO_PORTE_DR4R_R (*((volatile uint32_t *)0x40024504)) |
| #define | GPIO_PORTE_DR8R_R (*((volatile uint32_t *)0x40024508)) |
| #define | GPIO_PORTE_ODR_R (*((volatile uint32_t *)0x4002450C)) |
| #define | GPIO_PORTE_PUR_R (*((volatile uint32_t *)0x40024510)) |
| #define | GPIO_PORTE_PDR_R (*((volatile uint32_t *)0x40024514)) |
| #define | GPIO_PORTE_SLR_R (*((volatile uint32_t *)0x40024518)) |
| #define | GPIO_PORTE_DEN_R (*((volatile uint32_t *)0x4002451C)) |
| #define | GPIO_PORTE_LOCK_R (*((volatile uint32_t *)0x40024520)) |
| #define | GPIO_PORTE_CR_R (*((volatile uint32_t *)0x40024524)) |
| #define | GPIO_PORTE_AMSEL_R (*((volatile uint32_t *)0x40024528)) |
| #define | GPIO_PORTE_PCTL_R (*((volatile uint32_t *)0x4002452C)) |
| #define | GPIO_PORTE_ADCCTL_R (*((volatile uint32_t *)0x40024530)) |
| #define | GPIO_PORTE_DMACTL_R (*((volatile uint32_t *)0x40024534)) |
| #define | GPIO_PORTE_SI_R (*((volatile uint32_t *)0x40024538)) |
| #define | GPIO_PORTF_DATA_BITS_R ((volatile uint32_t *)0x40025000) |
| #define | GPIO_PORTF_DATA_R (*((volatile uint32_t *)0x400253FC)) |
| #define | GPIO_PORTF_DIR_R (*((volatile uint32_t *)0x40025400)) |
| #define | GPIO_PORTF_IS_R (*((volatile uint32_t *)0x40025404)) |
| #define | GPIO_PORTF_IBE_R (*((volatile uint32_t *)0x40025408)) |
| #define | GPIO_PORTF_IEV_R (*((volatile uint32_t *)0x4002540C)) |
| #define | GPIO_PORTF_IM_R (*((volatile uint32_t *)0x40025410)) |
| #define | GPIO_PORTF_RIS_R (*((volatile uint32_t *)0x40025414)) |
| #define | GPIO_PORTF_MIS_R (*((volatile uint32_t *)0x40025418)) |
| #define | GPIO_PORTF_ICR_R (*((volatile uint32_t *)0x4002541C)) |
| #define | GPIO_PORTF_AFSEL_R (*((volatile uint32_t *)0x40025420)) |
| #define | GPIO_PORTF_DR2R_R (*((volatile uint32_t *)0x40025500)) |
| #define | GPIO_PORTF_DR4R_R (*((volatile uint32_t *)0x40025504)) |
| #define | GPIO_PORTF_DR8R_R (*((volatile uint32_t *)0x40025508)) |
| #define | GPIO_PORTF_ODR_R (*((volatile uint32_t *)0x4002550C)) |
| #define | GPIO_PORTF_PUR_R (*((volatile uint32_t *)0x40025510)) |
| #define | GPIO_PORTF_PDR_R (*((volatile uint32_t *)0x40025514)) |
| #define | GPIO_PORTF_SLR_R (*((volatile uint32_t *)0x40025518)) |
| #define | GPIO_PORTF_DEN_R (*((volatile uint32_t *)0x4002551C)) |
| #define | GPIO_PORTF_LOCK_R (*((volatile uint32_t *)0x40025520)) |
| #define | GPIO_PORTF_CR_R (*((volatile uint32_t *)0x40025524)) |
| #define | GPIO_PORTF_AMSEL_R (*((volatile uint32_t *)0x40025528)) |
| #define | GPIO_PORTF_PCTL_R (*((volatile uint32_t *)0x4002552C)) |
| #define | GPIO_PORTF_ADCCTL_R (*((volatile uint32_t *)0x40025530)) |
| #define | GPIO_PORTF_DMACTL_R (*((volatile uint32_t *)0x40025534)) |
| #define | GPIO_PORTF_SI_R (*((volatile uint32_t *)0x40025538)) |
| #define | GPIO_PORTG_DATA_BITS_R ((volatile uint32_t *)0x40026000) |
| #define | GPIO_PORTG_DATA_R (*((volatile uint32_t *)0x400263FC)) |
| #define | GPIO_PORTG_DIR_R (*((volatile uint32_t *)0x40026400)) |
| #define | GPIO_PORTG_IS_R (*((volatile uint32_t *)0x40026404)) |
| #define | GPIO_PORTG_IBE_R (*((volatile uint32_t *)0x40026408)) |
| #define | GPIO_PORTG_IEV_R (*((volatile uint32_t *)0x4002640C)) |
| #define | GPIO_PORTG_IM_R (*((volatile uint32_t *)0x40026410)) |
| #define | GPIO_PORTG_RIS_R (*((volatile uint32_t *)0x40026414)) |
| #define | GPIO_PORTG_MIS_R (*((volatile uint32_t *)0x40026418)) |
| #define | GPIO_PORTG_ICR_R (*((volatile uint32_t *)0x4002641C)) |
| #define | GPIO_PORTG_AFSEL_R (*((volatile uint32_t *)0x40026420)) |
| #define | GPIO_PORTG_DR2R_R (*((volatile uint32_t *)0x40026500)) |
| #define | GPIO_PORTG_DR4R_R (*((volatile uint32_t *)0x40026504)) |
| #define | GPIO_PORTG_DR8R_R (*((volatile uint32_t *)0x40026508)) |
| #define | GPIO_PORTG_ODR_R (*((volatile uint32_t *)0x4002650C)) |
| #define | GPIO_PORTG_PUR_R (*((volatile uint32_t *)0x40026510)) |
| #define | GPIO_PORTG_PDR_R (*((volatile uint32_t *)0x40026514)) |
| #define | GPIO_PORTG_SLR_R (*((volatile uint32_t *)0x40026518)) |
| #define | GPIO_PORTG_DEN_R (*((volatile uint32_t *)0x4002651C)) |
| #define | GPIO_PORTG_LOCK_R (*((volatile uint32_t *)0x40026520)) |
| #define | GPIO_PORTG_CR_R (*((volatile uint32_t *)0x40026524)) |
| #define | GPIO_PORTG_AMSEL_R (*((volatile uint32_t *)0x40026528)) |
| #define | GPIO_PORTG_PCTL_R (*((volatile uint32_t *)0x4002652C)) |
| #define | GPIO_PORTG_ADCCTL_R (*((volatile uint32_t *)0x40026530)) |
| #define | GPIO_PORTG_DMACTL_R (*((volatile uint32_t *)0x40026534)) |
| #define | GPIO_PORTG_SI_R (*((volatile uint32_t *)0x40026538)) |
| #define | GPIO_PORTH_DATA_BITS_R ((volatile uint32_t *)0x40027000) |
| #define | GPIO_PORTH_DATA_R (*((volatile uint32_t *)0x400273FC)) |
| #define | GPIO_PORTH_DIR_R (*((volatile uint32_t *)0x40027400)) |
| #define | GPIO_PORTH_IS_R (*((volatile uint32_t *)0x40027404)) |
| #define | GPIO_PORTH_IBE_R (*((volatile uint32_t *)0x40027408)) |
| #define | GPIO_PORTH_IEV_R (*((volatile uint32_t *)0x4002740C)) |
| #define | GPIO_PORTH_IM_R (*((volatile uint32_t *)0x40027410)) |
| #define | GPIO_PORTH_RIS_R (*((volatile uint32_t *)0x40027414)) |
| #define | GPIO_PORTH_MIS_R (*((volatile uint32_t *)0x40027418)) |
| #define | GPIO_PORTH_ICR_R (*((volatile uint32_t *)0x4002741C)) |
| #define | GPIO_PORTH_AFSEL_R (*((volatile uint32_t *)0x40027420)) |
| #define | GPIO_PORTH_DR2R_R (*((volatile uint32_t *)0x40027500)) |
| #define | GPIO_PORTH_DR4R_R (*((volatile uint32_t *)0x40027504)) |
| #define | GPIO_PORTH_DR8R_R (*((volatile uint32_t *)0x40027508)) |
| #define | GPIO_PORTH_ODR_R (*((volatile uint32_t *)0x4002750C)) |
| #define | GPIO_PORTH_PUR_R (*((volatile uint32_t *)0x40027510)) |
| #define | GPIO_PORTH_PDR_R (*((volatile uint32_t *)0x40027514)) |
| #define | GPIO_PORTH_SLR_R (*((volatile uint32_t *)0x40027518)) |
| #define | GPIO_PORTH_DEN_R (*((volatile uint32_t *)0x4002751C)) |
| #define | GPIO_PORTH_LOCK_R (*((volatile uint32_t *)0x40027520)) |
| #define | GPIO_PORTH_CR_R (*((volatile uint32_t *)0x40027524)) |
| #define | GPIO_PORTH_AMSEL_R (*((volatile uint32_t *)0x40027528)) |
| #define | GPIO_PORTH_PCTL_R (*((volatile uint32_t *)0x4002752C)) |
| #define | GPIO_PORTH_ADCCTL_R (*((volatile uint32_t *)0x40027530)) |
| #define | GPIO_PORTH_DMACTL_R (*((volatile uint32_t *)0x40027534)) |
| #define | GPIO_PORTH_SI_R (*((volatile uint32_t *)0x40027538)) |
| #define | PWM0_CTL_R (*((volatile uint32_t *)0x40028000)) |
| #define | PWM0_SYNC_R (*((volatile uint32_t *)0x40028004)) |
| #define | PWM0_ENABLE_R (*((volatile uint32_t *)0x40028008)) |
| #define | PWM0_INVERT_R (*((volatile uint32_t *)0x4002800C)) |
| #define | PWM0_FAULT_R (*((volatile uint32_t *)0x40028010)) |
| #define | PWM0_INTEN_R (*((volatile uint32_t *)0x40028014)) |
| #define | PWM0_RIS_R (*((volatile uint32_t *)0x40028018)) |
| #define | PWM0_ISC_R (*((volatile uint32_t *)0x4002801C)) |
| #define | PWM0_STATUS_R (*((volatile uint32_t *)0x40028020)) |
| #define | PWM0_FAULTVAL_R (*((volatile uint32_t *)0x40028024)) |
| #define | PWM0_ENUPD_R (*((volatile uint32_t *)0x40028028)) |
| #define | PWM0_0_CTL_R (*((volatile uint32_t *)0x40028040)) |
| #define | PWM0_0_INTEN_R (*((volatile uint32_t *)0x40028044)) |
| #define | PWM0_0_RIS_R (*((volatile uint32_t *)0x40028048)) |
| #define | PWM0_0_ISC_R (*((volatile uint32_t *)0x4002804C)) |
| #define | PWM0_0_LOAD_R (*((volatile uint32_t *)0x40028050)) |
| #define | PWM0_0_COUNT_R (*((volatile uint32_t *)0x40028054)) |
| #define | PWM0_0_CMPA_R (*((volatile uint32_t *)0x40028058)) |
| #define | PWM0_0_CMPB_R (*((volatile uint32_t *)0x4002805C)) |
| #define | PWM0_0_GENA_R (*((volatile uint32_t *)0x40028060)) |
| #define | PWM0_0_GENB_R (*((volatile uint32_t *)0x40028064)) |
| #define | PWM0_0_DBCTL_R (*((volatile uint32_t *)0x40028068)) |
| #define | PWM0_0_DBRISE_R (*((volatile uint32_t *)0x4002806C)) |
| #define | PWM0_0_DBFALL_R (*((volatile uint32_t *)0x40028070)) |
| #define | PWM0_0_FLTSRC0_R (*((volatile uint32_t *)0x40028074)) |
| #define | PWM0_0_FLTSRC1_R (*((volatile uint32_t *)0x40028078)) |
| #define | PWM0_0_MINFLTPER_R (*((volatile uint32_t *)0x4002807C)) |
| #define | PWM0_1_CTL_R (*((volatile uint32_t *)0x40028080)) |
| #define | PWM0_1_INTEN_R (*((volatile uint32_t *)0x40028084)) |
| #define | PWM0_1_RIS_R (*((volatile uint32_t *)0x40028088)) |
| #define | PWM0_1_ISC_R (*((volatile uint32_t *)0x4002808C)) |
| #define | PWM0_1_LOAD_R (*((volatile uint32_t *)0x40028090)) |
| #define | PWM0_1_COUNT_R (*((volatile uint32_t *)0x40028094)) |
| #define | PWM0_1_CMPA_R (*((volatile uint32_t *)0x40028098)) |
| #define | PWM0_1_CMPB_R (*((volatile uint32_t *)0x4002809C)) |
| #define | PWM0_1_GENA_R (*((volatile uint32_t *)0x400280A0)) |
| #define | PWM0_1_GENB_R (*((volatile uint32_t *)0x400280A4)) |
| #define | PWM0_1_DBCTL_R (*((volatile uint32_t *)0x400280A8)) |
| #define | PWM0_1_DBRISE_R (*((volatile uint32_t *)0x400280AC)) |
| #define | PWM0_1_DBFALL_R (*((volatile uint32_t *)0x400280B0)) |
| #define | PWM0_1_FLTSRC0_R (*((volatile uint32_t *)0x400280B4)) |
| #define | PWM0_1_FLTSRC1_R (*((volatile uint32_t *)0x400280B8)) |
| #define | PWM0_1_MINFLTPER_R (*((volatile uint32_t *)0x400280BC)) |
| #define | PWM0_2_CTL_R (*((volatile uint32_t *)0x400280C0)) |
| #define | PWM0_2_INTEN_R (*((volatile uint32_t *)0x400280C4)) |
| #define | PWM0_2_RIS_R (*((volatile uint32_t *)0x400280C8)) |
| #define | PWM0_2_ISC_R (*((volatile uint32_t *)0x400280CC)) |
| #define | PWM0_2_LOAD_R (*((volatile uint32_t *)0x400280D0)) |
| #define | PWM0_2_COUNT_R (*((volatile uint32_t *)0x400280D4)) |
| #define | PWM0_2_CMPA_R (*((volatile uint32_t *)0x400280D8)) |
| #define | PWM0_2_CMPB_R (*((volatile uint32_t *)0x400280DC)) |
| #define | PWM0_2_GENA_R (*((volatile uint32_t *)0x400280E0)) |
| #define | PWM0_2_GENB_R (*((volatile uint32_t *)0x400280E4)) |
| #define | PWM0_2_DBCTL_R (*((volatile uint32_t *)0x400280E8)) |
| #define | PWM0_2_DBRISE_R (*((volatile uint32_t *)0x400280EC)) |
| #define | PWM0_2_DBFALL_R (*((volatile uint32_t *)0x400280F0)) |
| #define | PWM0_2_FLTSRC0_R (*((volatile uint32_t *)0x400280F4)) |
| #define | PWM0_2_FLTSRC1_R (*((volatile uint32_t *)0x400280F8)) |
| #define | PWM0_2_MINFLTPER_R (*((volatile uint32_t *)0x400280FC)) |
| #define | PWM0_3_CTL_R (*((volatile uint32_t *)0x40028100)) |
| #define | PWM0_3_INTEN_R (*((volatile uint32_t *)0x40028104)) |
| #define | PWM0_3_RIS_R (*((volatile uint32_t *)0x40028108)) |
| #define | PWM0_3_ISC_R (*((volatile uint32_t *)0x4002810C)) |
| #define | PWM0_3_LOAD_R (*((volatile uint32_t *)0x40028110)) |
| #define | PWM0_3_COUNT_R (*((volatile uint32_t *)0x40028114)) |
| #define | PWM0_3_CMPA_R (*((volatile uint32_t *)0x40028118)) |
| #define | PWM0_3_CMPB_R (*((volatile uint32_t *)0x4002811C)) |
| #define | PWM0_3_GENA_R (*((volatile uint32_t *)0x40028120)) |
| #define | PWM0_3_GENB_R (*((volatile uint32_t *)0x40028124)) |
| #define | PWM0_3_DBCTL_R (*((volatile uint32_t *)0x40028128)) |
| #define | PWM0_3_DBRISE_R (*((volatile uint32_t *)0x4002812C)) |
| #define | PWM0_3_DBFALL_R (*((volatile uint32_t *)0x40028130)) |
| #define | PWM0_3_FLTSRC0_R (*((volatile uint32_t *)0x40028134)) |
| #define | PWM0_3_FLTSRC1_R (*((volatile uint32_t *)0x40028138)) |
| #define | PWM0_3_MINFLTPER_R (*((volatile uint32_t *)0x4002813C)) |
| #define | PWM0_0_FLTSEN_R (*((volatile uint32_t *)0x40028800)) |
| #define | PWM0_0_FLTSTAT0_R (*((volatile uint32_t *)0x40028804)) |
| #define | PWM0_0_FLTSTAT1_R (*((volatile uint32_t *)0x40028808)) |
| #define | PWM0_1_FLTSEN_R (*((volatile uint32_t *)0x40028880)) |
| #define | PWM0_1_FLTSTAT0_R (*((volatile uint32_t *)0x40028884)) |
| #define | PWM0_1_FLTSTAT1_R (*((volatile uint32_t *)0x40028888)) |
| #define | PWM0_2_FLTSEN_R (*((volatile uint32_t *)0x40028900)) |
| #define | PWM0_2_FLTSTAT0_R (*((volatile uint32_t *)0x40028904)) |
| #define | PWM0_2_FLTSTAT1_R (*((volatile uint32_t *)0x40028908)) |
| #define | PWM0_3_FLTSEN_R (*((volatile uint32_t *)0x40028980)) |
| #define | PWM0_3_FLTSTAT0_R (*((volatile uint32_t *)0x40028984)) |
| #define | PWM0_3_FLTSTAT1_R (*((volatile uint32_t *)0x40028988)) |
| #define | PWM0_PP_R (*((volatile uint32_t *)0x40028FC0)) |
| #define | PWM1_CTL_R (*((volatile uint32_t *)0x40029000)) |
| #define | PWM1_SYNC_R (*((volatile uint32_t *)0x40029004)) |
| #define | PWM1_ENABLE_R (*((volatile uint32_t *)0x40029008)) |
| #define | PWM1_INVERT_R (*((volatile uint32_t *)0x4002900C)) |
| #define | PWM1_FAULT_R (*((volatile uint32_t *)0x40029010)) |
| #define | PWM1_INTEN_R (*((volatile uint32_t *)0x40029014)) |
| #define | PWM1_RIS_R (*((volatile uint32_t *)0x40029018)) |
| #define | PWM1_ISC_R (*((volatile uint32_t *)0x4002901C)) |
| #define | PWM1_STATUS_R (*((volatile uint32_t *)0x40029020)) |
| #define | PWM1_FAULTVAL_R (*((volatile uint32_t *)0x40029024)) |
| #define | PWM1_ENUPD_R (*((volatile uint32_t *)0x40029028)) |
| #define | PWM1_0_CTL_R (*((volatile uint32_t *)0x40029040)) |
| #define | PWM1_0_INTEN_R (*((volatile uint32_t *)0x40029044)) |
| #define | PWM1_0_RIS_R (*((volatile uint32_t *)0x40029048)) |
| #define | PWM1_0_ISC_R (*((volatile uint32_t *)0x4002904C)) |
| #define | PWM1_0_LOAD_R (*((volatile uint32_t *)0x40029050)) |
| #define | PWM1_0_COUNT_R (*((volatile uint32_t *)0x40029054)) |
| #define | PWM1_0_CMPA_R (*((volatile uint32_t *)0x40029058)) |
| #define | PWM1_0_CMPB_R (*((volatile uint32_t *)0x4002905C)) |
| #define | PWM1_0_GENA_R (*((volatile uint32_t *)0x40029060)) |
| #define | PWM1_0_GENB_R (*((volatile uint32_t *)0x40029064)) |
| #define | PWM1_0_DBCTL_R (*((volatile uint32_t *)0x40029068)) |
| #define | PWM1_0_DBRISE_R (*((volatile uint32_t *)0x4002906C)) |
| #define | PWM1_0_DBFALL_R (*((volatile uint32_t *)0x40029070)) |
| #define | PWM1_0_FLTSRC0_R (*((volatile uint32_t *)0x40029074)) |
| #define | PWM1_0_FLTSRC1_R (*((volatile uint32_t *)0x40029078)) |
| #define | PWM1_0_MINFLTPER_R (*((volatile uint32_t *)0x4002907C)) |
| #define | PWM1_1_CTL_R (*((volatile uint32_t *)0x40029080)) |
| #define | PWM1_1_INTEN_R (*((volatile uint32_t *)0x40029084)) |
| #define | PWM1_1_RIS_R (*((volatile uint32_t *)0x40029088)) |
| #define | PWM1_1_ISC_R (*((volatile uint32_t *)0x4002908C)) |
| #define | PWM1_1_LOAD_R (*((volatile uint32_t *)0x40029090)) |
| #define | PWM1_1_COUNT_R (*((volatile uint32_t *)0x40029094)) |
| #define | PWM1_1_CMPA_R (*((volatile uint32_t *)0x40029098)) |
| #define | PWM1_1_CMPB_R (*((volatile uint32_t *)0x4002909C)) |
| #define | PWM1_1_GENA_R (*((volatile uint32_t *)0x400290A0)) |
| #define | PWM1_1_GENB_R (*((volatile uint32_t *)0x400290A4)) |
| #define | PWM1_1_DBCTL_R (*((volatile uint32_t *)0x400290A8)) |
| #define | PWM1_1_DBRISE_R (*((volatile uint32_t *)0x400290AC)) |
| #define | PWM1_1_DBFALL_R (*((volatile uint32_t *)0x400290B0)) |
| #define | PWM1_1_FLTSRC0_R (*((volatile uint32_t *)0x400290B4)) |
| #define | PWM1_1_FLTSRC1_R (*((volatile uint32_t *)0x400290B8)) |
| #define | PWM1_1_MINFLTPER_R (*((volatile uint32_t *)0x400290BC)) |
| #define | PWM1_2_CTL_R (*((volatile uint32_t *)0x400290C0)) |
| #define | PWM1_2_INTEN_R (*((volatile uint32_t *)0x400290C4)) |
| #define | PWM1_2_RIS_R (*((volatile uint32_t *)0x400290C8)) |
| #define | PWM1_2_ISC_R (*((volatile uint32_t *)0x400290CC)) |
| #define | PWM1_2_LOAD_R (*((volatile uint32_t *)0x400290D0)) |
| #define | PWM1_2_COUNT_R (*((volatile uint32_t *)0x400290D4)) |
| #define | PWM1_2_CMPA_R (*((volatile uint32_t *)0x400290D8)) |
| #define | PWM1_2_CMPB_R (*((volatile uint32_t *)0x400290DC)) |
| #define | PWM1_2_GENA_R (*((volatile uint32_t *)0x400290E0)) |
| #define | PWM1_2_GENB_R (*((volatile uint32_t *)0x400290E4)) |
| #define | PWM1_2_DBCTL_R (*((volatile uint32_t *)0x400290E8)) |
| #define | PWM1_2_DBRISE_R (*((volatile uint32_t *)0x400290EC)) |
| #define | PWM1_2_DBFALL_R (*((volatile uint32_t *)0x400290F0)) |
| #define | PWM1_2_FLTSRC0_R (*((volatile uint32_t *)0x400290F4)) |
| #define | PWM1_2_FLTSRC1_R (*((volatile uint32_t *)0x400290F8)) |
| #define | PWM1_2_MINFLTPER_R (*((volatile uint32_t *)0x400290FC)) |
| #define | PWM1_3_CTL_R (*((volatile uint32_t *)0x40029100)) |
| #define | PWM1_3_INTEN_R (*((volatile uint32_t *)0x40029104)) |
| #define | PWM1_3_RIS_R (*((volatile uint32_t *)0x40029108)) |
| #define | PWM1_3_ISC_R (*((volatile uint32_t *)0x4002910C)) |
| #define | PWM1_3_LOAD_R (*((volatile uint32_t *)0x40029110)) |
| #define | PWM1_3_COUNT_R (*((volatile uint32_t *)0x40029114)) |
| #define | PWM1_3_CMPA_R (*((volatile uint32_t *)0x40029118)) |
| #define | PWM1_3_CMPB_R (*((volatile uint32_t *)0x4002911C)) |
| #define | PWM1_3_GENA_R (*((volatile uint32_t *)0x40029120)) |
| #define | PWM1_3_GENB_R (*((volatile uint32_t *)0x40029124)) |
| #define | PWM1_3_DBCTL_R (*((volatile uint32_t *)0x40029128)) |
| #define | PWM1_3_DBRISE_R (*((volatile uint32_t *)0x4002912C)) |
| #define | PWM1_3_DBFALL_R (*((volatile uint32_t *)0x40029130)) |
| #define | PWM1_3_FLTSRC0_R (*((volatile uint32_t *)0x40029134)) |
| #define | PWM1_3_FLTSRC1_R (*((volatile uint32_t *)0x40029138)) |
| #define | PWM1_3_MINFLTPER_R (*((volatile uint32_t *)0x4002913C)) |
| #define | PWM1_0_FLTSEN_R (*((volatile uint32_t *)0x40029800)) |
| #define | PWM1_0_FLTSTAT0_R (*((volatile uint32_t *)0x40029804)) |
| #define | PWM1_0_FLTSTAT1_R (*((volatile uint32_t *)0x40029808)) |
| #define | PWM1_1_FLTSEN_R (*((volatile uint32_t *)0x40029880)) |
| #define | PWM1_1_FLTSTAT0_R (*((volatile uint32_t *)0x40029884)) |
| #define | PWM1_1_FLTSTAT1_R (*((volatile uint32_t *)0x40029888)) |
| #define | PWM1_2_FLTSEN_R (*((volatile uint32_t *)0x40029900)) |
| #define | PWM1_2_FLTSTAT0_R (*((volatile uint32_t *)0x40029904)) |
| #define | PWM1_2_FLTSTAT1_R (*((volatile uint32_t *)0x40029908)) |
| #define | PWM1_3_FLTSEN_R (*((volatile uint32_t *)0x40029980)) |
| #define | PWM1_3_FLTSTAT0_R (*((volatile uint32_t *)0x40029984)) |
| #define | PWM1_3_FLTSTAT1_R (*((volatile uint32_t *)0x40029988)) |
| #define | PWM1_PP_R (*((volatile uint32_t *)0x40029FC0)) |
| #define | QEI0_CTL_R (*((volatile uint32_t *)0x4002C000)) |
| #define | QEI0_STAT_R (*((volatile uint32_t *)0x4002C004)) |
| #define | QEI0_POS_R (*((volatile uint32_t *)0x4002C008)) |
| #define | QEI0_MAXPOS_R (*((volatile uint32_t *)0x4002C00C)) |
| #define | QEI0_LOAD_R (*((volatile uint32_t *)0x4002C010)) |
| #define | QEI0_TIME_R (*((volatile uint32_t *)0x4002C014)) |
| #define | QEI0_COUNT_R (*((volatile uint32_t *)0x4002C018)) |
| #define | QEI0_SPEED_R (*((volatile uint32_t *)0x4002C01C)) |
| #define | QEI0_INTEN_R (*((volatile uint32_t *)0x4002C020)) |
| #define | QEI0_RIS_R (*((volatile uint32_t *)0x4002C024)) |
| #define | QEI0_ISC_R (*((volatile uint32_t *)0x4002C028)) |
| #define | QEI1_CTL_R (*((volatile uint32_t *)0x4002D000)) |
| #define | QEI1_STAT_R (*((volatile uint32_t *)0x4002D004)) |
| #define | QEI1_POS_R (*((volatile uint32_t *)0x4002D008)) |
| #define | QEI1_MAXPOS_R (*((volatile uint32_t *)0x4002D00C)) |
| #define | QEI1_LOAD_R (*((volatile uint32_t *)0x4002D010)) |
| #define | QEI1_TIME_R (*((volatile uint32_t *)0x4002D014)) |
| #define | QEI1_COUNT_R (*((volatile uint32_t *)0x4002D018)) |
| #define | QEI1_SPEED_R (*((volatile uint32_t *)0x4002D01C)) |
| #define | QEI1_INTEN_R (*((volatile uint32_t *)0x4002D020)) |
| #define | QEI1_RIS_R (*((volatile uint32_t *)0x4002D024)) |
| #define | QEI1_ISC_R (*((volatile uint32_t *)0x4002D028)) |
| #define | TIMER0_CFG_R (*((volatile uint32_t *)0x40030000)) |
| #define | TIMER0_TAMR_R (*((volatile uint32_t *)0x40030004)) |
| #define | TIMER0_TBMR_R (*((volatile uint32_t *)0x40030008)) |
| #define | TIMER0_CTL_R (*((volatile uint32_t *)0x4003000C)) |
| #define | TIMER0_SYNC_R (*((volatile uint32_t *)0x40030010)) |
| #define | TIMER0_IMR_R (*((volatile uint32_t *)0x40030018)) |
| #define | TIMER0_RIS_R (*((volatile uint32_t *)0x4003001C)) |
| #define | TIMER0_MIS_R (*((volatile uint32_t *)0x40030020)) |
| #define | TIMER0_ICR_R (*((volatile uint32_t *)0x40030024)) |
| #define | TIMER0_TAILR_R (*((volatile uint32_t *)0x40030028)) |
| #define | TIMER0_TBILR_R (*((volatile uint32_t *)0x4003002C)) |
| #define | TIMER0_TAMATCHR_R (*((volatile uint32_t *)0x40030030)) |
| #define | TIMER0_TBMATCHR_R (*((volatile uint32_t *)0x40030034)) |
| #define | TIMER0_TAPR_R (*((volatile uint32_t *)0x40030038)) |
| #define | TIMER0_TBPR_R (*((volatile uint32_t *)0x4003003C)) |
| #define | TIMER0_TAPMR_R (*((volatile uint32_t *)0x40030040)) |
| #define | TIMER0_TBPMR_R (*((volatile uint32_t *)0x40030044)) |
| #define | TIMER0_TAR_R (*((volatile uint32_t *)0x40030048)) |
| #define | TIMER0_TBR_R (*((volatile uint32_t *)0x4003004C)) |
| #define | TIMER0_TAV_R (*((volatile uint32_t *)0x40030050)) |
| #define | TIMER0_TBV_R (*((volatile uint32_t *)0x40030054)) |
| #define | TIMER0_RTCPD_R (*((volatile uint32_t *)0x40030058)) |
| #define | TIMER0_TAPS_R (*((volatile uint32_t *)0x4003005C)) |
| #define | TIMER0_TBPS_R (*((volatile uint32_t *)0x40030060)) |
| #define | TIMER0_TAPV_R (*((volatile uint32_t *)0x40030064)) |
| #define | TIMER0_TBPV_R (*((volatile uint32_t *)0x40030068)) |
| #define | TIMER0_PP_R (*((volatile uint32_t *)0x40030FC0)) |
| #define | TIMER1_CFG_R (*((volatile uint32_t *)0x40031000)) |
| #define | TIMER1_TAMR_R (*((volatile uint32_t *)0x40031004)) |
| #define | TIMER1_TBMR_R (*((volatile uint32_t *)0x40031008)) |
| #define | TIMER1_CTL_R (*((volatile uint32_t *)0x4003100C)) |
| #define | TIMER1_SYNC_R (*((volatile uint32_t *)0x40031010)) |
| #define | TIMER1_IMR_R (*((volatile uint32_t *)0x40031018)) |
| #define | TIMER1_RIS_R (*((volatile uint32_t *)0x4003101C)) |
| #define | TIMER1_MIS_R (*((volatile uint32_t *)0x40031020)) |
| #define | TIMER1_ICR_R (*((volatile uint32_t *)0x40031024)) |
| #define | TIMER1_TAILR_R (*((volatile uint32_t *)0x40031028)) |
| #define | TIMER1_TBILR_R (*((volatile uint32_t *)0x4003102C)) |
| #define | TIMER1_TAMATCHR_R (*((volatile uint32_t *)0x40031030)) |
| #define | TIMER1_TBMATCHR_R (*((volatile uint32_t *)0x40031034)) |
| #define | TIMER1_TAPR_R (*((volatile uint32_t *)0x40031038)) |
| #define | TIMER1_TBPR_R (*((volatile uint32_t *)0x4003103C)) |
| #define | TIMER1_TAPMR_R (*((volatile uint32_t *)0x40031040)) |
| #define | TIMER1_TBPMR_R (*((volatile uint32_t *)0x40031044)) |
| #define | TIMER1_TAR_R (*((volatile uint32_t *)0x40031048)) |
| #define | TIMER1_TBR_R (*((volatile uint32_t *)0x4003104C)) |
| #define | TIMER1_TAV_R (*((volatile uint32_t *)0x40031050)) |
| #define | TIMER1_TBV_R (*((volatile uint32_t *)0x40031054)) |
| #define | TIMER1_RTCPD_R (*((volatile uint32_t *)0x40031058)) |
| #define | TIMER1_TAPS_R (*((volatile uint32_t *)0x4003105C)) |
| #define | TIMER1_TBPS_R (*((volatile uint32_t *)0x40031060)) |
| #define | TIMER1_TAPV_R (*((volatile uint32_t *)0x40031064)) |
| #define | TIMER1_TBPV_R (*((volatile uint32_t *)0x40031068)) |
| #define | TIMER1_PP_R (*((volatile uint32_t *)0x40031FC0)) |
| #define | TIMER2_CFG_R (*((volatile uint32_t *)0x40032000)) |
| #define | TIMER2_TAMR_R (*((volatile uint32_t *)0x40032004)) |
| #define | TIMER2_TBMR_R (*((volatile uint32_t *)0x40032008)) |
| #define | TIMER2_CTL_R (*((volatile uint32_t *)0x4003200C)) |
| #define | TIMER2_SYNC_R (*((volatile uint32_t *)0x40032010)) |
| #define | TIMER2_IMR_R (*((volatile uint32_t *)0x40032018)) |
| #define | TIMER2_RIS_R (*((volatile uint32_t *)0x4003201C)) |
| #define | TIMER2_MIS_R (*((volatile uint32_t *)0x40032020)) |
| #define | TIMER2_ICR_R (*((volatile uint32_t *)0x40032024)) |
| #define | TIMER2_TAILR_R (*((volatile uint32_t *)0x40032028)) |
| #define | TIMER2_TBILR_R (*((volatile uint32_t *)0x4003202C)) |
| #define | TIMER2_TAMATCHR_R (*((volatile uint32_t *)0x40032030)) |
| #define | TIMER2_TBMATCHR_R (*((volatile uint32_t *)0x40032034)) |
| #define | TIMER2_TAPR_R (*((volatile uint32_t *)0x40032038)) |
| #define | TIMER2_TBPR_R (*((volatile uint32_t *)0x4003203C)) |
| #define | TIMER2_TAPMR_R (*((volatile uint32_t *)0x40032040)) |
| #define | TIMER2_TBPMR_R (*((volatile uint32_t *)0x40032044)) |
| #define | TIMER2_TAR_R (*((volatile uint32_t *)0x40032048)) |
| #define | TIMER2_TBR_R (*((volatile uint32_t *)0x4003204C)) |
| #define | TIMER2_TAV_R (*((volatile uint32_t *)0x40032050)) |
| #define | TIMER2_TBV_R (*((volatile uint32_t *)0x40032054)) |
| #define | TIMER2_RTCPD_R (*((volatile uint32_t *)0x40032058)) |
| #define | TIMER2_TAPS_R (*((volatile uint32_t *)0x4003205C)) |
| #define | TIMER2_TBPS_R (*((volatile uint32_t *)0x40032060)) |
| #define | TIMER2_TAPV_R (*((volatile uint32_t *)0x40032064)) |
| #define | TIMER2_TBPV_R (*((volatile uint32_t *)0x40032068)) |
| #define | TIMER2_PP_R (*((volatile uint32_t *)0x40032FC0)) |
| #define | TIMER3_CFG_R (*((volatile uint32_t *)0x40033000)) |
| #define | TIMER3_TAMR_R (*((volatile uint32_t *)0x40033004)) |
| #define | TIMER3_TBMR_R (*((volatile uint32_t *)0x40033008)) |
| #define | TIMER3_CTL_R (*((volatile uint32_t *)0x4003300C)) |
| #define | TIMER3_SYNC_R (*((volatile uint32_t *)0x40033010)) |
| #define | TIMER3_IMR_R (*((volatile uint32_t *)0x40033018)) |
| #define | TIMER3_RIS_R (*((volatile uint32_t *)0x4003301C)) |
| #define | TIMER3_MIS_R (*((volatile uint32_t *)0x40033020)) |
| #define | TIMER3_ICR_R (*((volatile uint32_t *)0x40033024)) |
| #define | TIMER3_TAILR_R (*((volatile uint32_t *)0x40033028)) |
| #define | TIMER3_TBILR_R (*((volatile uint32_t *)0x4003302C)) |
| #define | TIMER3_TAMATCHR_R (*((volatile uint32_t *)0x40033030)) |
| #define | TIMER3_TBMATCHR_R (*((volatile uint32_t *)0x40033034)) |
| #define | TIMER3_TAPR_R (*((volatile uint32_t *)0x40033038)) |
| #define | TIMER3_TBPR_R (*((volatile uint32_t *)0x4003303C)) |
| #define | TIMER3_TAPMR_R (*((volatile uint32_t *)0x40033040)) |
| #define | TIMER3_TBPMR_R (*((volatile uint32_t *)0x40033044)) |
| #define | TIMER3_TAR_R (*((volatile uint32_t *)0x40033048)) |
| #define | TIMER3_TBR_R (*((volatile uint32_t *)0x4003304C)) |
| #define | TIMER3_TAV_R (*((volatile uint32_t *)0x40033050)) |
| #define | TIMER3_TBV_R (*((volatile uint32_t *)0x40033054)) |
| #define | TIMER3_RTCPD_R (*((volatile uint32_t *)0x40033058)) |
| #define | TIMER3_TAPS_R (*((volatile uint32_t *)0x4003305C)) |
| #define | TIMER3_TBPS_R (*((volatile uint32_t *)0x40033060)) |
| #define | TIMER3_TAPV_R (*((volatile uint32_t *)0x40033064)) |
| #define | TIMER3_TBPV_R (*((volatile uint32_t *)0x40033068)) |
| #define | TIMER3_PP_R (*((volatile uint32_t *)0x40033FC0)) |
| #define | TIMER4_CFG_R (*((volatile uint32_t *)0x40034000)) |
| #define | TIMER4_TAMR_R (*((volatile uint32_t *)0x40034004)) |
| #define | TIMER4_TBMR_R (*((volatile uint32_t *)0x40034008)) |
| #define | TIMER4_CTL_R (*((volatile uint32_t *)0x4003400C)) |
| #define | TIMER4_SYNC_R (*((volatile uint32_t *)0x40034010)) |
| #define | TIMER4_IMR_R (*((volatile uint32_t *)0x40034018)) |
| #define | TIMER4_RIS_R (*((volatile uint32_t *)0x4003401C)) |
| #define | TIMER4_MIS_R (*((volatile uint32_t *)0x40034020)) |
| #define | TIMER4_ICR_R (*((volatile uint32_t *)0x40034024)) |
| #define | TIMER4_TAILR_R (*((volatile uint32_t *)0x40034028)) |
| #define | TIMER4_TBILR_R (*((volatile uint32_t *)0x4003402C)) |
| #define | TIMER4_TAMATCHR_R (*((volatile uint32_t *)0x40034030)) |
| #define | TIMER4_TBMATCHR_R (*((volatile uint32_t *)0x40034034)) |
| #define | TIMER4_TAPR_R (*((volatile uint32_t *)0x40034038)) |
| #define | TIMER4_TBPR_R (*((volatile uint32_t *)0x4003403C)) |
| #define | TIMER4_TAPMR_R (*((volatile uint32_t *)0x40034040)) |
| #define | TIMER4_TBPMR_R (*((volatile uint32_t *)0x40034044)) |
| #define | TIMER4_TAR_R (*((volatile uint32_t *)0x40034048)) |
| #define | TIMER4_TBR_R (*((volatile uint32_t *)0x4003404C)) |
| #define | TIMER4_TAV_R (*((volatile uint32_t *)0x40034050)) |
| #define | TIMER4_TBV_R (*((volatile uint32_t *)0x40034054)) |
| #define | TIMER4_RTCPD_R (*((volatile uint32_t *)0x40034058)) |
| #define | TIMER4_TAPS_R (*((volatile uint32_t *)0x4003405C)) |
| #define | TIMER4_TBPS_R (*((volatile uint32_t *)0x40034060)) |
| #define | TIMER4_TAPV_R (*((volatile uint32_t *)0x40034064)) |
| #define | TIMER4_TBPV_R (*((volatile uint32_t *)0x40034068)) |
| #define | TIMER4_PP_R (*((volatile uint32_t *)0x40034FC0)) |
| #define | TIMER5_CFG_R (*((volatile uint32_t *)0x40035000)) |
| #define | TIMER5_TAMR_R (*((volatile uint32_t *)0x40035004)) |
| #define | TIMER5_TBMR_R (*((volatile uint32_t *)0x40035008)) |
| #define | TIMER5_CTL_R (*((volatile uint32_t *)0x4003500C)) |
| #define | TIMER5_SYNC_R (*((volatile uint32_t *)0x40035010)) |
| #define | TIMER5_IMR_R (*((volatile uint32_t *)0x40035018)) |
| #define | TIMER5_RIS_R (*((volatile uint32_t *)0x4003501C)) |
| #define | TIMER5_MIS_R (*((volatile uint32_t *)0x40035020)) |
| #define | TIMER5_ICR_R (*((volatile uint32_t *)0x40035024)) |
| #define | TIMER5_TAILR_R (*((volatile uint32_t *)0x40035028)) |
| #define | TIMER5_TBILR_R (*((volatile uint32_t *)0x4003502C)) |
| #define | TIMER5_TAMATCHR_R (*((volatile uint32_t *)0x40035030)) |
| #define | TIMER5_TBMATCHR_R (*((volatile uint32_t *)0x40035034)) |
| #define | TIMER5_TAPR_R (*((volatile uint32_t *)0x40035038)) |
| #define | TIMER5_TBPR_R (*((volatile uint32_t *)0x4003503C)) |
| #define | TIMER5_TAPMR_R (*((volatile uint32_t *)0x40035040)) |
| #define | TIMER5_TBPMR_R (*((volatile uint32_t *)0x40035044)) |
| #define | TIMER5_TAR_R (*((volatile uint32_t *)0x40035048)) |
| #define | TIMER5_TBR_R (*((volatile uint32_t *)0x4003504C)) |
| #define | TIMER5_TAV_R (*((volatile uint32_t *)0x40035050)) |
| #define | TIMER5_TBV_R (*((volatile uint32_t *)0x40035054)) |
| #define | TIMER5_RTCPD_R (*((volatile uint32_t *)0x40035058)) |
| #define | TIMER5_TAPS_R (*((volatile uint32_t *)0x4003505C)) |
| #define | TIMER5_TBPS_R (*((volatile uint32_t *)0x40035060)) |
| #define | TIMER5_TAPV_R (*((volatile uint32_t *)0x40035064)) |
| #define | TIMER5_TBPV_R (*((volatile uint32_t *)0x40035068)) |
| #define | TIMER5_PP_R (*((volatile uint32_t *)0x40035FC0)) |
| #define | WTIMER0_CFG_R (*((volatile uint32_t *)0x40036000)) |
| #define | WTIMER0_TAMR_R (*((volatile uint32_t *)0x40036004)) |
| #define | WTIMER0_TBMR_R (*((volatile uint32_t *)0x40036008)) |
| #define | WTIMER0_CTL_R (*((volatile uint32_t *)0x4003600C)) |
| #define | WTIMER0_SYNC_R (*((volatile uint32_t *)0x40036010)) |
| #define | WTIMER0_IMR_R (*((volatile uint32_t *)0x40036018)) |
| #define | WTIMER0_RIS_R (*((volatile uint32_t *)0x4003601C)) |
| #define | WTIMER0_MIS_R (*((volatile uint32_t *)0x40036020)) |
| #define | WTIMER0_ICR_R (*((volatile uint32_t *)0x40036024)) |
| #define | WTIMER0_TAILR_R (*((volatile uint32_t *)0x40036028)) |
| #define | WTIMER0_TBILR_R (*((volatile uint32_t *)0x4003602C)) |
| #define | WTIMER0_TAMATCHR_R (*((volatile uint32_t *)0x40036030)) |
| #define | WTIMER0_TBMATCHR_R (*((volatile uint32_t *)0x40036034)) |
| #define | WTIMER0_TAPR_R (*((volatile uint32_t *)0x40036038)) |
| #define | WTIMER0_TBPR_R (*((volatile uint32_t *)0x4003603C)) |
| #define | WTIMER0_TAPMR_R (*((volatile uint32_t *)0x40036040)) |
| #define | WTIMER0_TBPMR_R (*((volatile uint32_t *)0x40036044)) |
| #define | WTIMER0_TAR_R (*((volatile uint32_t *)0x40036048)) |
| #define | WTIMER0_TBR_R (*((volatile uint32_t *)0x4003604C)) |
| #define | WTIMER0_TAV_R (*((volatile uint32_t *)0x40036050)) |
| #define | WTIMER0_TBV_R (*((volatile uint32_t *)0x40036054)) |
| #define | WTIMER0_RTCPD_R (*((volatile uint32_t *)0x40036058)) |
| #define | WTIMER0_TAPS_R (*((volatile uint32_t *)0x4003605C)) |
| #define | WTIMER0_TBPS_R (*((volatile uint32_t *)0x40036060)) |
| #define | WTIMER0_TAPV_R (*((volatile uint32_t *)0x40036064)) |
| #define | WTIMER0_TBPV_R (*((volatile uint32_t *)0x40036068)) |
| #define | WTIMER0_PP_R (*((volatile uint32_t *)0x40036FC0)) |
| #define | WTIMER1_CFG_R (*((volatile uint32_t *)0x40037000)) |
| #define | WTIMER1_TAMR_R (*((volatile uint32_t *)0x40037004)) |
| #define | WTIMER1_TBMR_R (*((volatile uint32_t *)0x40037008)) |
| #define | WTIMER1_CTL_R (*((volatile uint32_t *)0x4003700C)) |
| #define | WTIMER1_SYNC_R (*((volatile uint32_t *)0x40037010)) |
| #define | WTIMER1_IMR_R (*((volatile uint32_t *)0x40037018)) |
| #define | WTIMER1_RIS_R (*((volatile uint32_t *)0x4003701C)) |
| #define | WTIMER1_MIS_R (*((volatile uint32_t *)0x40037020)) |
| #define | WTIMER1_ICR_R (*((volatile uint32_t *)0x40037024)) |
| #define | WTIMER1_TAILR_R (*((volatile uint32_t *)0x40037028)) |
| #define | WTIMER1_TBILR_R (*((volatile uint32_t *)0x4003702C)) |
| #define | WTIMER1_TAMATCHR_R (*((volatile uint32_t *)0x40037030)) |
| #define | WTIMER1_TBMATCHR_R (*((volatile uint32_t *)0x40037034)) |
| #define | WTIMER1_TAPR_R (*((volatile uint32_t *)0x40037038)) |
| #define | WTIMER1_TBPR_R (*((volatile uint32_t *)0x4003703C)) |
| #define | WTIMER1_TAPMR_R (*((volatile uint32_t *)0x40037040)) |
| #define | WTIMER1_TBPMR_R (*((volatile uint32_t *)0x40037044)) |
| #define | WTIMER1_TAR_R (*((volatile uint32_t *)0x40037048)) |
| #define | WTIMER1_TBR_R (*((volatile uint32_t *)0x4003704C)) |
| #define | WTIMER1_TAV_R (*((volatile uint32_t *)0x40037050)) |
| #define | WTIMER1_TBV_R (*((volatile uint32_t *)0x40037054)) |
| #define | WTIMER1_RTCPD_R (*((volatile uint32_t *)0x40037058)) |
| #define | WTIMER1_TAPS_R (*((volatile uint32_t *)0x4003705C)) |
| #define | WTIMER1_TBPS_R (*((volatile uint32_t *)0x40037060)) |
| #define | WTIMER1_TAPV_R (*((volatile uint32_t *)0x40037064)) |
| #define | WTIMER1_TBPV_R (*((volatile uint32_t *)0x40037068)) |
| #define | WTIMER1_PP_R (*((volatile uint32_t *)0x40037FC0)) |
| #define | ADC0_ACTSS_R (*((volatile uint32_t *)0x40038000)) |
| #define | ADC0_RIS_R (*((volatile uint32_t *)0x40038004)) |
| #define | ADC0_IM_R (*((volatile uint32_t *)0x40038008)) |
| #define | ADC0_ISC_R (*((volatile uint32_t *)0x4003800C)) |
| #define | ADC0_OSTAT_R (*((volatile uint32_t *)0x40038010)) |
| #define | ADC0_EMUX_R (*((volatile uint32_t *)0x40038014)) |
| #define | ADC0_USTAT_R (*((volatile uint32_t *)0x40038018)) |
| #define | ADC0_TSSEL_R (*((volatile uint32_t *)0x4003801C)) |
| #define | ADC0_SSPRI_R (*((volatile uint32_t *)0x40038020)) |
| #define | ADC0_SPC_R (*((volatile uint32_t *)0x40038024)) |
| #define | ADC0_PSSI_R (*((volatile uint32_t *)0x40038028)) |
| #define | ADC0_SAC_R (*((volatile uint32_t *)0x40038030)) |
| #define | ADC0_DCISC_R (*((volatile uint32_t *)0x40038034)) |
| #define | ADC0_CTL_R (*((volatile uint32_t *)0x40038038)) |
| #define | ADC0_SSMUX0_R (*((volatile uint32_t *)0x40038040)) |
| #define | ADC0_SSCTL0_R (*((volatile uint32_t *)0x40038044)) |
| #define | ADC0_SSFIFO0_R (*((volatile uint32_t *)0x40038048)) |
| #define | ADC0_SSFSTAT0_R (*((volatile uint32_t *)0x4003804C)) |
| #define | ADC0_SSOP0_R (*((volatile uint32_t *)0x40038050)) |
| #define | ADC0_SSDC0_R (*((volatile uint32_t *)0x40038054)) |
| #define | ADC0_SSEMUX0_R (*((volatile uint32_t *)0x40038058)) |
| #define | ADC0_SSMUX1_R (*((volatile uint32_t *)0x40038060)) |
| #define | ADC0_SSCTL1_R (*((volatile uint32_t *)0x40038064)) |
| #define | ADC0_SSFIFO1_R (*((volatile uint32_t *)0x40038068)) |
| #define | ADC0_SSFSTAT1_R (*((volatile uint32_t *)0x4003806C)) |
| #define | ADC0_SSOP1_R (*((volatile uint32_t *)0x40038070)) |
| #define | ADC0_SSDC1_R (*((volatile uint32_t *)0x40038074)) |
| #define | ADC0_SSEMUX1_R (*((volatile uint32_t *)0x40038078)) |
| #define | ADC0_SSMUX2_R (*((volatile uint32_t *)0x40038080)) |
| #define | ADC0_SSCTL2_R (*((volatile uint32_t *)0x40038084)) |
| #define | ADC0_SSFIFO2_R (*((volatile uint32_t *)0x40038088)) |
| #define | ADC0_SSFSTAT2_R (*((volatile uint32_t *)0x4003808C)) |
| #define | ADC0_SSOP2_R (*((volatile uint32_t *)0x40038090)) |
| #define | ADC0_SSDC2_R (*((volatile uint32_t *)0x40038094)) |
| #define | ADC0_SSEMUX2_R (*((volatile uint32_t *)0x40038098)) |
| #define | ADC0_SSMUX3_R (*((volatile uint32_t *)0x400380A0)) |
| #define | ADC0_SSCTL3_R (*((volatile uint32_t *)0x400380A4)) |
| #define | ADC0_SSFIFO3_R (*((volatile uint32_t *)0x400380A8)) |
| #define | ADC0_SSFSTAT3_R (*((volatile uint32_t *)0x400380AC)) |
| #define | ADC0_SSOP3_R (*((volatile uint32_t *)0x400380B0)) |
| #define | ADC0_SSDC3_R (*((volatile uint32_t *)0x400380B4)) |
| #define | ADC0_SSEMUX3_R (*((volatile uint32_t *)0x400380B8)) |
| #define | ADC0_DCRIC_R (*((volatile uint32_t *)0x40038D00)) |
| #define | ADC0_DCCTL0_R (*((volatile uint32_t *)0x40038E00)) |
| #define | ADC0_DCCTL1_R (*((volatile uint32_t *)0x40038E04)) |
| #define | ADC0_DCCTL2_R (*((volatile uint32_t *)0x40038E08)) |
| #define | ADC0_DCCTL3_R (*((volatile uint32_t *)0x40038E0C)) |
| #define | ADC0_DCCTL4_R (*((volatile uint32_t *)0x40038E10)) |
| #define | ADC0_DCCTL5_R (*((volatile uint32_t *)0x40038E14)) |
| #define | ADC0_DCCTL6_R (*((volatile uint32_t *)0x40038E18)) |
| #define | ADC0_DCCTL7_R (*((volatile uint32_t *)0x40038E1C)) |
| #define | ADC0_DCCMP0_R (*((volatile uint32_t *)0x40038E40)) |
| #define | ADC0_DCCMP1_R (*((volatile uint32_t *)0x40038E44)) |
| #define | ADC0_DCCMP2_R (*((volatile uint32_t *)0x40038E48)) |
| #define | ADC0_DCCMP3_R (*((volatile uint32_t *)0x40038E4C)) |
| #define | ADC0_DCCMP4_R (*((volatile uint32_t *)0x40038E50)) |
| #define | ADC0_DCCMP5_R (*((volatile uint32_t *)0x40038E54)) |
| #define | ADC0_DCCMP6_R (*((volatile uint32_t *)0x40038E58)) |
| #define | ADC0_DCCMP7_R (*((volatile uint32_t *)0x40038E5C)) |
| #define | ADC0_PP_R (*((volatile uint32_t *)0x40038FC0)) |
| #define | ADC0_PC_R (*((volatile uint32_t *)0x40038FC4)) |
| #define | ADC0_CC_R (*((volatile uint32_t *)0x40038FC8)) |
| #define | ADC1_ACTSS_R (*((volatile uint32_t *)0x40039000)) |
| #define | ADC1_RIS_R (*((volatile uint32_t *)0x40039004)) |
| #define | ADC1_IM_R (*((volatile uint32_t *)0x40039008)) |
| #define | ADC1_ISC_R (*((volatile uint32_t *)0x4003900C)) |
| #define | ADC1_OSTAT_R (*((volatile uint32_t *)0x40039010)) |
| #define | ADC1_EMUX_R (*((volatile uint32_t *)0x40039014)) |
| #define | ADC1_USTAT_R (*((volatile uint32_t *)0x40039018)) |
| #define | ADC1_TSSEL_R (*((volatile uint32_t *)0x4003901C)) |
| #define | ADC1_SSPRI_R (*((volatile uint32_t *)0x40039020)) |
| #define | ADC1_SPC_R (*((volatile uint32_t *)0x40039024)) |
| #define | ADC1_PSSI_R (*((volatile uint32_t *)0x40039028)) |
| #define | ADC1_SAC_R (*((volatile uint32_t *)0x40039030)) |
| #define | ADC1_DCISC_R (*((volatile uint32_t *)0x40039034)) |
| #define | ADC1_CTL_R (*((volatile uint32_t *)0x40039038)) |
| #define | ADC1_SSMUX0_R (*((volatile uint32_t *)0x40039040)) |
| #define | ADC1_SSCTL0_R (*((volatile uint32_t *)0x40039044)) |
| #define | ADC1_SSFIFO0_R (*((volatile uint32_t *)0x40039048)) |
| #define | ADC1_SSFSTAT0_R (*((volatile uint32_t *)0x4003904C)) |
| #define | ADC1_SSOP0_R (*((volatile uint32_t *)0x40039050)) |
| #define | ADC1_SSDC0_R (*((volatile uint32_t *)0x40039054)) |
| #define | ADC1_SSEMUX0_R (*((volatile uint32_t *)0x40039058)) |
| #define | ADC1_SSMUX1_R (*((volatile uint32_t *)0x40039060)) |
| #define | ADC1_SSCTL1_R (*((volatile uint32_t *)0x40039064)) |
| #define | ADC1_SSFIFO1_R (*((volatile uint32_t *)0x40039068)) |
| #define | ADC1_SSFSTAT1_R (*((volatile uint32_t *)0x4003906C)) |
| #define | ADC1_SSOP1_R (*((volatile uint32_t *)0x40039070)) |
| #define | ADC1_SSDC1_R (*((volatile uint32_t *)0x40039074)) |
| #define | ADC1_SSEMUX1_R (*((volatile uint32_t *)0x40039078)) |
| #define | ADC1_SSMUX2_R (*((volatile uint32_t *)0x40039080)) |
| #define | ADC1_SSCTL2_R (*((volatile uint32_t *)0x40039084)) |
| #define | ADC1_SSFIFO2_R (*((volatile uint32_t *)0x40039088)) |
| #define | ADC1_SSFSTAT2_R (*((volatile uint32_t *)0x4003908C)) |
| #define | ADC1_SSOP2_R (*((volatile uint32_t *)0x40039090)) |
| #define | ADC1_SSDC2_R (*((volatile uint32_t *)0x40039094)) |
| #define | ADC1_SSEMUX2_R (*((volatile uint32_t *)0x40039098)) |
| #define | ADC1_SSMUX3_R (*((volatile uint32_t *)0x400390A0)) |
| #define | ADC1_SSCTL3_R (*((volatile uint32_t *)0x400390A4)) |
| #define | ADC1_SSFIFO3_R (*((volatile uint32_t *)0x400390A8)) |
| #define | ADC1_SSFSTAT3_R (*((volatile uint32_t *)0x400390AC)) |
| #define | ADC1_SSOP3_R (*((volatile uint32_t *)0x400390B0)) |
| #define | ADC1_SSDC3_R (*((volatile uint32_t *)0x400390B4)) |
| #define | ADC1_SSEMUX3_R (*((volatile uint32_t *)0x400390B8)) |
| #define | ADC1_DCRIC_R (*((volatile uint32_t *)0x40039D00)) |
| #define | ADC1_DCCTL0_R (*((volatile uint32_t *)0x40039E00)) |
| #define | ADC1_DCCTL1_R (*((volatile uint32_t *)0x40039E04)) |
| #define | ADC1_DCCTL2_R (*((volatile uint32_t *)0x40039E08)) |
| #define | ADC1_DCCTL3_R (*((volatile uint32_t *)0x40039E0C)) |
| #define | ADC1_DCCTL4_R (*((volatile uint32_t *)0x40039E10)) |
| #define | ADC1_DCCTL5_R (*((volatile uint32_t *)0x40039E14)) |
| #define | ADC1_DCCTL6_R (*((volatile uint32_t *)0x40039E18)) |
| #define | ADC1_DCCTL7_R (*((volatile uint32_t *)0x40039E1C)) |
| #define | ADC1_DCCMP0_R (*((volatile uint32_t *)0x40039E40)) |
| #define | ADC1_DCCMP1_R (*((volatile uint32_t *)0x40039E44)) |
| #define | ADC1_DCCMP2_R (*((volatile uint32_t *)0x40039E48)) |
| #define | ADC1_DCCMP3_R (*((volatile uint32_t *)0x40039E4C)) |
| #define | ADC1_DCCMP4_R (*((volatile uint32_t *)0x40039E50)) |
| #define | ADC1_DCCMP5_R (*((volatile uint32_t *)0x40039E54)) |
| #define | ADC1_DCCMP6_R (*((volatile uint32_t *)0x40039E58)) |
| #define | ADC1_DCCMP7_R (*((volatile uint32_t *)0x40039E5C)) |
| #define | ADC1_PP_R (*((volatile uint32_t *)0x40039FC0)) |
| #define | ADC1_PC_R (*((volatile uint32_t *)0x40039FC4)) |
| #define | ADC1_CC_R (*((volatile uint32_t *)0x40039FC8)) |
| #define | COMP_ACMIS_R (*((volatile uint32_t *)0x4003C000)) |
| #define | COMP_ACRIS_R (*((volatile uint32_t *)0x4003C004)) |
| #define | COMP_ACINTEN_R (*((volatile uint32_t *)0x4003C008)) |
| #define | COMP_ACREFCTL_R (*((volatile uint32_t *)0x4003C010)) |
| #define | COMP_ACSTAT0_R (*((volatile uint32_t *)0x4003C020)) |
| #define | COMP_ACCTL0_R (*((volatile uint32_t *)0x4003C024)) |
| #define | COMP_ACSTAT1_R (*((volatile uint32_t *)0x4003C040)) |
| #define | COMP_ACCTL1_R (*((volatile uint32_t *)0x4003C044)) |
| #define | COMP_ACSTAT2_R (*((volatile uint32_t *)0x4003C060)) |
| #define | COMP_ACCTL2_R (*((volatile uint32_t *)0x4003C064)) |
| #define | COMP_PP_R (*((volatile uint32_t *)0x4003CFC0)) |
| #define | GPIO_PORTJ_DATA_BITS_R ((volatile uint32_t *)0x4003D000) |
| #define | GPIO_PORTJ_DATA_R (*((volatile uint32_t *)0x4003D3FC)) |
| #define | GPIO_PORTJ_DIR_R (*((volatile uint32_t *)0x4003D400)) |
| #define | GPIO_PORTJ_IS_R (*((volatile uint32_t *)0x4003D404)) |
| #define | GPIO_PORTJ_IBE_R (*((volatile uint32_t *)0x4003D408)) |
| #define | GPIO_PORTJ_IEV_R (*((volatile uint32_t *)0x4003D40C)) |
| #define | GPIO_PORTJ_IM_R (*((volatile uint32_t *)0x4003D410)) |
| #define | GPIO_PORTJ_RIS_R (*((volatile uint32_t *)0x4003D414)) |
| #define | GPIO_PORTJ_MIS_R (*((volatile uint32_t *)0x4003D418)) |
| #define | GPIO_PORTJ_ICR_R (*((volatile uint32_t *)0x4003D41C)) |
| #define | GPIO_PORTJ_AFSEL_R (*((volatile uint32_t *)0x4003D420)) |
| #define | GPIO_PORTJ_DR2R_R (*((volatile uint32_t *)0x4003D500)) |
| #define | GPIO_PORTJ_DR4R_R (*((volatile uint32_t *)0x4003D504)) |
| #define | GPIO_PORTJ_DR8R_R (*((volatile uint32_t *)0x4003D508)) |
| #define | GPIO_PORTJ_ODR_R (*((volatile uint32_t *)0x4003D50C)) |
| #define | GPIO_PORTJ_PUR_R (*((volatile uint32_t *)0x4003D510)) |
| #define | GPIO_PORTJ_PDR_R (*((volatile uint32_t *)0x4003D514)) |
| #define | GPIO_PORTJ_SLR_R (*((volatile uint32_t *)0x4003D518)) |
| #define | GPIO_PORTJ_DEN_R (*((volatile uint32_t *)0x4003D51C)) |
| #define | GPIO_PORTJ_LOCK_R (*((volatile uint32_t *)0x4003D520)) |
| #define | GPIO_PORTJ_CR_R (*((volatile uint32_t *)0x4003D524)) |
| #define | GPIO_PORTJ_AMSEL_R (*((volatile uint32_t *)0x4003D528)) |
| #define | GPIO_PORTJ_PCTL_R (*((volatile uint32_t *)0x4003D52C)) |
| #define | GPIO_PORTJ_ADCCTL_R (*((volatile uint32_t *)0x4003D530)) |
| #define | GPIO_PORTJ_DMACTL_R (*((volatile uint32_t *)0x4003D534)) |
| #define | GPIO_PORTJ_SI_R (*((volatile uint32_t *)0x4003D538)) |
| #define | CAN0_CTL_R (*((volatile uint32_t *)0x40040000)) |
| #define | CAN0_STS_R (*((volatile uint32_t *)0x40040004)) |
| #define | CAN0_ERR_R (*((volatile uint32_t *)0x40040008)) |
| #define | CAN0_BIT_R (*((volatile uint32_t *)0x4004000C)) |
| #define | CAN0_INT_R (*((volatile uint32_t *)0x40040010)) |
| #define | CAN0_TST_R (*((volatile uint32_t *)0x40040014)) |
| #define | CAN0_BRPE_R (*((volatile uint32_t *)0x40040018)) |
| #define | CAN0_IF1CRQ_R (*((volatile uint32_t *)0x40040020)) |
| #define | CAN0_IF1CMSK_R (*((volatile uint32_t *)0x40040024)) |
| #define | CAN0_IF1MSK1_R (*((volatile uint32_t *)0x40040028)) |
| #define | CAN0_IF1MSK2_R (*((volatile uint32_t *)0x4004002C)) |
| #define | CAN0_IF1ARB1_R (*((volatile uint32_t *)0x40040030)) |
| #define | CAN0_IF1ARB2_R (*((volatile uint32_t *)0x40040034)) |
| #define | CAN0_IF1MCTL_R (*((volatile uint32_t *)0x40040038)) |
| #define | CAN0_IF1DA1_R (*((volatile uint32_t *)0x4004003C)) |
| #define | CAN0_IF1DA2_R (*((volatile uint32_t *)0x40040040)) |
| #define | CAN0_IF1DB1_R (*((volatile uint32_t *)0x40040044)) |
| #define | CAN0_IF1DB2_R (*((volatile uint32_t *)0x40040048)) |
| #define | CAN0_IF2CRQ_R (*((volatile uint32_t *)0x40040080)) |
| #define | CAN0_IF2CMSK_R (*((volatile uint32_t *)0x40040084)) |
| #define | CAN0_IF2MSK1_R (*((volatile uint32_t *)0x40040088)) |
| #define | CAN0_IF2MSK2_R (*((volatile uint32_t *)0x4004008C)) |
| #define | CAN0_IF2ARB1_R (*((volatile uint32_t *)0x40040090)) |
| #define | CAN0_IF2ARB2_R (*((volatile uint32_t *)0x40040094)) |
| #define | CAN0_IF2MCTL_R (*((volatile uint32_t *)0x40040098)) |
| #define | CAN0_IF2DA1_R (*((volatile uint32_t *)0x4004009C)) |
| #define | CAN0_IF2DA2_R (*((volatile uint32_t *)0x400400A0)) |
| #define | CAN0_IF2DB1_R (*((volatile uint32_t *)0x400400A4)) |
| #define | CAN0_IF2DB2_R (*((volatile uint32_t *)0x400400A8)) |
| #define | CAN0_TXRQ1_R (*((volatile uint32_t *)0x40040100)) |
| #define | CAN0_TXRQ2_R (*((volatile uint32_t *)0x40040104)) |
| #define | CAN0_NWDA1_R (*((volatile uint32_t *)0x40040120)) |
| #define | CAN0_NWDA2_R (*((volatile uint32_t *)0x40040124)) |
| #define | CAN0_MSG1INT_R (*((volatile uint32_t *)0x40040140)) |
| #define | CAN0_MSG2INT_R (*((volatile uint32_t *)0x40040144)) |
| #define | CAN0_MSG1VAL_R (*((volatile uint32_t *)0x40040160)) |
| #define | CAN0_MSG2VAL_R (*((volatile uint32_t *)0x40040164)) |
| #define | CAN1_CTL_R (*((volatile uint32_t *)0x40041000)) |
| #define | CAN1_STS_R (*((volatile uint32_t *)0x40041004)) |
| #define | CAN1_ERR_R (*((volatile uint32_t *)0x40041008)) |
| #define | CAN1_BIT_R (*((volatile uint32_t *)0x4004100C)) |
| #define | CAN1_INT_R (*((volatile uint32_t *)0x40041010)) |
| #define | CAN1_TST_R (*((volatile uint32_t *)0x40041014)) |
| #define | CAN1_BRPE_R (*((volatile uint32_t *)0x40041018)) |
| #define | CAN1_IF1CRQ_R (*((volatile uint32_t *)0x40041020)) |
| #define | CAN1_IF1CMSK_R (*((volatile uint32_t *)0x40041024)) |
| #define | CAN1_IF1MSK1_R (*((volatile uint32_t *)0x40041028)) |
| #define | CAN1_IF1MSK2_R (*((volatile uint32_t *)0x4004102C)) |
| #define | CAN1_IF1ARB1_R (*((volatile uint32_t *)0x40041030)) |
| #define | CAN1_IF1ARB2_R (*((volatile uint32_t *)0x40041034)) |
| #define | CAN1_IF1MCTL_R (*((volatile uint32_t *)0x40041038)) |
| #define | CAN1_IF1DA1_R (*((volatile uint32_t *)0x4004103C)) |
| #define | CAN1_IF1DA2_R (*((volatile uint32_t *)0x40041040)) |
| #define | CAN1_IF1DB1_R (*((volatile uint32_t *)0x40041044)) |
| #define | CAN1_IF1DB2_R (*((volatile uint32_t *)0x40041048)) |
| #define | CAN1_IF2CRQ_R (*((volatile uint32_t *)0x40041080)) |
| #define | CAN1_IF2CMSK_R (*((volatile uint32_t *)0x40041084)) |
| #define | CAN1_IF2MSK1_R (*((volatile uint32_t *)0x40041088)) |
| #define | CAN1_IF2MSK2_R (*((volatile uint32_t *)0x4004108C)) |
| #define | CAN1_IF2ARB1_R (*((volatile uint32_t *)0x40041090)) |
| #define | CAN1_IF2ARB2_R (*((volatile uint32_t *)0x40041094)) |
| #define | CAN1_IF2MCTL_R (*((volatile uint32_t *)0x40041098)) |
| #define | CAN1_IF2DA1_R (*((volatile uint32_t *)0x4004109C)) |
| #define | CAN1_IF2DA2_R (*((volatile uint32_t *)0x400410A0)) |
| #define | CAN1_IF2DB1_R (*((volatile uint32_t *)0x400410A4)) |
| #define | CAN1_IF2DB2_R (*((volatile uint32_t *)0x400410A8)) |
| #define | CAN1_TXRQ1_R (*((volatile uint32_t *)0x40041100)) |
| #define | CAN1_TXRQ2_R (*((volatile uint32_t *)0x40041104)) |
| #define | CAN1_NWDA1_R (*((volatile uint32_t *)0x40041120)) |
| #define | CAN1_NWDA2_R (*((volatile uint32_t *)0x40041124)) |
| #define | CAN1_MSG1INT_R (*((volatile uint32_t *)0x40041140)) |
| #define | CAN1_MSG2INT_R (*((volatile uint32_t *)0x40041144)) |
| #define | CAN1_MSG1VAL_R (*((volatile uint32_t *)0x40041160)) |
| #define | CAN1_MSG2VAL_R (*((volatile uint32_t *)0x40041164)) |
| #define | WTIMER2_CFG_R (*((volatile uint32_t *)0x4004C000)) |
| #define | WTIMER2_TAMR_R (*((volatile uint32_t *)0x4004C004)) |
| #define | WTIMER2_TBMR_R (*((volatile uint32_t *)0x4004C008)) |
| #define | WTIMER2_CTL_R (*((volatile uint32_t *)0x4004C00C)) |
| #define | WTIMER2_SYNC_R (*((volatile uint32_t *)0x4004C010)) |
| #define | WTIMER2_IMR_R (*((volatile uint32_t *)0x4004C018)) |
| #define | WTIMER2_RIS_R (*((volatile uint32_t *)0x4004C01C)) |
| #define | WTIMER2_MIS_R (*((volatile uint32_t *)0x4004C020)) |
| #define | WTIMER2_ICR_R (*((volatile uint32_t *)0x4004C024)) |
| #define | WTIMER2_TAILR_R (*((volatile uint32_t *)0x4004C028)) |
| #define | WTIMER2_TBILR_R (*((volatile uint32_t *)0x4004C02C)) |
| #define | WTIMER2_TAMATCHR_R (*((volatile uint32_t *)0x4004C030)) |
| #define | WTIMER2_TBMATCHR_R (*((volatile uint32_t *)0x4004C034)) |
| #define | WTIMER2_TAPR_R (*((volatile uint32_t *)0x4004C038)) |
| #define | WTIMER2_TBPR_R (*((volatile uint32_t *)0x4004C03C)) |
| #define | WTIMER2_TAPMR_R (*((volatile uint32_t *)0x4004C040)) |
| #define | WTIMER2_TBPMR_R (*((volatile uint32_t *)0x4004C044)) |
| #define | WTIMER2_TAR_R (*((volatile uint32_t *)0x4004C048)) |
| #define | WTIMER2_TBR_R (*((volatile uint32_t *)0x4004C04C)) |
| #define | WTIMER2_TAV_R (*((volatile uint32_t *)0x4004C050)) |
| #define | WTIMER2_TBV_R (*((volatile uint32_t *)0x4004C054)) |
| #define | WTIMER2_RTCPD_R (*((volatile uint32_t *)0x4004C058)) |
| #define | WTIMER2_TAPS_R (*((volatile uint32_t *)0x4004C05C)) |
| #define | WTIMER2_TBPS_R (*((volatile uint32_t *)0x4004C060)) |
| #define | WTIMER2_TAPV_R (*((volatile uint32_t *)0x4004C064)) |
| #define | WTIMER2_TBPV_R (*((volatile uint32_t *)0x4004C068)) |
| #define | WTIMER2_PP_R (*((volatile uint32_t *)0x4004CFC0)) |
| #define | WTIMER3_CFG_R (*((volatile uint32_t *)0x4004D000)) |
| #define | WTIMER3_TAMR_R (*((volatile uint32_t *)0x4004D004)) |
| #define | WTIMER3_TBMR_R (*((volatile uint32_t *)0x4004D008)) |
| #define | WTIMER3_CTL_R (*((volatile uint32_t *)0x4004D00C)) |
| #define | WTIMER3_SYNC_R (*((volatile uint32_t *)0x4004D010)) |
| #define | WTIMER3_IMR_R (*((volatile uint32_t *)0x4004D018)) |
| #define | WTIMER3_RIS_R (*((volatile uint32_t *)0x4004D01C)) |
| #define | WTIMER3_MIS_R (*((volatile uint32_t *)0x4004D020)) |
| #define | WTIMER3_ICR_R (*((volatile uint32_t *)0x4004D024)) |
| #define | WTIMER3_TAILR_R (*((volatile uint32_t *)0x4004D028)) |
| #define | WTIMER3_TBILR_R (*((volatile uint32_t *)0x4004D02C)) |
| #define | WTIMER3_TAMATCHR_R (*((volatile uint32_t *)0x4004D030)) |
| #define | WTIMER3_TBMATCHR_R (*((volatile uint32_t *)0x4004D034)) |
| #define | WTIMER3_TAPR_R (*((volatile uint32_t *)0x4004D038)) |
| #define | WTIMER3_TBPR_R (*((volatile uint32_t *)0x4004D03C)) |
| #define | WTIMER3_TAPMR_R (*((volatile uint32_t *)0x4004D040)) |
| #define | WTIMER3_TBPMR_R (*((volatile uint32_t *)0x4004D044)) |
| #define | WTIMER3_TAR_R (*((volatile uint32_t *)0x4004D048)) |
| #define | WTIMER3_TBR_R (*((volatile uint32_t *)0x4004D04C)) |
| #define | WTIMER3_TAV_R (*((volatile uint32_t *)0x4004D050)) |
| #define | WTIMER3_TBV_R (*((volatile uint32_t *)0x4004D054)) |
| #define | WTIMER3_RTCPD_R (*((volatile uint32_t *)0x4004D058)) |
| #define | WTIMER3_TAPS_R (*((volatile uint32_t *)0x4004D05C)) |
| #define | WTIMER3_TBPS_R (*((volatile uint32_t *)0x4004D060)) |
| #define | WTIMER3_TAPV_R (*((volatile uint32_t *)0x4004D064)) |
| #define | WTIMER3_TBPV_R (*((volatile uint32_t *)0x4004D068)) |
| #define | WTIMER3_PP_R (*((volatile uint32_t *)0x4004DFC0)) |
| #define | WTIMER4_CFG_R (*((volatile uint32_t *)0x4004E000)) |
| #define | WTIMER4_TAMR_R (*((volatile uint32_t *)0x4004E004)) |
| #define | WTIMER4_TBMR_R (*((volatile uint32_t *)0x4004E008)) |
| #define | WTIMER4_CTL_R (*((volatile uint32_t *)0x4004E00C)) |
| #define | WTIMER4_SYNC_R (*((volatile uint32_t *)0x4004E010)) |
| #define | WTIMER4_IMR_R (*((volatile uint32_t *)0x4004E018)) |
| #define | WTIMER4_RIS_R (*((volatile uint32_t *)0x4004E01C)) |
| #define | WTIMER4_MIS_R (*((volatile uint32_t *)0x4004E020)) |
| #define | WTIMER4_ICR_R (*((volatile uint32_t *)0x4004E024)) |
| #define | WTIMER4_TAILR_R (*((volatile uint32_t *)0x4004E028)) |
| #define | WTIMER4_TBILR_R (*((volatile uint32_t *)0x4004E02C)) |
| #define | WTIMER4_TAMATCHR_R (*((volatile uint32_t *)0x4004E030)) |
| #define | WTIMER4_TBMATCHR_R (*((volatile uint32_t *)0x4004E034)) |
| #define | WTIMER4_TAPR_R (*((volatile uint32_t *)0x4004E038)) |
| #define | WTIMER4_TBPR_R (*((volatile uint32_t *)0x4004E03C)) |
| #define | WTIMER4_TAPMR_R (*((volatile uint32_t *)0x4004E040)) |
| #define | WTIMER4_TBPMR_R (*((volatile uint32_t *)0x4004E044)) |
| #define | WTIMER4_TAR_R (*((volatile uint32_t *)0x4004E048)) |
| #define | WTIMER4_TBR_R (*((volatile uint32_t *)0x4004E04C)) |
| #define | WTIMER4_TAV_R (*((volatile uint32_t *)0x4004E050)) |
| #define | WTIMER4_TBV_R (*((volatile uint32_t *)0x4004E054)) |
| #define | WTIMER4_RTCPD_R (*((volatile uint32_t *)0x4004E058)) |
| #define | WTIMER4_TAPS_R (*((volatile uint32_t *)0x4004E05C)) |
| #define | WTIMER4_TBPS_R (*((volatile uint32_t *)0x4004E060)) |
| #define | WTIMER4_TAPV_R (*((volatile uint32_t *)0x4004E064)) |
| #define | WTIMER4_TBPV_R (*((volatile uint32_t *)0x4004E068)) |
| #define | WTIMER4_PP_R (*((volatile uint32_t *)0x4004EFC0)) |
| #define | WTIMER5_CFG_R (*((volatile uint32_t *)0x4004F000)) |
| #define | WTIMER5_TAMR_R (*((volatile uint32_t *)0x4004F004)) |
| #define | WTIMER5_TBMR_R (*((volatile uint32_t *)0x4004F008)) |
| #define | WTIMER5_CTL_R (*((volatile uint32_t *)0x4004F00C)) |
| #define | WTIMER5_SYNC_R (*((volatile uint32_t *)0x4004F010)) |
| #define | WTIMER5_IMR_R (*((volatile uint32_t *)0x4004F018)) |
| #define | WTIMER5_RIS_R (*((volatile uint32_t *)0x4004F01C)) |
| #define | WTIMER5_MIS_R (*((volatile uint32_t *)0x4004F020)) |
| #define | WTIMER5_ICR_R (*((volatile uint32_t *)0x4004F024)) |
| #define | WTIMER5_TAILR_R (*((volatile uint32_t *)0x4004F028)) |
| #define | WTIMER5_TBILR_R (*((volatile uint32_t *)0x4004F02C)) |
| #define | WTIMER5_TAMATCHR_R (*((volatile uint32_t *)0x4004F030)) |
| #define | WTIMER5_TBMATCHR_R (*((volatile uint32_t *)0x4004F034)) |
| #define | WTIMER5_TAPR_R (*((volatile uint32_t *)0x4004F038)) |
| #define | WTIMER5_TBPR_R (*((volatile uint32_t *)0x4004F03C)) |
| #define | WTIMER5_TAPMR_R (*((volatile uint32_t *)0x4004F040)) |
| #define | WTIMER5_TBPMR_R (*((volatile uint32_t *)0x4004F044)) |
| #define | WTIMER5_TAR_R (*((volatile uint32_t *)0x4004F048)) |
| #define | WTIMER5_TBR_R (*((volatile uint32_t *)0x4004F04C)) |
| #define | WTIMER5_TAV_R (*((volatile uint32_t *)0x4004F050)) |
| #define | WTIMER5_TBV_R (*((volatile uint32_t *)0x4004F054)) |
| #define | WTIMER5_RTCPD_R (*((volatile uint32_t *)0x4004F058)) |
| #define | WTIMER5_TAPS_R (*((volatile uint32_t *)0x4004F05C)) |
| #define | WTIMER5_TBPS_R (*((volatile uint32_t *)0x4004F060)) |
| #define | WTIMER5_TAPV_R (*((volatile uint32_t *)0x4004F064)) |
| #define | WTIMER5_TBPV_R (*((volatile uint32_t *)0x4004F068)) |
| #define | WTIMER5_PP_R (*((volatile uint32_t *)0x4004FFC0)) |
| #define | USB0_FADDR_R (*((volatile uint8_t *)0x40050000)) |
| #define | USB0_POWER_R (*((volatile uint8_t *)0x40050001)) |
| #define | USB0_TXIS_R (*((volatile uint16_t *)0x40050002)) |
| #define | USB0_RXIS_R (*((volatile uint16_t *)0x40050004)) |
| #define | USB0_TXIE_R (*((volatile uint16_t *)0x40050006)) |
| #define | USB0_RXIE_R (*((volatile uint16_t *)0x40050008)) |
| #define | USB0_IS_R (*((volatile uint8_t *)0x4005000A)) |
| #define | USB0_IE_R (*((volatile uint8_t *)0x4005000B)) |
| #define | USB0_FRAME_R (*((volatile uint16_t *)0x4005000C)) |
| #define | USB0_EPIDX_R (*((volatile uint8_t *)0x4005000E)) |
| #define | USB0_TEST_R (*((volatile uint8_t *)0x4005000F)) |
| #define | USB0_FIFO0_R (*((volatile uint32_t *)0x40050020)) |
| #define | USB0_FIFO1_R (*((volatile uint32_t *)0x40050024)) |
| #define | USB0_FIFO2_R (*((volatile uint32_t *)0x40050028)) |
| #define | USB0_FIFO3_R (*((volatile uint32_t *)0x4005002C)) |
| #define | USB0_FIFO4_R (*((volatile uint32_t *)0x40050030)) |
| #define | USB0_FIFO5_R (*((volatile uint32_t *)0x40050034)) |
| #define | USB0_FIFO6_R (*((volatile uint32_t *)0x40050038)) |
| #define | USB0_FIFO7_R (*((volatile uint32_t *)0x4005003C)) |
| #define | USB0_DEVCTL_R (*((volatile uint8_t *)0x40050060)) |
| #define | USB0_TXFIFOSZ_R (*((volatile uint8_t *)0x40050062)) |
| #define | USB0_RXFIFOSZ_R (*((volatile uint8_t *)0x40050063)) |
| #define | USB0_TXFIFOADD_R (*((volatile uint16_t *)0x40050064)) |
| #define | USB0_RXFIFOADD_R (*((volatile uint16_t *)0x40050066)) |
| #define | USB0_CONTIM_R (*((volatile uint8_t *)0x4005007A)) |
| #define | USB0_VPLEN_R (*((volatile uint8_t *)0x4005007B)) |
| #define | USB0_FSEOF_R (*((volatile uint8_t *)0x4005007D)) |
| #define | USB0_LSEOF_R (*((volatile uint8_t *)0x4005007E)) |
| #define | USB0_TXFUNCADDR0_R (*((volatile uint8_t *)0x40050080)) |
| #define | USB0_TXHUBADDR0_R (*((volatile uint8_t *)0x40050082)) |
| #define | USB0_TXHUBPORT0_R (*((volatile uint8_t *)0x40050083)) |
| #define | USB0_TXFUNCADDR1_R (*((volatile uint8_t *)0x40050088)) |
| #define | USB0_TXHUBADDR1_R (*((volatile uint8_t *)0x4005008A)) |
| #define | USB0_TXHUBPORT1_R (*((volatile uint8_t *)0x4005008B)) |
| #define | USB0_RXFUNCADDR1_R (*((volatile uint8_t *)0x4005008C)) |
| #define | USB0_RXHUBADDR1_R (*((volatile uint8_t *)0x4005008E)) |
| #define | USB0_RXHUBPORT1_R (*((volatile uint8_t *)0x4005008F)) |
| #define | USB0_TXFUNCADDR2_R (*((volatile uint8_t *)0x40050090)) |
| #define | USB0_TXHUBADDR2_R (*((volatile uint8_t *)0x40050092)) |
| #define | USB0_TXHUBPORT2_R (*((volatile uint8_t *)0x40050093)) |
| #define | USB0_RXFUNCADDR2_R (*((volatile uint8_t *)0x40050094)) |
| #define | USB0_RXHUBADDR2_R (*((volatile uint8_t *)0x40050096)) |
| #define | USB0_RXHUBPORT2_R (*((volatile uint8_t *)0x40050097)) |
| #define | USB0_TXFUNCADDR3_R (*((volatile uint8_t *)0x40050098)) |
| #define | USB0_TXHUBADDR3_R (*((volatile uint8_t *)0x4005009A)) |
| #define | USB0_TXHUBPORT3_R (*((volatile uint8_t *)0x4005009B)) |
| #define | USB0_RXFUNCADDR3_R (*((volatile uint8_t *)0x4005009C)) |
| #define | USB0_RXHUBADDR3_R (*((volatile uint8_t *)0x4005009E)) |
| #define | USB0_RXHUBPORT3_R (*((volatile uint8_t *)0x4005009F)) |
| #define | USB0_TXFUNCADDR4_R (*((volatile uint8_t *)0x400500A0)) |
| #define | USB0_TXHUBADDR4_R (*((volatile uint8_t *)0x400500A2)) |
| #define | USB0_TXHUBPORT4_R (*((volatile uint8_t *)0x400500A3)) |
| #define | USB0_RXFUNCADDR4_R (*((volatile uint8_t *)0x400500A4)) |
| #define | USB0_RXHUBADDR4_R (*((volatile uint8_t *)0x400500A6)) |
| #define | USB0_RXHUBPORT4_R (*((volatile uint8_t *)0x400500A7)) |
| #define | USB0_TXFUNCADDR5_R (*((volatile uint8_t *)0x400500A8)) |
| #define | USB0_TXHUBADDR5_R (*((volatile uint8_t *)0x400500AA)) |
| #define | USB0_TXHUBPORT5_R (*((volatile uint8_t *)0x400500AB)) |
| #define | USB0_RXFUNCADDR5_R (*((volatile uint8_t *)0x400500AC)) |
| #define | USB0_RXHUBADDR5_R (*((volatile uint8_t *)0x400500AE)) |
| #define | USB0_RXHUBPORT5_R (*((volatile uint8_t *)0x400500AF)) |
| #define | USB0_TXFUNCADDR6_R (*((volatile uint8_t *)0x400500B0)) |
| #define | USB0_TXHUBADDR6_R (*((volatile uint8_t *)0x400500B2)) |
| #define | USB0_TXHUBPORT6_R (*((volatile uint8_t *)0x400500B3)) |
| #define | USB0_RXFUNCADDR6_R (*((volatile uint8_t *)0x400500B4)) |
| #define | USB0_RXHUBADDR6_R (*((volatile uint8_t *)0x400500B6)) |
| #define | USB0_RXHUBPORT6_R (*((volatile uint8_t *)0x400500B7)) |
| #define | USB0_TXFUNCADDR7_R (*((volatile uint8_t *)0x400500B8)) |
| #define | USB0_TXHUBADDR7_R (*((volatile uint8_t *)0x400500BA)) |
| #define | USB0_TXHUBPORT7_R (*((volatile uint8_t *)0x400500BB)) |
| #define | USB0_RXFUNCADDR7_R (*((volatile uint8_t *)0x400500BC)) |
| #define | USB0_RXHUBADDR7_R (*((volatile uint8_t *)0x400500BE)) |
| #define | USB0_RXHUBPORT7_R (*((volatile uint8_t *)0x400500BF)) |
| #define | USB0_CSRL0_R (*((volatile uint8_t *)0x40050102)) |
| #define | USB0_CSRH0_R (*((volatile uint8_t *)0x40050103)) |
| #define | USB0_COUNT0_R (*((volatile uint8_t *)0x40050108)) |
| #define | USB0_TYPE0_R (*((volatile uint8_t *)0x4005010A)) |
| #define | USB0_NAKLMT_R (*((volatile uint8_t *)0x4005010B)) |
| #define | USB0_TXMAXP1_R (*((volatile uint16_t *)0x40050110)) |
| #define | USB0_TXCSRL1_R (*((volatile uint8_t *)0x40050112)) |
| #define | USB0_TXCSRH1_R (*((volatile uint8_t *)0x40050113)) |
| #define | USB0_RXMAXP1_R (*((volatile uint16_t *)0x40050114)) |
| #define | USB0_RXCSRL1_R (*((volatile uint8_t *)0x40050116)) |
| #define | USB0_RXCSRH1_R (*((volatile uint8_t *)0x40050117)) |
| #define | USB0_RXCOUNT1_R (*((volatile uint16_t *)0x40050118)) |
| #define | USB0_TXTYPE1_R (*((volatile uint8_t *)0x4005011A)) |
| #define | USB0_TXINTERVAL1_R (*((volatile uint8_t *)0x4005011B)) |
| #define | USB0_RXTYPE1_R (*((volatile uint8_t *)0x4005011C)) |
| #define | USB0_RXINTERVAL1_R (*((volatile uint8_t *)0x4005011D)) |
| #define | USB0_TXMAXP2_R (*((volatile uint16_t *)0x40050120)) |
| #define | USB0_TXCSRL2_R (*((volatile uint8_t *)0x40050122)) |
| #define | USB0_TXCSRH2_R (*((volatile uint8_t *)0x40050123)) |
| #define | USB0_RXMAXP2_R (*((volatile uint16_t *)0x40050124)) |
| #define | USB0_RXCSRL2_R (*((volatile uint8_t *)0x40050126)) |
| #define | USB0_RXCSRH2_R (*((volatile uint8_t *)0x40050127)) |
| #define | USB0_RXCOUNT2_R (*((volatile uint16_t *)0x40050128)) |
| #define | USB0_TXTYPE2_R (*((volatile uint8_t *)0x4005012A)) |
| #define | USB0_TXINTERVAL2_R (*((volatile uint8_t *)0x4005012B)) |
| #define | USB0_RXTYPE2_R (*((volatile uint8_t *)0x4005012C)) |
| #define | USB0_RXINTERVAL2_R (*((volatile uint8_t *)0x4005012D)) |
| #define | USB0_TXMAXP3_R (*((volatile uint16_t *)0x40050130)) |
| #define | USB0_TXCSRL3_R (*((volatile uint8_t *)0x40050132)) |
| #define | USB0_TXCSRH3_R (*((volatile uint8_t *)0x40050133)) |
| #define | USB0_RXMAXP3_R (*((volatile uint16_t *)0x40050134)) |
| #define | USB0_RXCSRL3_R (*((volatile uint8_t *)0x40050136)) |
| #define | USB0_RXCSRH3_R (*((volatile uint8_t *)0x40050137)) |
| #define | USB0_RXCOUNT3_R (*((volatile uint16_t *)0x40050138)) |
| #define | USB0_TXTYPE3_R (*((volatile uint8_t *)0x4005013A)) |
| #define | USB0_TXINTERVAL3_R (*((volatile uint8_t *)0x4005013B)) |
| #define | USB0_RXTYPE3_R (*((volatile uint8_t *)0x4005013C)) |
| #define | USB0_RXINTERVAL3_R (*((volatile uint8_t *)0x4005013D)) |
| #define | USB0_TXMAXP4_R (*((volatile uint16_t *)0x40050140)) |
| #define | USB0_TXCSRL4_R (*((volatile uint8_t *)0x40050142)) |
| #define | USB0_TXCSRH4_R (*((volatile uint8_t *)0x40050143)) |
| #define | USB0_RXMAXP4_R (*((volatile uint16_t *)0x40050144)) |
| #define | USB0_RXCSRL4_R (*((volatile uint8_t *)0x40050146)) |
| #define | USB0_RXCSRH4_R (*((volatile uint8_t *)0x40050147)) |
| #define | USB0_RXCOUNT4_R (*((volatile uint16_t *)0x40050148)) |
| #define | USB0_TXTYPE4_R (*((volatile uint8_t *)0x4005014A)) |
| #define | USB0_TXINTERVAL4_R (*((volatile uint8_t *)0x4005014B)) |
| #define | USB0_RXTYPE4_R (*((volatile uint8_t *)0x4005014C)) |
| #define | USB0_RXINTERVAL4_R (*((volatile uint8_t *)0x4005014D)) |
| #define | USB0_TXMAXP5_R (*((volatile uint16_t *)0x40050150)) |
| #define | USB0_TXCSRL5_R (*((volatile uint8_t *)0x40050152)) |
| #define | USB0_TXCSRH5_R (*((volatile uint8_t *)0x40050153)) |
| #define | USB0_RXMAXP5_R (*((volatile uint16_t *)0x40050154)) |
| #define | USB0_RXCSRL5_R (*((volatile uint8_t *)0x40050156)) |
| #define | USB0_RXCSRH5_R (*((volatile uint8_t *)0x40050157)) |
| #define | USB0_RXCOUNT5_R (*((volatile uint16_t *)0x40050158)) |
| #define | USB0_TXTYPE5_R (*((volatile uint8_t *)0x4005015A)) |
| #define | USB0_TXINTERVAL5_R (*((volatile uint8_t *)0x4005015B)) |
| #define | USB0_RXTYPE5_R (*((volatile uint8_t *)0x4005015C)) |
| #define | USB0_RXINTERVAL5_R (*((volatile uint8_t *)0x4005015D)) |
| #define | USB0_TXMAXP6_R (*((volatile uint16_t *)0x40050160)) |
| #define | USB0_TXCSRL6_R (*((volatile uint8_t *)0x40050162)) |
| #define | USB0_TXCSRH6_R (*((volatile uint8_t *)0x40050163)) |
| #define | USB0_RXMAXP6_R (*((volatile uint16_t *)0x40050164)) |
| #define | USB0_RXCSRL6_R (*((volatile uint8_t *)0x40050166)) |
| #define | USB0_RXCSRH6_R (*((volatile uint8_t *)0x40050167)) |
| #define | USB0_RXCOUNT6_R (*((volatile uint16_t *)0x40050168)) |
| #define | USB0_TXTYPE6_R (*((volatile uint8_t *)0x4005016A)) |
| #define | USB0_TXINTERVAL6_R (*((volatile uint8_t *)0x4005016B)) |
| #define | USB0_RXTYPE6_R (*((volatile uint8_t *)0x4005016C)) |
| #define | USB0_RXINTERVAL6_R (*((volatile uint8_t *)0x4005016D)) |
| #define | USB0_TXMAXP7_R (*((volatile uint16_t *)0x40050170)) |
| #define | USB0_TXCSRL7_R (*((volatile uint8_t *)0x40050172)) |
| #define | USB0_TXCSRH7_R (*((volatile uint8_t *)0x40050173)) |
| #define | USB0_RXMAXP7_R (*((volatile uint16_t *)0x40050174)) |
| #define | USB0_RXCSRL7_R (*((volatile uint8_t *)0x40050176)) |
| #define | USB0_RXCSRH7_R (*((volatile uint8_t *)0x40050177)) |
| #define | USB0_RXCOUNT7_R (*((volatile uint16_t *)0x40050178)) |
| #define | USB0_TXTYPE7_R (*((volatile uint8_t *)0x4005017A)) |
| #define | USB0_TXINTERVAL7_R (*((volatile uint8_t *)0x4005017B)) |
| #define | USB0_RXTYPE7_R (*((volatile uint8_t *)0x4005017C)) |
| #define | USB0_RXINTERVAL7_R (*((volatile uint8_t *)0x4005017D)) |
| #define | USB0_RQPKTCOUNT1_R (*((volatile uint16_t *)0x40050304)) |
| #define | USB0_RQPKTCOUNT2_R (*((volatile uint16_t *)0x40050308)) |
| #define | USB0_RQPKTCOUNT3_R (*((volatile uint16_t *)0x4005030C)) |
| #define | USB0_RQPKTCOUNT4_R (*((volatile uint16_t *)0x40050310)) |
| #define | USB0_RQPKTCOUNT5_R (*((volatile uint16_t *)0x40050314)) |
| #define | USB0_RQPKTCOUNT6_R (*((volatile uint16_t *)0x40050318)) |
| #define | USB0_RQPKTCOUNT7_R (*((volatile uint16_t *)0x4005031C)) |
| #define | USB0_RXDPKTBUFDIS_R (*((volatile uint16_t *)0x40050340)) |
| #define | USB0_TXDPKTBUFDIS_R (*((volatile uint16_t *)0x40050342)) |
| #define | USB0_EPC_R (*((volatile uint32_t *)0x40050400)) |
| #define | USB0_EPCRIS_R (*((volatile uint32_t *)0x40050404)) |
| #define | USB0_EPCIM_R (*((volatile uint32_t *)0x40050408)) |
| #define | USB0_EPCISC_R (*((volatile uint32_t *)0x4005040C)) |
| #define | USB0_DRRIS_R (*((volatile uint32_t *)0x40050410)) |
| #define | USB0_DRIM_R (*((volatile uint32_t *)0x40050414)) |
| #define | USB0_DRISC_R (*((volatile uint32_t *)0x40050418)) |
| #define | USB0_GPCS_R (*((volatile uint32_t *)0x4005041C)) |
| #define | USB0_VDC_R (*((volatile uint32_t *)0x40050430)) |
| #define | USB0_VDCRIS_R (*((volatile uint32_t *)0x40050434)) |
| #define | USB0_VDCIM_R (*((volatile uint32_t *)0x40050438)) |
| #define | USB0_VDCISC_R (*((volatile uint32_t *)0x4005043C)) |
| #define | USB0_IDVRIS_R (*((volatile uint32_t *)0x40050444)) |
| #define | USB0_IDVIM_R (*((volatile uint32_t *)0x40050448)) |
| #define | USB0_IDVISC_R (*((volatile uint32_t *)0x4005044C)) |
| #define | USB0_DMASEL_R (*((volatile uint32_t *)0x40050450)) |
| #define | USB0_PP_R (*((volatile uint32_t *)0x40050FC0)) |
| #define | GPIO_PORTA_AHB_DATA_BITS_R ((volatile uint32_t *)0x40058000) |
| #define | GPIO_PORTA_AHB_DATA_R (*((volatile uint32_t *)0x400583FC)) |
| #define | GPIO_PORTA_AHB_DIR_R (*((volatile uint32_t *)0x40058400)) |
| #define | GPIO_PORTA_AHB_IS_R (*((volatile uint32_t *)0x40058404)) |
| #define | GPIO_PORTA_AHB_IBE_R (*((volatile uint32_t *)0x40058408)) |
| #define | GPIO_PORTA_AHB_IEV_R (*((volatile uint32_t *)0x4005840C)) |
| #define | GPIO_PORTA_AHB_IM_R (*((volatile uint32_t *)0x40058410)) |
| #define | GPIO_PORTA_AHB_RIS_R (*((volatile uint32_t *)0x40058414)) |
| #define | GPIO_PORTA_AHB_MIS_R (*((volatile uint32_t *)0x40058418)) |
| #define | GPIO_PORTA_AHB_ICR_R (*((volatile uint32_t *)0x4005841C)) |
| #define | GPIO_PORTA_AHB_AFSEL_R (*((volatile uint32_t *)0x40058420)) |
| #define | GPIO_PORTA_AHB_DR2R_R (*((volatile uint32_t *)0x40058500)) |
| #define | GPIO_PORTA_AHB_DR4R_R (*((volatile uint32_t *)0x40058504)) |
| #define | GPIO_PORTA_AHB_DR8R_R (*((volatile uint32_t *)0x40058508)) |
| #define | GPIO_PORTA_AHB_ODR_R (*((volatile uint32_t *)0x4005850C)) |
| #define | GPIO_PORTA_AHB_PUR_R (*((volatile uint32_t *)0x40058510)) |
| #define | GPIO_PORTA_AHB_PDR_R (*((volatile uint32_t *)0x40058514)) |
| #define | GPIO_PORTA_AHB_SLR_R (*((volatile uint32_t *)0x40058518)) |
| #define | GPIO_PORTA_AHB_DEN_R (*((volatile uint32_t *)0x4005851C)) |
| #define | GPIO_PORTA_AHB_LOCK_R (*((volatile uint32_t *)0x40058520)) |
| #define | GPIO_PORTA_AHB_CR_R (*((volatile uint32_t *)0x40058524)) |
| #define | GPIO_PORTA_AHB_AMSEL_R (*((volatile uint32_t *)0x40058528)) |
| #define | GPIO_PORTA_AHB_PCTL_R (*((volatile uint32_t *)0x4005852C)) |
| #define | GPIO_PORTA_AHB_ADCCTL_R (*((volatile uint32_t *)0x40058530)) |
| #define | GPIO_PORTA_AHB_DMACTL_R (*((volatile uint32_t *)0x40058534)) |
| #define | GPIO_PORTA_AHB_SI_R (*((volatile uint32_t *)0x40058538)) |
| #define | GPIO_PORTB_AHB_DATA_BITS_R ((volatile uint32_t *)0x40059000) |
| #define | GPIO_PORTB_AHB_DATA_R (*((volatile uint32_t *)0x400593FC)) |
| #define | GPIO_PORTB_AHB_DIR_R (*((volatile uint32_t *)0x40059400)) |
| #define | GPIO_PORTB_AHB_IS_R (*((volatile uint32_t *)0x40059404)) |
| #define | GPIO_PORTB_AHB_IBE_R (*((volatile uint32_t *)0x40059408)) |
| #define | GPIO_PORTB_AHB_IEV_R (*((volatile uint32_t *)0x4005940C)) |
| #define | GPIO_PORTB_AHB_IM_R (*((volatile uint32_t *)0x40059410)) |
| #define | GPIO_PORTB_AHB_RIS_R (*((volatile uint32_t *)0x40059414)) |
| #define | GPIO_PORTB_AHB_MIS_R (*((volatile uint32_t *)0x40059418)) |
| #define | GPIO_PORTB_AHB_ICR_R (*((volatile uint32_t *)0x4005941C)) |
| #define | GPIO_PORTB_AHB_AFSEL_R (*((volatile uint32_t *)0x40059420)) |
| #define | GPIO_PORTB_AHB_DR2R_R (*((volatile uint32_t *)0x40059500)) |
| #define | GPIO_PORTB_AHB_DR4R_R (*((volatile uint32_t *)0x40059504)) |
| #define | GPIO_PORTB_AHB_DR8R_R (*((volatile uint32_t *)0x40059508)) |
| #define | GPIO_PORTB_AHB_ODR_R (*((volatile uint32_t *)0x4005950C)) |
| #define | GPIO_PORTB_AHB_PUR_R (*((volatile uint32_t *)0x40059510)) |
| #define | GPIO_PORTB_AHB_PDR_R (*((volatile uint32_t *)0x40059514)) |
| #define | GPIO_PORTB_AHB_SLR_R (*((volatile uint32_t *)0x40059518)) |
| #define | GPIO_PORTB_AHB_DEN_R (*((volatile uint32_t *)0x4005951C)) |
| #define | GPIO_PORTB_AHB_LOCK_R (*((volatile uint32_t *)0x40059520)) |
| #define | GPIO_PORTB_AHB_CR_R (*((volatile uint32_t *)0x40059524)) |
| #define | GPIO_PORTB_AHB_AMSEL_R (*((volatile uint32_t *)0x40059528)) |
| #define | GPIO_PORTB_AHB_PCTL_R (*((volatile uint32_t *)0x4005952C)) |
| #define | GPIO_PORTB_AHB_ADCCTL_R (*((volatile uint32_t *)0x40059530)) |
| #define | GPIO_PORTB_AHB_DMACTL_R (*((volatile uint32_t *)0x40059534)) |
| #define | GPIO_PORTB_AHB_SI_R (*((volatile uint32_t *)0x40059538)) |
| #define | GPIO_PORTC_AHB_DATA_BITS_R ((volatile uint32_t *)0x4005A000) |
| #define | GPIO_PORTC_AHB_DATA_R (*((volatile uint32_t *)0x4005A3FC)) |
| #define | GPIO_PORTC_AHB_DIR_R (*((volatile uint32_t *)0x4005A400)) |
| #define | GPIO_PORTC_AHB_IS_R (*((volatile uint32_t *)0x4005A404)) |
| #define | GPIO_PORTC_AHB_IBE_R (*((volatile uint32_t *)0x4005A408)) |
| #define | GPIO_PORTC_AHB_IEV_R (*((volatile uint32_t *)0x4005A40C)) |
| #define | GPIO_PORTC_AHB_IM_R (*((volatile uint32_t *)0x4005A410)) |
| #define | GPIO_PORTC_AHB_RIS_R (*((volatile uint32_t *)0x4005A414)) |
| #define | GPIO_PORTC_AHB_MIS_R (*((volatile uint32_t *)0x4005A418)) |
| #define | GPIO_PORTC_AHB_ICR_R (*((volatile uint32_t *)0x4005A41C)) |
| #define | GPIO_PORTC_AHB_AFSEL_R (*((volatile uint32_t *)0x4005A420)) |
| #define | GPIO_PORTC_AHB_DR2R_R (*((volatile uint32_t *)0x4005A500)) |
| #define | GPIO_PORTC_AHB_DR4R_R (*((volatile uint32_t *)0x4005A504)) |
| #define | GPIO_PORTC_AHB_DR8R_R (*((volatile uint32_t *)0x4005A508)) |
| #define | GPIO_PORTC_AHB_ODR_R (*((volatile uint32_t *)0x4005A50C)) |
| #define | GPIO_PORTC_AHB_PUR_R (*((volatile uint32_t *)0x4005A510)) |
| #define | GPIO_PORTC_AHB_PDR_R (*((volatile uint32_t *)0x4005A514)) |
| #define | GPIO_PORTC_AHB_SLR_R (*((volatile uint32_t *)0x4005A518)) |
| #define | GPIO_PORTC_AHB_DEN_R (*((volatile uint32_t *)0x4005A51C)) |
| #define | GPIO_PORTC_AHB_LOCK_R (*((volatile uint32_t *)0x4005A520)) |
| #define | GPIO_PORTC_AHB_CR_R (*((volatile uint32_t *)0x4005A524)) |
| #define | GPIO_PORTC_AHB_AMSEL_R (*((volatile uint32_t *)0x4005A528)) |
| #define | GPIO_PORTC_AHB_PCTL_R (*((volatile uint32_t *)0x4005A52C)) |
| #define | GPIO_PORTC_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005A530)) |
| #define | GPIO_PORTC_AHB_DMACTL_R (*((volatile uint32_t *)0x4005A534)) |
| #define | GPIO_PORTC_AHB_SI_R (*((volatile uint32_t *)0x4005A538)) |
| #define | GPIO_PORTD_AHB_DATA_BITS_R ((volatile uint32_t *)0x4005B000) |
| #define | GPIO_PORTD_AHB_DATA_R (*((volatile uint32_t *)0x4005B3FC)) |
| #define | GPIO_PORTD_AHB_DIR_R (*((volatile uint32_t *)0x4005B400)) |
| #define | GPIO_PORTD_AHB_IS_R (*((volatile uint32_t *)0x4005B404)) |
| #define | GPIO_PORTD_AHB_IBE_R (*((volatile uint32_t *)0x4005B408)) |
| #define | GPIO_PORTD_AHB_IEV_R (*((volatile uint32_t *)0x4005B40C)) |
| #define | GPIO_PORTD_AHB_IM_R (*((volatile uint32_t *)0x4005B410)) |
| #define | GPIO_PORTD_AHB_RIS_R (*((volatile uint32_t *)0x4005B414)) |
| #define | GPIO_PORTD_AHB_MIS_R (*((volatile uint32_t *)0x4005B418)) |
| #define | GPIO_PORTD_AHB_ICR_R (*((volatile uint32_t *)0x4005B41C)) |
| #define | GPIO_PORTD_AHB_AFSEL_R (*((volatile uint32_t *)0x4005B420)) |
| #define | GPIO_PORTD_AHB_DR2R_R (*((volatile uint32_t *)0x4005B500)) |
| #define | GPIO_PORTD_AHB_DR4R_R (*((volatile uint32_t *)0x4005B504)) |
| #define | GPIO_PORTD_AHB_DR8R_R (*((volatile uint32_t *)0x4005B508)) |
| #define | GPIO_PORTD_AHB_ODR_R (*((volatile uint32_t *)0x4005B50C)) |
| #define | GPIO_PORTD_AHB_PUR_R (*((volatile uint32_t *)0x4005B510)) |
| #define | GPIO_PORTD_AHB_PDR_R (*((volatile uint32_t *)0x4005B514)) |
| #define | GPIO_PORTD_AHB_SLR_R (*((volatile uint32_t *)0x4005B518)) |
| #define | GPIO_PORTD_AHB_DEN_R (*((volatile uint32_t *)0x4005B51C)) |
| #define | GPIO_PORTD_AHB_LOCK_R (*((volatile uint32_t *)0x4005B520)) |
| #define | GPIO_PORTD_AHB_CR_R (*((volatile uint32_t *)0x4005B524)) |
| #define | GPIO_PORTD_AHB_AMSEL_R (*((volatile uint32_t *)0x4005B528)) |
| #define | GPIO_PORTD_AHB_PCTL_R (*((volatile uint32_t *)0x4005B52C)) |
| #define | GPIO_PORTD_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005B530)) |
| #define | GPIO_PORTD_AHB_DMACTL_R (*((volatile uint32_t *)0x4005B534)) |
| #define | GPIO_PORTD_AHB_SI_R (*((volatile uint32_t *)0x4005B538)) |
| #define | GPIO_PORTE_AHB_DATA_BITS_R ((volatile uint32_t *)0x4005C000) |
| #define | GPIO_PORTE_AHB_DATA_R (*((volatile uint32_t *)0x4005C3FC)) |
| #define | GPIO_PORTE_AHB_DIR_R (*((volatile uint32_t *)0x4005C400)) |
| #define | GPIO_PORTE_AHB_IS_R (*((volatile uint32_t *)0x4005C404)) |
| #define | GPIO_PORTE_AHB_IBE_R (*((volatile uint32_t *)0x4005C408)) |
| #define | GPIO_PORTE_AHB_IEV_R (*((volatile uint32_t *)0x4005C40C)) |
| #define | GPIO_PORTE_AHB_IM_R (*((volatile uint32_t *)0x4005C410)) |
| #define | GPIO_PORTE_AHB_RIS_R (*((volatile uint32_t *)0x4005C414)) |
| #define | GPIO_PORTE_AHB_MIS_R (*((volatile uint32_t *)0x4005C418)) |
| #define | GPIO_PORTE_AHB_ICR_R (*((volatile uint32_t *)0x4005C41C)) |
| #define | GPIO_PORTE_AHB_AFSEL_R (*((volatile uint32_t *)0x4005C420)) |
| #define | GPIO_PORTE_AHB_DR2R_R (*((volatile uint32_t *)0x4005C500)) |
| #define | GPIO_PORTE_AHB_DR4R_R (*((volatile uint32_t *)0x4005C504)) |
| #define | GPIO_PORTE_AHB_DR8R_R (*((volatile uint32_t *)0x4005C508)) |
| #define | GPIO_PORTE_AHB_ODR_R (*((volatile uint32_t *)0x4005C50C)) |
| #define | GPIO_PORTE_AHB_PUR_R (*((volatile uint32_t *)0x4005C510)) |
| #define | GPIO_PORTE_AHB_PDR_R (*((volatile uint32_t *)0x4005C514)) |
| #define | GPIO_PORTE_AHB_SLR_R (*((volatile uint32_t *)0x4005C518)) |
| #define | GPIO_PORTE_AHB_DEN_R (*((volatile uint32_t *)0x4005C51C)) |
| #define | GPIO_PORTE_AHB_LOCK_R (*((volatile uint32_t *)0x4005C520)) |
| #define | GPIO_PORTE_AHB_CR_R (*((volatile uint32_t *)0x4005C524)) |
| #define | GPIO_PORTE_AHB_AMSEL_R (*((volatile uint32_t *)0x4005C528)) |
| #define | GPIO_PORTE_AHB_PCTL_R (*((volatile uint32_t *)0x4005C52C)) |
| #define | GPIO_PORTE_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005C530)) |
| #define | GPIO_PORTE_AHB_DMACTL_R (*((volatile uint32_t *)0x4005C534)) |
| #define | GPIO_PORTE_AHB_SI_R (*((volatile uint32_t *)0x4005C538)) |
| #define | GPIO_PORTF_AHB_DATA_BITS_R ((volatile uint32_t *)0x4005D000) |
| #define | GPIO_PORTF_AHB_DATA_R (*((volatile uint32_t *)0x4005D3FC)) |
| #define | GPIO_PORTF_AHB_DIR_R (*((volatile uint32_t *)0x4005D400)) |
| #define | GPIO_PORTF_AHB_IS_R (*((volatile uint32_t *)0x4005D404)) |
| #define | GPIO_PORTF_AHB_IBE_R (*((volatile uint32_t *)0x4005D408)) |
| #define | GPIO_PORTF_AHB_IEV_R (*((volatile uint32_t *)0x4005D40C)) |
| #define | GPIO_PORTF_AHB_IM_R (*((volatile uint32_t *)0x4005D410)) |
| #define | GPIO_PORTF_AHB_RIS_R (*((volatile uint32_t *)0x4005D414)) |
| #define | GPIO_PORTF_AHB_MIS_R (*((volatile uint32_t *)0x4005D418)) |
| #define | GPIO_PORTF_AHB_ICR_R (*((volatile uint32_t *)0x4005D41C)) |
| #define | GPIO_PORTF_AHB_AFSEL_R (*((volatile uint32_t *)0x4005D420)) |
| #define | GPIO_PORTF_AHB_DR2R_R (*((volatile uint32_t *)0x4005D500)) |
| #define | GPIO_PORTF_AHB_DR4R_R (*((volatile uint32_t *)0x4005D504)) |
| #define | GPIO_PORTF_AHB_DR8R_R (*((volatile uint32_t *)0x4005D508)) |
| #define | GPIO_PORTF_AHB_ODR_R (*((volatile uint32_t *)0x4005D50C)) |
| #define | GPIO_PORTF_AHB_PUR_R (*((volatile uint32_t *)0x4005D510)) |
| #define | GPIO_PORTF_AHB_PDR_R (*((volatile uint32_t *)0x4005D514)) |
| #define | GPIO_PORTF_AHB_SLR_R (*((volatile uint32_t *)0x4005D518)) |
| #define | GPIO_PORTF_AHB_DEN_R (*((volatile uint32_t *)0x4005D51C)) |
| #define | GPIO_PORTF_AHB_LOCK_R (*((volatile uint32_t *)0x4005D520)) |
| #define | GPIO_PORTF_AHB_CR_R (*((volatile uint32_t *)0x4005D524)) |
| #define | GPIO_PORTF_AHB_AMSEL_R (*((volatile uint32_t *)0x4005D528)) |
| #define | GPIO_PORTF_AHB_PCTL_R (*((volatile uint32_t *)0x4005D52C)) |
| #define | GPIO_PORTF_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005D530)) |
| #define | GPIO_PORTF_AHB_DMACTL_R (*((volatile uint32_t *)0x4005D534)) |
| #define | GPIO_PORTF_AHB_SI_R (*((volatile uint32_t *)0x4005D538)) |
| #define | GPIO_PORTG_AHB_DATA_BITS_R ((volatile uint32_t *)0x4005E000) |
| #define | GPIO_PORTG_AHB_DATA_R (*((volatile uint32_t *)0x4005E3FC)) |
| #define | GPIO_PORTG_AHB_DIR_R (*((volatile uint32_t *)0x4005E400)) |
| #define | GPIO_PORTG_AHB_IS_R (*((volatile uint32_t *)0x4005E404)) |
| #define | GPIO_PORTG_AHB_IBE_R (*((volatile uint32_t *)0x4005E408)) |
| #define | GPIO_PORTG_AHB_IEV_R (*((volatile uint32_t *)0x4005E40C)) |
| #define | GPIO_PORTG_AHB_IM_R (*((volatile uint32_t *)0x4005E410)) |
| #define | GPIO_PORTG_AHB_RIS_R (*((volatile uint32_t *)0x4005E414)) |
| #define | GPIO_PORTG_AHB_MIS_R (*((volatile uint32_t *)0x4005E418)) |
| #define | GPIO_PORTG_AHB_ICR_R (*((volatile uint32_t *)0x4005E41C)) |
| #define | GPIO_PORTG_AHB_AFSEL_R (*((volatile uint32_t *)0x4005E420)) |
| #define | GPIO_PORTG_AHB_DR2R_R (*((volatile uint32_t *)0x4005E500)) |
| #define | GPIO_PORTG_AHB_DR4R_R (*((volatile uint32_t *)0x4005E504)) |
| #define | GPIO_PORTG_AHB_DR8R_R (*((volatile uint32_t *)0x4005E508)) |
| #define | GPIO_PORTG_AHB_ODR_R (*((volatile uint32_t *)0x4005E50C)) |
| #define | GPIO_PORTG_AHB_PUR_R (*((volatile uint32_t *)0x4005E510)) |
| #define | GPIO_PORTG_AHB_PDR_R (*((volatile uint32_t *)0x4005E514)) |
| #define | GPIO_PORTG_AHB_SLR_R (*((volatile uint32_t *)0x4005E518)) |
| #define | GPIO_PORTG_AHB_DEN_R (*((volatile uint32_t *)0x4005E51C)) |
| #define | GPIO_PORTG_AHB_LOCK_R (*((volatile uint32_t *)0x4005E520)) |
| #define | GPIO_PORTG_AHB_CR_R (*((volatile uint32_t *)0x4005E524)) |
| #define | GPIO_PORTG_AHB_AMSEL_R (*((volatile uint32_t *)0x4005E528)) |
| #define | GPIO_PORTG_AHB_PCTL_R (*((volatile uint32_t *)0x4005E52C)) |
| #define | GPIO_PORTG_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005E530)) |
| #define | GPIO_PORTG_AHB_DMACTL_R (*((volatile uint32_t *)0x4005E534)) |
| #define | GPIO_PORTG_AHB_SI_R (*((volatile uint32_t *)0x4005E538)) |
| #define | GPIO_PORTH_AHB_DATA_BITS_R ((volatile uint32_t *)0x4005F000) |
| #define | GPIO_PORTH_AHB_DATA_R (*((volatile uint32_t *)0x4005F3FC)) |
| #define | GPIO_PORTH_AHB_DIR_R (*((volatile uint32_t *)0x4005F400)) |
| #define | GPIO_PORTH_AHB_IS_R (*((volatile uint32_t *)0x4005F404)) |
| #define | GPIO_PORTH_AHB_IBE_R (*((volatile uint32_t *)0x4005F408)) |
| #define | GPIO_PORTH_AHB_IEV_R (*((volatile uint32_t *)0x4005F40C)) |
| #define | GPIO_PORTH_AHB_IM_R (*((volatile uint32_t *)0x4005F410)) |
| #define | GPIO_PORTH_AHB_RIS_R (*((volatile uint32_t *)0x4005F414)) |
| #define | GPIO_PORTH_AHB_MIS_R (*((volatile uint32_t *)0x4005F418)) |
| #define | GPIO_PORTH_AHB_ICR_R (*((volatile uint32_t *)0x4005F41C)) |
| #define | GPIO_PORTH_AHB_AFSEL_R (*((volatile uint32_t *)0x4005F420)) |
| #define | GPIO_PORTH_AHB_DR2R_R (*((volatile uint32_t *)0x4005F500)) |
| #define | GPIO_PORTH_AHB_DR4R_R (*((volatile uint32_t *)0x4005F504)) |
| #define | GPIO_PORTH_AHB_DR8R_R (*((volatile uint32_t *)0x4005F508)) |
| #define | GPIO_PORTH_AHB_ODR_R (*((volatile uint32_t *)0x4005F50C)) |
| #define | GPIO_PORTH_AHB_PUR_R (*((volatile uint32_t *)0x4005F510)) |
| #define | GPIO_PORTH_AHB_PDR_R (*((volatile uint32_t *)0x4005F514)) |
| #define | GPIO_PORTH_AHB_SLR_R (*((volatile uint32_t *)0x4005F518)) |
| #define | GPIO_PORTH_AHB_DEN_R (*((volatile uint32_t *)0x4005F51C)) |
| #define | GPIO_PORTH_AHB_LOCK_R (*((volatile uint32_t *)0x4005F520)) |
| #define | GPIO_PORTH_AHB_CR_R (*((volatile uint32_t *)0x4005F524)) |
| #define | GPIO_PORTH_AHB_AMSEL_R (*((volatile uint32_t *)0x4005F528)) |
| #define | GPIO_PORTH_AHB_PCTL_R (*((volatile uint32_t *)0x4005F52C)) |
| #define | GPIO_PORTH_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005F530)) |
| #define | GPIO_PORTH_AHB_DMACTL_R (*((volatile uint32_t *)0x4005F534)) |
| #define | GPIO_PORTH_AHB_SI_R (*((volatile uint32_t *)0x4005F538)) |
| #define | GPIO_PORTJ_AHB_DATA_BITS_R ((volatile uint32_t *)0x40060000) |
| #define | GPIO_PORTJ_AHB_DATA_R (*((volatile uint32_t *)0x400603FC)) |
| #define | GPIO_PORTJ_AHB_DIR_R (*((volatile uint32_t *)0x40060400)) |
| #define | GPIO_PORTJ_AHB_IS_R (*((volatile uint32_t *)0x40060404)) |
| #define | GPIO_PORTJ_AHB_IBE_R (*((volatile uint32_t *)0x40060408)) |
| #define | GPIO_PORTJ_AHB_IEV_R (*((volatile uint32_t *)0x4006040C)) |
| #define | GPIO_PORTJ_AHB_IM_R (*((volatile uint32_t *)0x40060410)) |
| #define | GPIO_PORTJ_AHB_RIS_R (*((volatile uint32_t *)0x40060414)) |
| #define | GPIO_PORTJ_AHB_MIS_R (*((volatile uint32_t *)0x40060418)) |
| #define | GPIO_PORTJ_AHB_ICR_R (*((volatile uint32_t *)0x4006041C)) |
| #define | GPIO_PORTJ_AHB_AFSEL_R (*((volatile uint32_t *)0x40060420)) |
| #define | GPIO_PORTJ_AHB_DR2R_R (*((volatile uint32_t *)0x40060500)) |
| #define | GPIO_PORTJ_AHB_DR4R_R (*((volatile uint32_t *)0x40060504)) |
| #define | GPIO_PORTJ_AHB_DR8R_R (*((volatile uint32_t *)0x40060508)) |
| #define | GPIO_PORTJ_AHB_ODR_R (*((volatile uint32_t *)0x4006050C)) |
| #define | GPIO_PORTJ_AHB_PUR_R (*((volatile uint32_t *)0x40060510)) |
| #define | GPIO_PORTJ_AHB_PDR_R (*((volatile uint32_t *)0x40060514)) |
| #define | GPIO_PORTJ_AHB_SLR_R (*((volatile uint32_t *)0x40060518)) |
| #define | GPIO_PORTJ_AHB_DEN_R (*((volatile uint32_t *)0x4006051C)) |
| #define | GPIO_PORTJ_AHB_LOCK_R (*((volatile uint32_t *)0x40060520)) |
| #define | GPIO_PORTJ_AHB_CR_R (*((volatile uint32_t *)0x40060524)) |
| #define | GPIO_PORTJ_AHB_AMSEL_R (*((volatile uint32_t *)0x40060528)) |
| #define | GPIO_PORTJ_AHB_PCTL_R (*((volatile uint32_t *)0x4006052C)) |
| #define | GPIO_PORTJ_AHB_ADCCTL_R (*((volatile uint32_t *)0x40060530)) |
| #define | GPIO_PORTJ_AHB_DMACTL_R (*((volatile uint32_t *)0x40060534)) |
| #define | GPIO_PORTJ_AHB_SI_R (*((volatile uint32_t *)0x40060538)) |
| #define | GPIO_PORTK_DATA_BITS_R ((volatile uint32_t *)0x40061000) |
| #define | GPIO_PORTK_DATA_R (*((volatile uint32_t *)0x400613FC)) |
| #define | GPIO_PORTK_DIR_R (*((volatile uint32_t *)0x40061400)) |
| #define | GPIO_PORTK_IS_R (*((volatile uint32_t *)0x40061404)) |
| #define | GPIO_PORTK_IBE_R (*((volatile uint32_t *)0x40061408)) |
| #define | GPIO_PORTK_IEV_R (*((volatile uint32_t *)0x4006140C)) |
| #define | GPIO_PORTK_IM_R (*((volatile uint32_t *)0x40061410)) |
| #define | GPIO_PORTK_RIS_R (*((volatile uint32_t *)0x40061414)) |
| #define | GPIO_PORTK_MIS_R (*((volatile uint32_t *)0x40061418)) |
| #define | GPIO_PORTK_ICR_R (*((volatile uint32_t *)0x4006141C)) |
| #define | GPIO_PORTK_AFSEL_R (*((volatile uint32_t *)0x40061420)) |
| #define | GPIO_PORTK_DR2R_R (*((volatile uint32_t *)0x40061500)) |
| #define | GPIO_PORTK_DR4R_R (*((volatile uint32_t *)0x40061504)) |
| #define | GPIO_PORTK_DR8R_R (*((volatile uint32_t *)0x40061508)) |
| #define | GPIO_PORTK_ODR_R (*((volatile uint32_t *)0x4006150C)) |
| #define | GPIO_PORTK_PUR_R (*((volatile uint32_t *)0x40061510)) |
| #define | GPIO_PORTK_PDR_R (*((volatile uint32_t *)0x40061514)) |
| #define | GPIO_PORTK_SLR_R (*((volatile uint32_t *)0x40061518)) |
| #define | GPIO_PORTK_DEN_R (*((volatile uint32_t *)0x4006151C)) |
| #define | GPIO_PORTK_LOCK_R (*((volatile uint32_t *)0x40061520)) |
| #define | GPIO_PORTK_CR_R (*((volatile uint32_t *)0x40061524)) |
| #define | GPIO_PORTK_AMSEL_R (*((volatile uint32_t *)0x40061528)) |
| #define | GPIO_PORTK_PCTL_R (*((volatile uint32_t *)0x4006152C)) |
| #define | GPIO_PORTK_ADCCTL_R (*((volatile uint32_t *)0x40061530)) |
| #define | GPIO_PORTK_DMACTL_R (*((volatile uint32_t *)0x40061534)) |
| #define | GPIO_PORTK_SI_R (*((volatile uint32_t *)0x40061538)) |
| #define | GPIO_PORTL_DATA_BITS_R ((volatile uint32_t *)0x40062000) |
| #define | GPIO_PORTL_DATA_R (*((volatile uint32_t *)0x400623FC)) |
| #define | GPIO_PORTL_DIR_R (*((volatile uint32_t *)0x40062400)) |
| #define | GPIO_PORTL_IS_R (*((volatile uint32_t *)0x40062404)) |
| #define | GPIO_PORTL_IBE_R (*((volatile uint32_t *)0x40062408)) |
| #define | GPIO_PORTL_IEV_R (*((volatile uint32_t *)0x4006240C)) |
| #define | GPIO_PORTL_IM_R (*((volatile uint32_t *)0x40062410)) |
| #define | GPIO_PORTL_RIS_R (*((volatile uint32_t *)0x40062414)) |
| #define | GPIO_PORTL_MIS_R (*((volatile uint32_t *)0x40062418)) |
| #define | GPIO_PORTL_ICR_R (*((volatile uint32_t *)0x4006241C)) |
| #define | GPIO_PORTL_AFSEL_R (*((volatile uint32_t *)0x40062420)) |
| #define | GPIO_PORTL_DR2R_R (*((volatile uint32_t *)0x40062500)) |
| #define | GPIO_PORTL_DR4R_R (*((volatile uint32_t *)0x40062504)) |
| #define | GPIO_PORTL_DR8R_R (*((volatile uint32_t *)0x40062508)) |
| #define | GPIO_PORTL_ODR_R (*((volatile uint32_t *)0x4006250C)) |
| #define | GPIO_PORTL_PUR_R (*((volatile uint32_t *)0x40062510)) |
| #define | GPIO_PORTL_PDR_R (*((volatile uint32_t *)0x40062514)) |
| #define | GPIO_PORTL_SLR_R (*((volatile uint32_t *)0x40062518)) |
| #define | GPIO_PORTL_DEN_R (*((volatile uint32_t *)0x4006251C)) |
| #define | GPIO_PORTL_LOCK_R (*((volatile uint32_t *)0x40062520)) |
| #define | GPIO_PORTL_CR_R (*((volatile uint32_t *)0x40062524)) |
| #define | GPIO_PORTL_AMSEL_R (*((volatile uint32_t *)0x40062528)) |
| #define | GPIO_PORTL_PCTL_R (*((volatile uint32_t *)0x4006252C)) |
| #define | GPIO_PORTL_ADCCTL_R (*((volatile uint32_t *)0x40062530)) |
| #define | GPIO_PORTL_DMACTL_R (*((volatile uint32_t *)0x40062534)) |
| #define | GPIO_PORTL_SI_R (*((volatile uint32_t *)0x40062538)) |
| #define | GPIO_PORTM_DATA_BITS_R ((volatile uint32_t *)0x40063000) |
| #define | GPIO_PORTM_DATA_R (*((volatile uint32_t *)0x400633FC)) |
| #define | GPIO_PORTM_DIR_R (*((volatile uint32_t *)0x40063400)) |
| #define | GPIO_PORTM_IS_R (*((volatile uint32_t *)0x40063404)) |
| #define | GPIO_PORTM_IBE_R (*((volatile uint32_t *)0x40063408)) |
| #define | GPIO_PORTM_IEV_R (*((volatile uint32_t *)0x4006340C)) |
| #define | GPIO_PORTM_IM_R (*((volatile uint32_t *)0x40063410)) |
| #define | GPIO_PORTM_RIS_R (*((volatile uint32_t *)0x40063414)) |
| #define | GPIO_PORTM_MIS_R (*((volatile uint32_t *)0x40063418)) |
| #define | GPIO_PORTM_ICR_R (*((volatile uint32_t *)0x4006341C)) |
| #define | GPIO_PORTM_AFSEL_R (*((volatile uint32_t *)0x40063420)) |
| #define | GPIO_PORTM_DR2R_R (*((volatile uint32_t *)0x40063500)) |
| #define | GPIO_PORTM_DR4R_R (*((volatile uint32_t *)0x40063504)) |
| #define | GPIO_PORTM_DR8R_R (*((volatile uint32_t *)0x40063508)) |
| #define | GPIO_PORTM_ODR_R (*((volatile uint32_t *)0x4006350C)) |
| #define | GPIO_PORTM_PUR_R (*((volatile uint32_t *)0x40063510)) |
| #define | GPIO_PORTM_PDR_R (*((volatile uint32_t *)0x40063514)) |
| #define | GPIO_PORTM_SLR_R (*((volatile uint32_t *)0x40063518)) |
| #define | GPIO_PORTM_DEN_R (*((volatile uint32_t *)0x4006351C)) |
| #define | GPIO_PORTM_LOCK_R (*((volatile uint32_t *)0x40063520)) |
| #define | GPIO_PORTM_CR_R (*((volatile uint32_t *)0x40063524)) |
| #define | GPIO_PORTM_AMSEL_R (*((volatile uint32_t *)0x40063528)) |
| #define | GPIO_PORTM_PCTL_R (*((volatile uint32_t *)0x4006352C)) |
| #define | GPIO_PORTM_ADCCTL_R (*((volatile uint32_t *)0x40063530)) |
| #define | GPIO_PORTM_DMACTL_R (*((volatile uint32_t *)0x40063534)) |
| #define | GPIO_PORTM_SI_R (*((volatile uint32_t *)0x40063538)) |
| #define | GPIO_PORTN_DATA_BITS_R ((volatile uint32_t *)0x40064000) |
| #define | GPIO_PORTN_DATA_R (*((volatile uint32_t *)0x400643FC)) |
| #define | GPIO_PORTN_DIR_R (*((volatile uint32_t *)0x40064400)) |
| #define | GPIO_PORTN_IS_R (*((volatile uint32_t *)0x40064404)) |
| #define | GPIO_PORTN_IBE_R (*((volatile uint32_t *)0x40064408)) |
| #define | GPIO_PORTN_IEV_R (*((volatile uint32_t *)0x4006440C)) |
| #define | GPIO_PORTN_IM_R (*((volatile uint32_t *)0x40064410)) |
| #define | GPIO_PORTN_RIS_R (*((volatile uint32_t *)0x40064414)) |
| #define | GPIO_PORTN_MIS_R (*((volatile uint32_t *)0x40064418)) |
| #define | GPIO_PORTN_ICR_R (*((volatile uint32_t *)0x4006441C)) |
| #define | GPIO_PORTN_AFSEL_R (*((volatile uint32_t *)0x40064420)) |
| #define | GPIO_PORTN_DR2R_R (*((volatile uint32_t *)0x40064500)) |
| #define | GPIO_PORTN_DR4R_R (*((volatile uint32_t *)0x40064504)) |
| #define | GPIO_PORTN_DR8R_R (*((volatile uint32_t *)0x40064508)) |
| #define | GPIO_PORTN_ODR_R (*((volatile uint32_t *)0x4006450C)) |
| #define | GPIO_PORTN_PUR_R (*((volatile uint32_t *)0x40064510)) |
| #define | GPIO_PORTN_PDR_R (*((volatile uint32_t *)0x40064514)) |
| #define | GPIO_PORTN_SLR_R (*((volatile uint32_t *)0x40064518)) |
| #define | GPIO_PORTN_DEN_R (*((volatile uint32_t *)0x4006451C)) |
| #define | GPIO_PORTN_LOCK_R (*((volatile uint32_t *)0x40064520)) |
| #define | GPIO_PORTN_CR_R (*((volatile uint32_t *)0x40064524)) |
| #define | GPIO_PORTN_AMSEL_R (*((volatile uint32_t *)0x40064528)) |
| #define | GPIO_PORTN_PCTL_R (*((volatile uint32_t *)0x4006452C)) |
| #define | GPIO_PORTN_ADCCTL_R (*((volatile uint32_t *)0x40064530)) |
| #define | GPIO_PORTN_DMACTL_R (*((volatile uint32_t *)0x40064534)) |
| #define | GPIO_PORTN_SI_R (*((volatile uint32_t *)0x40064538)) |
| #define | GPIO_PORTP_DATA_BITS_R ((volatile uint32_t *)0x40065000) |
| #define | GPIO_PORTP_DATA_R (*((volatile uint32_t *)0x400653FC)) |
| #define | GPIO_PORTP_DIR_R (*((volatile uint32_t *)0x40065400)) |
| #define | GPIO_PORTP_IS_R (*((volatile uint32_t *)0x40065404)) |
| #define | GPIO_PORTP_IBE_R (*((volatile uint32_t *)0x40065408)) |
| #define | GPIO_PORTP_IEV_R (*((volatile uint32_t *)0x4006540C)) |
| #define | GPIO_PORTP_IM_R (*((volatile uint32_t *)0x40065410)) |
| #define | GPIO_PORTP_RIS_R (*((volatile uint32_t *)0x40065414)) |
| #define | GPIO_PORTP_MIS_R (*((volatile uint32_t *)0x40065418)) |
| #define | GPIO_PORTP_ICR_R (*((volatile uint32_t *)0x4006541C)) |
| #define | GPIO_PORTP_AFSEL_R (*((volatile uint32_t *)0x40065420)) |
| #define | GPIO_PORTP_DR2R_R (*((volatile uint32_t *)0x40065500)) |
| #define | GPIO_PORTP_DR4R_R (*((volatile uint32_t *)0x40065504)) |
| #define | GPIO_PORTP_DR8R_R (*((volatile uint32_t *)0x40065508)) |
| #define | GPIO_PORTP_ODR_R (*((volatile uint32_t *)0x4006550C)) |
| #define | GPIO_PORTP_PUR_R (*((volatile uint32_t *)0x40065510)) |
| #define | GPIO_PORTP_PDR_R (*((volatile uint32_t *)0x40065514)) |
| #define | GPIO_PORTP_SLR_R (*((volatile uint32_t *)0x40065518)) |
| #define | GPIO_PORTP_DEN_R (*((volatile uint32_t *)0x4006551C)) |
| #define | GPIO_PORTP_LOCK_R (*((volatile uint32_t *)0x40065520)) |
| #define | GPIO_PORTP_CR_R (*((volatile uint32_t *)0x40065524)) |
| #define | GPIO_PORTP_AMSEL_R (*((volatile uint32_t *)0x40065528)) |
| #define | GPIO_PORTP_PCTL_R (*((volatile uint32_t *)0x4006552C)) |
| #define | GPIO_PORTP_ADCCTL_R (*((volatile uint32_t *)0x40065530)) |
| #define | GPIO_PORTP_DMACTL_R (*((volatile uint32_t *)0x40065534)) |
| #define | GPIO_PORTP_SI_R (*((volatile uint32_t *)0x40065538)) |
| #define | EEPROM_EESIZE_R (*((volatile uint32_t *)0x400AF000)) |
| #define | EEPROM_EEBLOCK_R (*((volatile uint32_t *)0x400AF004)) |
| #define | EEPROM_EEOFFSET_R (*((volatile uint32_t *)0x400AF008)) |
| #define | EEPROM_EERDWR_R (*((volatile uint32_t *)0x400AF010)) |
| #define | EEPROM_EERDWRINC_R (*((volatile uint32_t *)0x400AF014)) |
| #define | EEPROM_EEDONE_R (*((volatile uint32_t *)0x400AF018)) |
| #define | EEPROM_EESUPP_R (*((volatile uint32_t *)0x400AF01C)) |
| #define | EEPROM_EEUNLOCK_R (*((volatile uint32_t *)0x400AF020)) |
| #define | EEPROM_EEPROT_R (*((volatile uint32_t *)0x400AF030)) |
| #define | EEPROM_EEPASS0_R (*((volatile uint32_t *)0x400AF034)) |
| #define | EEPROM_EEPASS1_R (*((volatile uint32_t *)0x400AF038)) |
| #define | EEPROM_EEPASS2_R (*((volatile uint32_t *)0x400AF03C)) |
| #define | EEPROM_EEINT_R (*((volatile uint32_t *)0x400AF040)) |
| #define | EEPROM_EEHIDE_R (*((volatile uint32_t *)0x400AF050)) |
| #define | EEPROM_EEDBGME_R (*((volatile uint32_t *)0x400AF080)) |
| #define | EEPROM_PP_R (*((volatile uint32_t *)0x400AFFC0)) |
| #define | I2C4_MSA_R (*((volatile uint32_t *)0x400C0000)) |
| #define | I2C4_MCS_R (*((volatile uint32_t *)0x400C0004)) |
| #define | I2C4_MDR_R (*((volatile uint32_t *)0x400C0008)) |
| #define | I2C4_MTPR_R (*((volatile uint32_t *)0x400C000C)) |
| #define | I2C4_MIMR_R (*((volatile uint32_t *)0x400C0010)) |
| #define | I2C4_MRIS_R (*((volatile uint32_t *)0x400C0014)) |
| #define | I2C4_MMIS_R (*((volatile uint32_t *)0x400C0018)) |
| #define | I2C4_MICR_R (*((volatile uint32_t *)0x400C001C)) |
| #define | I2C4_MCR_R (*((volatile uint32_t *)0x400C0020)) |
| #define | I2C4_MCLKOCNT_R (*((volatile uint32_t *)0x400C0024)) |
| #define | I2C4_MBMON_R (*((volatile uint32_t *)0x400C002C)) |
| #define | I2C4_MCR2_R (*((volatile uint32_t *)0x400C0038)) |
| #define | I2C4_SOAR_R (*((volatile uint32_t *)0x400C0800)) |
| #define | I2C4_SCSR_R (*((volatile uint32_t *)0x400C0804)) |
| #define | I2C4_SDR_R (*((volatile uint32_t *)0x400C0808)) |
| #define | I2C4_SIMR_R (*((volatile uint32_t *)0x400C080C)) |
| #define | I2C4_SRIS_R (*((volatile uint32_t *)0x400C0810)) |
| #define | I2C4_SMIS_R (*((volatile uint32_t *)0x400C0814)) |
| #define | I2C4_SICR_R (*((volatile uint32_t *)0x400C0818)) |
| #define | I2C4_SOAR2_R (*((volatile uint32_t *)0x400C081C)) |
| #define | I2C4_SACKCTL_R (*((volatile uint32_t *)0x400C0820)) |
| #define | I2C4_PP_R (*((volatile uint32_t *)0x400C0FC0)) |
| #define | I2C4_PC_R (*((volatile uint32_t *)0x400C0FC4)) |
| #define | I2C5_MSA_R (*((volatile uint32_t *)0x400C1000)) |
| #define | I2C5_MCS_R (*((volatile uint32_t *)0x400C1004)) |
| #define | I2C5_MDR_R (*((volatile uint32_t *)0x400C1008)) |
| #define | I2C5_MTPR_R (*((volatile uint32_t *)0x400C100C)) |
| #define | I2C5_MIMR_R (*((volatile uint32_t *)0x400C1010)) |
| #define | I2C5_MRIS_R (*((volatile uint32_t *)0x400C1014)) |
| #define | I2C5_MMIS_R (*((volatile uint32_t *)0x400C1018)) |
| #define | I2C5_MICR_R (*((volatile uint32_t *)0x400C101C)) |
| #define | I2C5_MCR_R (*((volatile uint32_t *)0x400C1020)) |
| #define | I2C5_MCLKOCNT_R (*((volatile uint32_t *)0x400C1024)) |
| #define | I2C5_MBMON_R (*((volatile uint32_t *)0x400C102C)) |
| #define | I2C5_MCR2_R (*((volatile uint32_t *)0x400C1038)) |
| #define | I2C5_SOAR_R (*((volatile uint32_t *)0x400C1800)) |
| #define | I2C5_SCSR_R (*((volatile uint32_t *)0x400C1804)) |
| #define | I2C5_SDR_R (*((volatile uint32_t *)0x400C1808)) |
| #define | I2C5_SIMR_R (*((volatile uint32_t *)0x400C180C)) |
| #define | I2C5_SRIS_R (*((volatile uint32_t *)0x400C1810)) |
| #define | I2C5_SMIS_R (*((volatile uint32_t *)0x400C1814)) |
| #define | I2C5_SICR_R (*((volatile uint32_t *)0x400C1818)) |
| #define | I2C5_SOAR2_R (*((volatile uint32_t *)0x400C181C)) |
| #define | I2C5_SACKCTL_R (*((volatile uint32_t *)0x400C1820)) |
| #define | I2C5_PP_R (*((volatile uint32_t *)0x400C1FC0)) |
| #define | I2C5_PC_R (*((volatile uint32_t *)0x400C1FC4)) |
| #define | SYSEXC_RIS_R (*((volatile uint32_t *)0x400F9000)) |
| #define | SYSEXC_IM_R (*((volatile uint32_t *)0x400F9004)) |
| #define | SYSEXC_MIS_R (*((volatile uint32_t *)0x400F9008)) |
| #define | SYSEXC_IC_R (*((volatile uint32_t *)0x400F900C)) |
| #define | HIB_RTCC_R (*((volatile uint32_t *)0x400FC000)) |
| #define | HIB_RTCM0_R (*((volatile uint32_t *)0x400FC004)) |
| #define | HIB_RTCLD_R (*((volatile uint32_t *)0x400FC00C)) |
| #define | HIB_CTL_R (*((volatile uint32_t *)0x400FC010)) |
| #define | HIB_IM_R (*((volatile uint32_t *)0x400FC014)) |
| #define | HIB_RIS_R (*((volatile uint32_t *)0x400FC018)) |
| #define | HIB_MIS_R (*((volatile uint32_t *)0x400FC01C)) |
| #define | HIB_IC_R (*((volatile uint32_t *)0x400FC020)) |
| #define | HIB_RTCT_R (*((volatile uint32_t *)0x400FC024)) |
| #define | HIB_RTCSS_R (*((volatile uint32_t *)0x400FC028)) |
| #define | HIB_DATA_R (*((volatile uint32_t *)0x400FC030)) |
| #define | FLASH_FMA_R (*((volatile uint32_t *)0x400FD000)) |
| #define | FLASH_FMD_R (*((volatile uint32_t *)0x400FD004)) |
| #define | FLASH_FMC_R (*((volatile uint32_t *)0x400FD008)) |
| #define | FLASH_FCRIS_R (*((volatile uint32_t *)0x400FD00C)) |
| #define | FLASH_FCIM_R (*((volatile uint32_t *)0x400FD010)) |
| #define | FLASH_FCMISC_R (*((volatile uint32_t *)0x400FD014)) |
| #define | FLASH_FMC2_R (*((volatile uint32_t *)0x400FD020)) |
| #define | FLASH_FWBVAL_R (*((volatile uint32_t *)0x400FD030)) |
| #define | FLASH_FWBN_R (*((volatile uint32_t *)0x400FD100)) |
| #define | FLASH_FSIZE_R (*((volatile uint32_t *)0x400FDFC0)) |
| #define | FLASH_SSIZE_R (*((volatile uint32_t *)0x400FDFC4)) |
| #define | FLASH_ROMSWMAP_R (*((volatile uint32_t *)0x400FDFCC)) |
| #define | FLASH_RMCTL_R (*((volatile uint32_t *)0x400FE0F0)) |
| #define | FLASH_BOOTCFG_R (*((volatile uint32_t *)0x400FE1D0)) |
| #define | FLASH_USERREG0_R (*((volatile uint32_t *)0x400FE1E0)) |
| #define | FLASH_USERREG1_R (*((volatile uint32_t *)0x400FE1E4)) |
| #define | FLASH_USERREG2_R (*((volatile uint32_t *)0x400FE1E8)) |
| #define | FLASH_USERREG3_R (*((volatile uint32_t *)0x400FE1EC)) |
| #define | FLASH_FMPRE0_R (*((volatile uint32_t *)0x400FE200)) |
| #define | FLASH_FMPRE1_R (*((volatile uint32_t *)0x400FE204)) |
| #define | FLASH_FMPRE2_R (*((volatile uint32_t *)0x400FE208)) |
| #define | FLASH_FMPRE3_R (*((volatile uint32_t *)0x400FE20C)) |
| #define | FLASH_FMPPE0_R (*((volatile uint32_t *)0x400FE400)) |
| #define | FLASH_FMPPE1_R (*((volatile uint32_t *)0x400FE404)) |
| #define | FLASH_FMPPE2_R (*((volatile uint32_t *)0x400FE408)) |
| #define | FLASH_FMPPE3_R (*((volatile uint32_t *)0x400FE40C)) |
| #define | SYSCTL_DID0_R (*((volatile uint32_t *)0x400FE000)) |
| #define | SYSCTL_DID1_R (*((volatile uint32_t *)0x400FE004)) |
| #define | SYSCTL_DC0_R (*((volatile uint32_t *)0x400FE008)) |
| #define | SYSCTL_DC1_R (*((volatile uint32_t *)0x400FE010)) |
| #define | SYSCTL_DC2_R (*((volatile uint32_t *)0x400FE014)) |
| #define | SYSCTL_DC3_R (*((volatile uint32_t *)0x400FE018)) |
| #define | SYSCTL_DC4_R (*((volatile uint32_t *)0x400FE01C)) |
| #define | SYSCTL_DC5_R (*((volatile uint32_t *)0x400FE020)) |
| #define | SYSCTL_DC6_R (*((volatile uint32_t *)0x400FE024)) |
| #define | SYSCTL_DC7_R (*((volatile uint32_t *)0x400FE028)) |
| #define | SYSCTL_DC8_R (*((volatile uint32_t *)0x400FE02C)) |
| #define | SYSCTL_PBORCTL_R (*((volatile uint32_t *)0x400FE030)) |
| #define | SYSCTL_SRCR0_R (*((volatile uint32_t *)0x400FE040)) |
| #define | SYSCTL_SRCR1_R (*((volatile uint32_t *)0x400FE044)) |
| #define | SYSCTL_SRCR2_R (*((volatile uint32_t *)0x400FE048)) |
| #define | SYSCTL_RIS_R (*((volatile uint32_t *)0x400FE050)) |
| #define | SYSCTL_IMC_R (*((volatile uint32_t *)0x400FE054)) |
| #define | SYSCTL_MISC_R (*((volatile uint32_t *)0x400FE058)) |
| #define | SYSCTL_RESC_R (*((volatile uint32_t *)0x400FE05C)) |
| #define | SYSCTL_RCC_R (*((volatile uint32_t *)0x400FE060)) |
| #define | SYSCTL_GPIOHBCTL_R (*((volatile uint32_t *)0x400FE06C)) |
| #define | SYSCTL_RCC2_R (*((volatile uint32_t *)0x400FE070)) |
| #define | SYSCTL_MOSCCTL_R (*((volatile uint32_t *)0x400FE07C)) |
| #define | SYSCTL_RCGC0_R (*((volatile uint32_t *)0x400FE100)) |
| #define | SYSCTL_RCGC1_R (*((volatile uint32_t *)0x400FE104)) |
| #define | SYSCTL_RCGC2_R (*((volatile uint32_t *)0x400FE108)) |
| #define | SYSCTL_SCGC0_R (*((volatile uint32_t *)0x400FE110)) |
| #define | SYSCTL_SCGC1_R (*((volatile uint32_t *)0x400FE114)) |
| #define | SYSCTL_SCGC2_R (*((volatile uint32_t *)0x400FE118)) |
| #define | SYSCTL_DCGC0_R (*((volatile uint32_t *)0x400FE120)) |
| #define | SYSCTL_DCGC1_R (*((volatile uint32_t *)0x400FE124)) |
| #define | SYSCTL_DCGC2_R (*((volatile uint32_t *)0x400FE128)) |
| #define | SYSCTL_DSLPCLKCFG_R (*((volatile uint32_t *)0x400FE144)) |
| #define | SYSCTL_SYSPROP_R (*((volatile uint32_t *)0x400FE14C)) |
| #define | SYSCTL_PIOSCCAL_R (*((volatile uint32_t *)0x400FE150)) |
| #define | SYSCTL_PIOSCSTAT_R (*((volatile uint32_t *)0x400FE154)) |
| #define | SYSCTL_PLLFREQ0_R (*((volatile uint32_t *)0x400FE160)) |
| #define | SYSCTL_PLLFREQ1_R (*((volatile uint32_t *)0x400FE164)) |
| #define | SYSCTL_PLLSTAT_R (*((volatile uint32_t *)0x400FE168)) |
| #define | SYSCTL_SLPPWRCFG_R (*((volatile uint32_t *)0x400FE188)) |
| #define | SYSCTL_DSLPPWRCFG_R (*((volatile uint32_t *)0x400FE18C)) |
| #define | SYSCTL_DC9_R (*((volatile uint32_t *)0x400FE190)) |
| #define | SYSCTL_NVMSTAT_R (*((volatile uint32_t *)0x400FE1A0)) |
| #define | SYSCTL_LDOSPCTL_R (*((volatile uint32_t *)0x400FE1B4)) |
| #define | SYSCTL_LDODPCTL_R (*((volatile uint32_t *)0x400FE1BC)) |
| #define | SYSCTL_PPWD_R (*((volatile uint32_t *)0x400FE300)) |
| #define | SYSCTL_PPTIMER_R (*((volatile uint32_t *)0x400FE304)) |
| #define | SYSCTL_PPGPIO_R (*((volatile uint32_t *)0x400FE308)) |
| #define | SYSCTL_PPDMA_R (*((volatile uint32_t *)0x400FE30C)) |
| #define | SYSCTL_PPHIB_R (*((volatile uint32_t *)0x400FE314)) |
| #define | SYSCTL_PPUART_R (*((volatile uint32_t *)0x400FE318)) |
| #define | SYSCTL_PPSSI_R (*((volatile uint32_t *)0x400FE31C)) |
| #define | SYSCTL_PPI2C_R (*((volatile uint32_t *)0x400FE320)) |
| #define | SYSCTL_PPUSB_R (*((volatile uint32_t *)0x400FE328)) |
| #define | SYSCTL_PPCAN_R (*((volatile uint32_t *)0x400FE334)) |
| #define | SYSCTL_PPADC_R (*((volatile uint32_t *)0x400FE338)) |
| #define | SYSCTL_PPACMP_R (*((volatile uint32_t *)0x400FE33C)) |
| #define | SYSCTL_PPPWM_R (*((volatile uint32_t *)0x400FE340)) |
| #define | SYSCTL_PPQEI_R (*((volatile uint32_t *)0x400FE344)) |
| #define | SYSCTL_PPEEPROM_R (*((volatile uint32_t *)0x400FE358)) |
| #define | SYSCTL_PPWTIMER_R (*((volatile uint32_t *)0x400FE35C)) |
| #define | SYSCTL_SRWD_R (*((volatile uint32_t *)0x400FE500)) |
| #define | SYSCTL_SRTIMER_R (*((volatile uint32_t *)0x400FE504)) |
| #define | SYSCTL_SRGPIO_R (*((volatile uint32_t *)0x400FE508)) |
| #define | SYSCTL_SRDMA_R (*((volatile uint32_t *)0x400FE50C)) |
| #define | SYSCTL_SRHIB_R (*((volatile uint32_t *)0x400FE514)) |
| #define | SYSCTL_SRUART_R (*((volatile uint32_t *)0x400FE518)) |
| #define | SYSCTL_SRSSI_R (*((volatile uint32_t *)0x400FE51C)) |
| #define | SYSCTL_SRI2C_R (*((volatile uint32_t *)0x400FE520)) |
| #define | SYSCTL_SRUSB_R (*((volatile uint32_t *)0x400FE528)) |
| #define | SYSCTL_SRCAN_R (*((volatile uint32_t *)0x400FE534)) |
| #define | SYSCTL_SRADC_R (*((volatile uint32_t *)0x400FE538)) |
| #define | SYSCTL_SRACMP_R (*((volatile uint32_t *)0x400FE53C)) |
| #define | SYSCTL_SRPWM_R (*((volatile uint32_t *)0x400FE540)) |
| #define | SYSCTL_SRQEI_R (*((volatile uint32_t *)0x400FE544)) |
| #define | SYSCTL_SREEPROM_R (*((volatile uint32_t *)0x400FE558)) |
| #define | SYSCTL_SRWTIMER_R (*((volatile uint32_t *)0x400FE55C)) |
| #define | SYSCTL_RCGCWD_R (*((volatile uint32_t *)0x400FE600)) |
| #define | SYSCTL_RCGCTIMER_R (*((volatile uint32_t *)0x400FE604)) |
| #define | SYSCTL_RCGCGPIO_R (*((volatile uint32_t *)0x400FE608)) |
| #define | SYSCTL_RCGCDMA_R (*((volatile uint32_t *)0x400FE60C)) |
| #define | SYSCTL_RCGCHIB_R (*((volatile uint32_t *)0x400FE614)) |
| #define | SYSCTL_RCGCUART_R (*((volatile uint32_t *)0x400FE618)) |
| #define | SYSCTL_RCGCSSI_R (*((volatile uint32_t *)0x400FE61C)) |
| #define | SYSCTL_RCGCI2C_R (*((volatile uint32_t *)0x400FE620)) |
| #define | SYSCTL_RCGCUSB_R (*((volatile uint32_t *)0x400FE628)) |
| #define | SYSCTL_RCGCCAN_R (*((volatile uint32_t *)0x400FE634)) |
| #define | SYSCTL_RCGCADC_R (*((volatile uint32_t *)0x400FE638)) |
| #define | SYSCTL_RCGCACMP_R (*((volatile uint32_t *)0x400FE63C)) |
| #define | SYSCTL_RCGCPWM_R (*((volatile uint32_t *)0x400FE640)) |
| #define | SYSCTL_RCGCQEI_R (*((volatile uint32_t *)0x400FE644)) |
| #define | SYSCTL_RCGCEEPROM_R (*((volatile uint32_t *)0x400FE658)) |
| #define | SYSCTL_RCGCWTIMER_R (*((volatile uint32_t *)0x400FE65C)) |
| #define | SYSCTL_SCGCWD_R (*((volatile uint32_t *)0x400FE700)) |
| #define | SYSCTL_SCGCTIMER_R (*((volatile uint32_t *)0x400FE704)) |
| #define | SYSCTL_SCGCGPIO_R (*((volatile uint32_t *)0x400FE708)) |
| #define | SYSCTL_SCGCDMA_R (*((volatile uint32_t *)0x400FE70C)) |
| #define | SYSCTL_SCGCHIB_R (*((volatile uint32_t *)0x400FE714)) |
| #define | SYSCTL_SCGCUART_R (*((volatile uint32_t *)0x400FE718)) |
| #define | SYSCTL_SCGCSSI_R (*((volatile uint32_t *)0x400FE71C)) |
| #define | SYSCTL_SCGCI2C_R (*((volatile uint32_t *)0x400FE720)) |
| #define | SYSCTL_SCGCUSB_R (*((volatile uint32_t *)0x400FE728)) |
| #define | SYSCTL_SCGCCAN_R (*((volatile uint32_t *)0x400FE734)) |
| #define | SYSCTL_SCGCADC_R (*((volatile uint32_t *)0x400FE738)) |
| #define | SYSCTL_SCGCACMP_R (*((volatile uint32_t *)0x400FE73C)) |
| #define | SYSCTL_SCGCPWM_R (*((volatile uint32_t *)0x400FE740)) |
| #define | SYSCTL_SCGCQEI_R (*((volatile uint32_t *)0x400FE744)) |
| #define | SYSCTL_SCGCEEPROM_R (*((volatile uint32_t *)0x400FE758)) |
| #define | SYSCTL_SCGCWTIMER_R (*((volatile uint32_t *)0x400FE75C)) |
| #define | SYSCTL_DCGCWD_R (*((volatile uint32_t *)0x400FE800)) |
| #define | SYSCTL_DCGCTIMER_R (*((volatile uint32_t *)0x400FE804)) |
| #define | SYSCTL_DCGCGPIO_R (*((volatile uint32_t *)0x400FE808)) |
| #define | SYSCTL_DCGCDMA_R (*((volatile uint32_t *)0x400FE80C)) |
| #define | SYSCTL_DCGCHIB_R (*((volatile uint32_t *)0x400FE814)) |
| #define | SYSCTL_DCGCUART_R (*((volatile uint32_t *)0x400FE818)) |
| #define | SYSCTL_DCGCSSI_R (*((volatile uint32_t *)0x400FE81C)) |
| #define | SYSCTL_DCGCI2C_R (*((volatile uint32_t *)0x400FE820)) |
| #define | SYSCTL_DCGCUSB_R (*((volatile uint32_t *)0x400FE828)) |
| #define | SYSCTL_DCGCCAN_R (*((volatile uint32_t *)0x400FE834)) |
| #define | SYSCTL_DCGCADC_R (*((volatile uint32_t *)0x400FE838)) |
| #define | SYSCTL_DCGCACMP_R (*((volatile uint32_t *)0x400FE83C)) |
| #define | SYSCTL_DCGCPWM_R (*((volatile uint32_t *)0x400FE840)) |
| #define | SYSCTL_DCGCQEI_R (*((volatile uint32_t *)0x400FE844)) |
| #define | SYSCTL_DCGCEEPROM_R (*((volatile uint32_t *)0x400FE858)) |
| #define | SYSCTL_DCGCWTIMER_R (*((volatile uint32_t *)0x400FE85C)) |
| #define | SYSCTL_PRWD_R (*((volatile uint32_t *)0x400FEA00)) |
| #define | SYSCTL_PRTIMER_R (*((volatile uint32_t *)0x400FEA04)) |
| #define | SYSCTL_PRGPIO_R (*((volatile uint32_t *)0x400FEA08)) |
| #define | SYSCTL_PRDMA_R (*((volatile uint32_t *)0x400FEA0C)) |
| #define | SYSCTL_PRHIB_R (*((volatile uint32_t *)0x400FEA14)) |
| #define | SYSCTL_PRUART_R (*((volatile uint32_t *)0x400FEA18)) |
| #define | SYSCTL_PRSSI_R (*((volatile uint32_t *)0x400FEA1C)) |
| #define | SYSCTL_PRI2C_R (*((volatile uint32_t *)0x400FEA20)) |
| #define | SYSCTL_PRUSB_R (*((volatile uint32_t *)0x400FEA28)) |
| #define | SYSCTL_PRCAN_R (*((volatile uint32_t *)0x400FEA34)) |
| #define | SYSCTL_PRADC_R (*((volatile uint32_t *)0x400FEA38)) |
| #define | SYSCTL_PRACMP_R (*((volatile uint32_t *)0x400FEA3C)) |
| #define | SYSCTL_PRPWM_R (*((volatile uint32_t *)0x400FEA40)) |
| #define | SYSCTL_PRQEI_R (*((volatile uint32_t *)0x400FEA44)) |
| #define | SYSCTL_PREEPROM_R (*((volatile uint32_t *)0x400FEA58)) |
| #define | SYSCTL_PRWTIMER_R (*((volatile uint32_t *)0x400FEA5C)) |
| #define | UDMA_STAT_R (*((volatile uint32_t *)0x400FF000)) |
| #define | UDMA_CFG_R (*((volatile uint32_t *)0x400FF004)) |
| #define | UDMA_CTLBASE_R (*((volatile uint32_t *)0x400FF008)) |
| #define | UDMA_ALTBASE_R (*((volatile uint32_t *)0x400FF00C)) |
| #define | UDMA_WAITSTAT_R (*((volatile uint32_t *)0x400FF010)) |
| #define | UDMA_SWREQ_R (*((volatile uint32_t *)0x400FF014)) |
| #define | UDMA_USEBURSTSET_R (*((volatile uint32_t *)0x400FF018)) |
| #define | UDMA_USEBURSTCLR_R (*((volatile uint32_t *)0x400FF01C)) |
| #define | UDMA_REQMASKSET_R (*((volatile uint32_t *)0x400FF020)) |
| #define | UDMA_REQMASKCLR_R (*((volatile uint32_t *)0x400FF024)) |
| #define | UDMA_ENASET_R (*((volatile uint32_t *)0x400FF028)) |
| #define | UDMA_ENACLR_R (*((volatile uint32_t *)0x400FF02C)) |
| #define | UDMA_ALTSET_R (*((volatile uint32_t *)0x400FF030)) |
| #define | UDMA_ALTCLR_R (*((volatile uint32_t *)0x400FF034)) |
| #define | UDMA_PRIOSET_R (*((volatile uint32_t *)0x400FF038)) |
| #define | UDMA_PRIOCLR_R (*((volatile uint32_t *)0x400FF03C)) |
| #define | UDMA_ERRCLR_R (*((volatile uint32_t *)0x400FF04C)) |
| #define | UDMA_CHASGN_R (*((volatile uint32_t *)0x400FF500)) |
| #define | UDMA_CHIS_R (*((volatile uint32_t *)0x400FF504)) |
| #define | UDMA_CHMAP0_R (*((volatile uint32_t *)0x400FF510)) |
| #define | UDMA_CHMAP1_R (*((volatile uint32_t *)0x400FF514)) |
| #define | UDMA_CHMAP2_R (*((volatile uint32_t *)0x400FF518)) |
| #define | UDMA_CHMAP3_R (*((volatile uint32_t *)0x400FF51C)) |
| #define | UDMA_SRCENDP 0x00000000 |
| #define | UDMA_DSTENDP 0x00000004 |
| #define | UDMA_CHCTL 0x00000008 |
| #define | NVIC_ACTLR_R (*((volatile uint32_t *)0xE000E008)) |
| #define | NVIC_ST_CTRL_R (*((volatile uint32_t *)0xE000E010)) |
| #define | NVIC_ST_RELOAD_R (*((volatile uint32_t *)0xE000E014)) |
| #define | NVIC_ST_CURRENT_R (*((volatile uint32_t *)0xE000E018)) |
| #define | NVIC_EN0_R (*((volatile uint32_t *)0xE000E100)) |
| #define | NVIC_EN1_R (*((volatile uint32_t *)0xE000E104)) |
| #define | NVIC_EN2_R (*((volatile uint32_t *)0xE000E108)) |
| #define | NVIC_EN3_R (*((volatile uint32_t *)0xE000E10C)) |
| #define | NVIC_EN4_R (*((volatile uint32_t *)0xE000E110)) |
| #define | NVIC_DIS0_R (*((volatile uint32_t *)0xE000E180)) |
| #define | NVIC_DIS1_R (*((volatile uint32_t *)0xE000E184)) |
| #define | NVIC_DIS2_R (*((volatile uint32_t *)0xE000E188)) |
| #define | NVIC_DIS3_R (*((volatile uint32_t *)0xE000E18C)) |
| #define | NVIC_DIS4_R (*((volatile uint32_t *)0xE000E190)) |
| #define | NVIC_PEND0_R (*((volatile uint32_t *)0xE000E200)) |
| #define | NVIC_PEND1_R (*((volatile uint32_t *)0xE000E204)) |
| #define | NVIC_PEND2_R (*((volatile uint32_t *)0xE000E208)) |
| #define | NVIC_PEND3_R (*((volatile uint32_t *)0xE000E20C)) |
| #define | NVIC_PEND4_R (*((volatile uint32_t *)0xE000E210)) |
| #define | NVIC_UNPEND0_R (*((volatile uint32_t *)0xE000E280)) |
| #define | NVIC_UNPEND1_R (*((volatile uint32_t *)0xE000E284)) |
| #define | NVIC_UNPEND2_R (*((volatile uint32_t *)0xE000E288)) |
| #define | NVIC_UNPEND3_R (*((volatile uint32_t *)0xE000E28C)) |
| #define | NVIC_UNPEND4_R (*((volatile uint32_t *)0xE000E290)) |
| #define | NVIC_ACTIVE0_R (*((volatile uint32_t *)0xE000E300)) |
| #define | NVIC_ACTIVE1_R (*((volatile uint32_t *)0xE000E304)) |
| #define | NVIC_ACTIVE2_R (*((volatile uint32_t *)0xE000E308)) |
| #define | NVIC_ACTIVE3_R (*((volatile uint32_t *)0xE000E30C)) |
| #define | NVIC_ACTIVE4_R (*((volatile uint32_t *)0xE000E310)) |
| #define | NVIC_PRI0_R (*((volatile uint32_t *)0xE000E400)) |
| #define | NVIC_PRI1_R (*((volatile uint32_t *)0xE000E404)) |
| #define | NVIC_PRI2_R (*((volatile uint32_t *)0xE000E408)) |
| #define | NVIC_PRI3_R (*((volatile uint32_t *)0xE000E40C)) |
| #define | NVIC_PRI4_R (*((volatile uint32_t *)0xE000E410)) |
| #define | NVIC_PRI5_R (*((volatile uint32_t *)0xE000E414)) |
| #define | NVIC_PRI6_R (*((volatile uint32_t *)0xE000E418)) |
| #define | NVIC_PRI7_R (*((volatile uint32_t *)0xE000E41C)) |
| #define | NVIC_PRI8_R (*((volatile uint32_t *)0xE000E420)) |
| #define | NVIC_PRI9_R (*((volatile uint32_t *)0xE000E424)) |
| #define | NVIC_PRI10_R (*((volatile uint32_t *)0xE000E428)) |
| #define | NVIC_PRI11_R (*((volatile uint32_t *)0xE000E42C)) |
| #define | NVIC_PRI12_R (*((volatile uint32_t *)0xE000E430)) |
| #define | NVIC_PRI13_R (*((volatile uint32_t *)0xE000E434)) |
| #define | NVIC_PRI14_R (*((volatile uint32_t *)0xE000E438)) |
| #define | NVIC_PRI15_R (*((volatile uint32_t *)0xE000E43C)) |
| #define | NVIC_PRI16_R (*((volatile uint32_t *)0xE000E440)) |
| #define | NVIC_PRI17_R (*((volatile uint32_t *)0xE000E444)) |
| #define | NVIC_PRI18_R (*((volatile uint32_t *)0xE000E448)) |
| #define | NVIC_PRI19_R (*((volatile uint32_t *)0xE000E44C)) |
| #define | NVIC_PRI20_R (*((volatile uint32_t *)0xE000E450)) |
| #define | NVIC_PRI21_R (*((volatile uint32_t *)0xE000E454)) |
| #define | NVIC_PRI22_R (*((volatile uint32_t *)0xE000E458)) |
| #define | NVIC_PRI23_R (*((volatile uint32_t *)0xE000E45C)) |
| #define | NVIC_PRI24_R (*((volatile uint32_t *)0xE000E460)) |
| #define | NVIC_PRI25_R (*((volatile uint32_t *)0xE000E464)) |
| #define | NVIC_PRI26_R (*((volatile uint32_t *)0xE000E468)) |
| #define | NVIC_PRI27_R (*((volatile uint32_t *)0xE000E46C)) |
| #define | NVIC_PRI28_R (*((volatile uint32_t *)0xE000E470)) |
| #define | NVIC_PRI29_R (*((volatile uint32_t *)0xE000E474)) |
| #define | NVIC_PRI30_R (*((volatile uint32_t *)0xE000E478)) |
| #define | NVIC_PRI31_R (*((volatile uint32_t *)0xE000E47C)) |
| #define | NVIC_PRI32_R (*((volatile uint32_t *)0xE000E480)) |
| #define | NVIC_PRI33_R (*((volatile uint32_t *)0xE000E484)) |
| #define | NVIC_PRI34_R (*((volatile uint32_t *)0xE000E488)) |
| #define | NVIC_CPUID_R (*((volatile uint32_t *)0xE000ED00)) |
| #define | NVIC_INT_CTRL_R (*((volatile uint32_t *)0xE000ED04)) |
| #define | NVIC_VTABLE_R (*((volatile uint32_t *)0xE000ED08)) |
| #define | NVIC_APINT_R (*((volatile uint32_t *)0xE000ED0C)) |
| #define | NVIC_SYS_CTRL_R (*((volatile uint32_t *)0xE000ED10)) |
| #define | NVIC_CFG_CTRL_R (*((volatile uint32_t *)0xE000ED14)) |
| #define | NVIC_SYS_PRI1_R (*((volatile uint32_t *)0xE000ED18)) |
| #define | NVIC_SYS_PRI2_R (*((volatile uint32_t *)0xE000ED1C)) |
| #define | NVIC_SYS_PRI3_R (*((volatile uint32_t *)0xE000ED20)) |
| #define | NVIC_SYS_HND_CTRL_R (*((volatile uint32_t *)0xE000ED24)) |
| #define | NVIC_FAULT_STAT_R (*((volatile uint32_t *)0xE000ED28)) |
| #define | NVIC_HFAULT_STAT_R (*((volatile uint32_t *)0xE000ED2C)) |
| #define | NVIC_DEBUG_STAT_R (*((volatile uint32_t *)0xE000ED30)) |
| #define | NVIC_MM_ADDR_R (*((volatile uint32_t *)0xE000ED34)) |
| #define | NVIC_FAULT_ADDR_R (*((volatile uint32_t *)0xE000ED38)) |
| #define | NVIC_CPAC_R (*((volatile uint32_t *)0xE000ED88)) |
| #define | NVIC_MPU_TYPE_R (*((volatile uint32_t *)0xE000ED90)) |
| #define | NVIC_MPU_CTRL_R (*((volatile uint32_t *)0xE000ED94)) |
| #define | NVIC_MPU_NUMBER_R (*((volatile uint32_t *)0xE000ED98)) |
| #define | NVIC_MPU_BASE_R (*((volatile uint32_t *)0xE000ED9C)) |
| #define | NVIC_MPU_ATTR_R (*((volatile uint32_t *)0xE000EDA0)) |
| #define | NVIC_MPU_BASE1_R (*((volatile uint32_t *)0xE000EDA4)) |
| #define | NVIC_MPU_ATTR1_R (*((volatile uint32_t *)0xE000EDA8)) |
| #define | NVIC_MPU_BASE2_R (*((volatile uint32_t *)0xE000EDAC)) |
| #define | NVIC_MPU_ATTR2_R (*((volatile uint32_t *)0xE000EDB0)) |
| #define | NVIC_MPU_BASE3_R (*((volatile uint32_t *)0xE000EDB4)) |
| #define | NVIC_MPU_ATTR3_R (*((volatile uint32_t *)0xE000EDB8)) |
| #define | NVIC_DBG_CTRL_R (*((volatile uint32_t *)0xE000EDF0)) |
| #define | NVIC_DBG_XFER_R (*((volatile uint32_t *)0xE000EDF4)) |
| #define | NVIC_DBG_DATA_R (*((volatile uint32_t *)0xE000EDF8)) |
| #define | NVIC_DBG_INT_R (*((volatile uint32_t *)0xE000EDFC)) |
| #define | NVIC_SW_TRIG_R (*((volatile uint32_t *)0xE000EF00)) |
| #define | NVIC_FPCC_R (*((volatile uint32_t *)0xE000EF34)) |
| #define | NVIC_FPCA_R (*((volatile uint32_t *)0xE000EF38)) |
| #define | NVIC_FPDSC_R (*((volatile uint32_t *)0xE000EF3C)) |
| #define | WDT_LOAD_M 0xFFFFFFFF |
| #define | WDT_LOAD_S 0 |
| #define | WDT_VALUE_M 0xFFFFFFFF |
| #define | WDT_VALUE_S 0 |
| #define | WDT_CTL_WRC 0x80000000 |
| #define | WDT_CTL_INTTYPE 0x00000004 |
| #define | WDT_CTL_RESEN 0x00000002 |
| #define | WDT_CTL_INTEN 0x00000001 |
| #define | WDT_ICR_M 0xFFFFFFFF |
| #define | WDT_ICR_S 0 |
| #define | WDT_RIS_WDTRIS 0x00000001 |
| #define | WDT_MIS_WDTMIS 0x00000001 |
| #define | WDT_TEST_STALL 0x00000100 |
| #define | WDT_LOCK_M 0xFFFFFFFF |
| #define | WDT_LOCK_UNLOCKED 0x00000000 |
| #define | WDT_LOCK_LOCKED 0x00000001 |
| #define | WDT_LOCK_UNLOCK 0x1ACCE551 |
| #define | GPIO_IM_GPIO_M 0x000000FF |
| #define | GPIO_IM_GPIO_S 0 |
| #define | GPIO_RIS_GPIO_M 0x000000FF |
| #define | GPIO_RIS_GPIO_S 0 |
| #define | GPIO_MIS_GPIO_M 0x000000FF |
| #define | GPIO_MIS_GPIO_S 0 |
| #define | GPIO_ICR_GPIO_M 0x000000FF |
| #define | GPIO_ICR_GPIO_S 0 |
| #define | GPIO_LOCK_M 0xFFFFFFFF |
| #define | GPIO_LOCK_UNLOCKED 0x00000000 |
| #define | GPIO_LOCK_LOCKED 0x00000001 |
| #define | GPIO_LOCK_KEY 0x4C4F434B |
| #define | GPIO_SI_SUM 0x00000001 |
| #define | GPIO_PCTL_PA7_M 0xF0000000 |
| #define | GPIO_PCTL_PA7_I2C1SDA 0x30000000 |
| #define | GPIO_PCTL_PA7_M1PWM3 0x50000000 |
| #define | GPIO_PCTL_PA6_M 0x0F000000 |
| #define | GPIO_PCTL_PA6_I2C1SCL 0x03000000 |
| #define | GPIO_PCTL_PA6_M1PWM2 0x05000000 |
| #define | GPIO_PCTL_PA5_M 0x00F00000 |
| #define | GPIO_PCTL_PA5_SSI0TX 0x00200000 |
| #define | GPIO_PCTL_PA4_M 0x000F0000 |
| #define | GPIO_PCTL_PA4_SSI0RX 0x00020000 |
| #define | GPIO_PCTL_PA3_M 0x0000F000 |
| #define | GPIO_PCTL_PA3_SSI0FSS 0x00002000 |
| #define | GPIO_PCTL_PA2_M 0x00000F00 |
| #define | GPIO_PCTL_PA2_SSI0CLK 0x00000200 |
| #define | GPIO_PCTL_PA1_M 0x000000F0 |
| #define | GPIO_PCTL_PA1_U0TX 0x00000010 |
| #define | GPIO_PCTL_PA1_CAN1TX 0x00000080 |
| #define | GPIO_PCTL_PA0_M 0x0000000F |
| #define | GPIO_PCTL_PA0_U0RX 0x00000001 |
| #define | GPIO_PCTL_PA0_CAN1RX 0x00000008 |
| #define | GPIO_PCTL_PB5_M 0x00F00000 |
| #define | GPIO_PCTL_PB5_SSI2FSS 0x00200000 |
| #define | GPIO_PCTL_PB5_M0PWM3 0x00400000 |
| #define | GPIO_PCTL_PB5_T1CCP1 0x00700000 |
| #define | GPIO_PCTL_PB5_CAN0TX 0x00800000 |
| #define | GPIO_PCTL_PB4_M 0x000F0000 |
| #define | GPIO_PCTL_PB4_SSI2CLK 0x00020000 |
| #define | GPIO_PCTL_PB4_M0PWM2 0x00040000 |
| #define | GPIO_PCTL_PB4_T1CCP0 0x00070000 |
| #define | GPIO_PCTL_PB4_CAN0RX 0x00080000 |
| #define | GPIO_PCTL_PB3_M 0x0000F000 |
| #define | GPIO_PCTL_PB3_I2C0SDA 0x00003000 |
| #define | GPIO_PCTL_PB3_T3CCP1 0x00007000 |
| #define | GPIO_PCTL_PB2_M 0x00000F00 |
| #define | GPIO_PCTL_PB2_I2C0SCL 0x00000300 |
| #define | GPIO_PCTL_PB2_T3CCP0 0x00000700 |
| #define | GPIO_PCTL_PB1_M 0x000000F0 |
| #define | GPIO_PCTL_PB1_USB0VBUS 0x00000000 |
| #define | GPIO_PCTL_PB1_U1TX 0x00000010 |
| #define | GPIO_PCTL_PB1_T2CCP1 0x00000070 |
| #define | GPIO_PCTL_PB0_M 0x0000000F |
| #define | GPIO_PCTL_PB0_USB0ID 0x00000000 |
| #define | GPIO_PCTL_PB0_U1RX 0x00000001 |
| #define | GPIO_PCTL_PB0_T2CCP0 0x00000007 |
| #define | GPIO_PCTL_PC7_M 0xF0000000 |
| #define | GPIO_PCTL_PC7_U3TX 0x10000000 |
| #define | GPIO_PCTL_PC7_WT1CCP1 0x70000000 |
| #define | GPIO_PCTL_PC7_USB0PFLT 0x80000000 |
| #define | GPIO_PCTL_PC6_M 0x0F000000 |
| #define | GPIO_PCTL_PC6_U3RX 0x01000000 |
| #define | GPIO_PCTL_PC6_PHB1 0x06000000 |
| #define | GPIO_PCTL_PC6_WT1CCP0 0x07000000 |
| #define | GPIO_PCTL_PC6_USB0EPEN 0x08000000 |
| #define | GPIO_PCTL_PC5_M 0x00F00000 |
| #define | GPIO_PCTL_PC5_U4TX 0x00100000 |
| #define | GPIO_PCTL_PC5_U1TX 0x00200000 |
| #define | GPIO_PCTL_PC5_M0PWM7 0x00400000 |
| #define | GPIO_PCTL_PC5_PHA1 0x00600000 |
| #define | GPIO_PCTL_PC5_WT0CCP1 0x00700000 |
| #define | GPIO_PCTL_PC5_U1CTS 0x00800000 |
| #define | GPIO_PCTL_PC4_M 0x000F0000 |
| #define | GPIO_PCTL_PC4_U4RX 0x00010000 |
| #define | GPIO_PCTL_PC4_U1RX 0x00020000 |
| #define | GPIO_PCTL_PC4_M0PWM6 0x00040000 |
| #define | GPIO_PCTL_PC4_IDX1 0x00060000 |
| #define | GPIO_PCTL_PC4_WT0CCP0 0x00070000 |
| #define | GPIO_PCTL_PC4_U1RTS 0x00080000 |
| #define | GPIO_PCTL_PC3_M 0x0000F000 |
| #define | GPIO_PCTL_PC3_TDO 0x00001000 |
| #define | GPIO_PCTL_PC3_T5CCP1 0x00007000 |
| #define | GPIO_PCTL_PC2_M 0x00000F00 |
| #define | GPIO_PCTL_PC2_TDI 0x00000100 |
| #define | GPIO_PCTL_PC2_T5CCP0 0x00000700 |
| #define | GPIO_PCTL_PC1_M 0x000000F0 |
| #define | GPIO_PCTL_PC1_TMS 0x00000010 |
| #define | GPIO_PCTL_PC1_T4CCP1 0x00000070 |
| #define | GPIO_PCTL_PC0_M 0x0000000F |
| #define | GPIO_PCTL_PC0_TCK 0x00000001 |
| #define | GPIO_PCTL_PC0_T4CCP0 0x00000007 |
| #define | GPIO_PCTL_PD7_M 0xF0000000 |
| #define | GPIO_PCTL_PD7_AIN4 0x00000000 |
| #define | GPIO_PCTL_PD7_U2TX 0x10000000 |
| #define | GPIO_PCTL_PD7_M0FAULT1 0x40000000 |
| #define | GPIO_PCTL_PD7_PHB0 0x60000000 |
| #define | GPIO_PCTL_PD7_WT5CCP1 0x70000000 |
| #define | GPIO_PCTL_PD7_NMI 0x80000000 |
| #define | GPIO_PCTL_PD6_M 0x0F000000 |
| #define | GPIO_PCTL_PD6_AIN5 0x00000000 |
| #define | GPIO_PCTL_PD6_U2RX 0x01000000 |
| #define | GPIO_PCTL_PD6_M0FAULT0 0x04000000 |
| #define | GPIO_PCTL_PD6_PHA0 0x06000000 |
| #define | GPIO_PCTL_PD6_WT5CCP0 0x07000000 |
| #define | GPIO_PCTL_PD5_M 0x00F00000 |
| #define | GPIO_PCTL_PD5_U6TX 0x00100000 |
| #define | GPIO_PCTL_PD5_WT4CCP1 0x00700000 |
| #define | GPIO_PCTL_PD4_M 0x000F0000 |
| #define | GPIO_PCTL_PD4_AIN7 0x00000000 |
| #define | GPIO_PCTL_PD4_U6RX 0x00010000 |
| #define | GPIO_PCTL_PD4_WT4CCP0 0x00070000 |
| #define | GPIO_PCTL_PD3_M 0x0000F000 |
| #define | GPIO_PCTL_PD3_AIN12 0x00000000 |
| #define | GPIO_PCTL_PD3_SSI3TX 0x00001000 |
| #define | GPIO_PCTL_PD3_SSI1TX 0x00002000 |
| #define | GPIO_PCTL_PD3_IDX0 0x00006000 |
| #define | GPIO_PCTL_PD3_WT3CCP1 0x00007000 |
| #define | GPIO_PCTL_PD3_USB0PFLT 0x00008000 |
| #define | GPIO_PCTL_PD2_M 0x00000F00 |
| #define | GPIO_PCTL_PD2_AIN13 0x00000000 |
| #define | GPIO_PCTL_PD2_SSI3RX 0x00000100 |
| #define | GPIO_PCTL_PD2_SSI1RX 0x00000200 |
| #define | GPIO_PCTL_PD2_M0FAULT0 0x00000400 |
| #define | GPIO_PCTL_PD2_WT3CCP0 0x00000700 |
| #define | GPIO_PCTL_PD2_USB0EPEN 0x00000800 |
| #define | GPIO_PCTL_PD1_M 0x000000F0 |
| #define | GPIO_PCTL_PD1_AIN14 0x00000000 |
| #define | GPIO_PCTL_PD1_SSI3FSS 0x00000010 |
| #define | GPIO_PCTL_PD1_SSI1FSS 0x00000020 |
| #define | GPIO_PCTL_PD1_I2C3SDA 0x00000030 |
| #define | GPIO_PCTL_PD1_M0PWM7 0x00000040 |
| #define | GPIO_PCTL_PD1_M1PWM1 0x00000050 |
| #define | GPIO_PCTL_PD1_WT2CCP1 0x00000070 |
| #define | GPIO_PCTL_PD0_M 0x0000000F |
| #define | GPIO_PCTL_PD0_AIN15 0x00000000 |
| #define | GPIO_PCTL_PD0_SSI3CLK 0x00000001 |
| #define | GPIO_PCTL_PD0_SSI1CLK 0x00000002 |
| #define | GPIO_PCTL_PD0_I2C3SCL 0x00000003 |
| #define | GPIO_PCTL_PD0_M0PWM6 0x00000004 |
| #define | GPIO_PCTL_PD0_M1PWM0 0x00000005 |
| #define | GPIO_PCTL_PD0_WT2CCP0 0x00000007 |
| #define | GPIO_PCTL_PE7_M 0xF0000000 |
| #define | GPIO_PCTL_PE7_AIN20 0x00000000 |
| #define | GPIO_PCTL_PE7_U1RI 0x10000000 |
| #define | GPIO_PCTL_PE7_CAN1TX 0x80000000 |
| #define | GPIO_PCTL_PE6_M 0x0F000000 |
| #define | GPIO_PCTL_PE6_AIN21 0x00000000 |
| #define | GPIO_PCTL_PE6_CAN1RX 0x08000000 |
| #define | GPIO_PCTL_PE5_M 0x00F00000 |
| #define | GPIO_PCTL_PE5_AIN8 0x00000000 |
| #define | GPIO_PCTL_PE5_U5TX 0x00100000 |
| #define | GPIO_PCTL_PE5_I2C2SDA 0x00300000 |
| #define | GPIO_PCTL_PE5_M0PWM5 0x00400000 |
| #define | GPIO_PCTL_PE5_M1PWM3 0x00500000 |
| #define | GPIO_PCTL_PE5_CAN0TX 0x00800000 |
| #define | GPIO_PCTL_PE4_M 0x000F0000 |
| #define | GPIO_PCTL_PE4_AIN9 0x00000000 |
| #define | GPIO_PCTL_PE4_U5RX 0x00010000 |
| #define | GPIO_PCTL_PE4_I2C2SCL 0x00030000 |
| #define | GPIO_PCTL_PE4_M0PWM4 0x00040000 |
| #define | GPIO_PCTL_PE4_M1PWM2 0x00050000 |
| #define | GPIO_PCTL_PE4_CAN0RX 0x00080000 |
| #define | GPIO_PCTL_PE3_M 0x0000F000 |
| #define | GPIO_PCTL_PE3_AIN0 0x00000000 |
| #define | GPIO_PCTL_PE2_M 0x00000F00 |
| #define | GPIO_PCTL_PE2_AIN1 0x00000000 |
| #define | GPIO_PCTL_PE1_M 0x000000F0 |
| #define | GPIO_PCTL_PE1_AIN2 0x00000000 |
| #define | GPIO_PCTL_PE1_U7TX 0x00000010 |
| #define | GPIO_PCTL_PE0_M 0x0000000F |
| #define | GPIO_PCTL_PE0_AIN3 0x00000000 |
| #define | GPIO_PCTL_PE0_U7RX 0x00000001 |
| #define | GPIO_PCTL_PF7_M 0xF0000000 |
| #define | GPIO_PCTL_PF7_I2C2SDA 0x30000000 |
| #define | GPIO_PCTL_PF7_M1FAULT0 0x50000000 |
| #define | GPIO_PCTL_PF7_T3CCP1 0x70000000 |
| #define | GPIO_PCTL_PF6_M 0x0F000000 |
| #define | GPIO_PCTL_PF6_I2C2SCL 0x03000000 |
| #define | GPIO_PCTL_PF6_T3CCP0 0x07000000 |
| #define | GPIO_PCTL_PF5_M 0x00F00000 |
| #define | GPIO_PCTL_PF5_M0FAULT3 0x00400000 |
| #define | GPIO_PCTL_PF5_T2CCP1 0x00700000 |
| #define | GPIO_PCTL_PF5_USB0PFLT 0x00800000 |
| #define | GPIO_PCTL_PF4_M 0x000F0000 |
| #define | GPIO_PCTL_PF4_U1DTR 0x00010000 |
| #define | GPIO_PCTL_PF4_M0FAULT2 0x00040000 |
| #define | GPIO_PCTL_PF4_M1FAULT0 0x00050000 |
| #define | GPIO_PCTL_PF4_IDX0 0x00060000 |
| #define | GPIO_PCTL_PF4_T2CCP0 0x00070000 |
| #define | GPIO_PCTL_PF4_USB0EPEN 0x00080000 |
| #define | GPIO_PCTL_PF4_TRD3 0x000E0000 |
| #define | GPIO_PCTL_PF3_M 0x0000F000 |
| #define | GPIO_PCTL_PF3_U1DSR 0x00001000 |
| #define | GPIO_PCTL_PF3_SSI1FSS 0x00002000 |
| #define | GPIO_PCTL_PF3_CAN0TX 0x00003000 |
| #define | GPIO_PCTL_PF3_M0FAULT1 0x00004000 |
| #define | GPIO_PCTL_PF3_M1PWM7 0x00005000 |
| #define | GPIO_PCTL_PF3_T1CCP1 0x00007000 |
| #define | GPIO_PCTL_PF3_TRCLK 0x0000E000 |
| #define | GPIO_PCTL_PF2_M 0x00000F00 |
| #define | GPIO_PCTL_PF2_U1DCD 0x00000100 |
| #define | GPIO_PCTL_PF2_SSI1CLK 0x00000200 |
| #define | GPIO_PCTL_PF2_M0FAULT0 0x00000400 |
| #define | GPIO_PCTL_PF2_M1PWM6 0x00000500 |
| #define | GPIO_PCTL_PF2_T1CCP0 0x00000700 |
| #define | GPIO_PCTL_PF2_C2O 0x00000900 |
| #define | GPIO_PCTL_PF2_TRD0 0x00000E00 |
| #define | GPIO_PCTL_PF1_M 0x000000F0 |
| #define | GPIO_PCTL_PF1_U1CTS 0x00000010 |
| #define | GPIO_PCTL_PF1_SSI1TX 0x00000020 |
| #define | GPIO_PCTL_PF1_M1PWM5 0x00000050 |
| #define | GPIO_PCTL_PF1_PHB0 0x00000060 |
| #define | GPIO_PCTL_PF1_T0CCP1 0x00000070 |
| #define | GPIO_PCTL_PF1_C1O 0x00000090 |
| #define | GPIO_PCTL_PF1_TRD1 0x000000E0 |
| #define | GPIO_PCTL_PF0_M 0x0000000F |
| #define | GPIO_PCTL_PF0_U1RTS 0x00000001 |
| #define | GPIO_PCTL_PF0_SSI1RX 0x00000002 |
| #define | GPIO_PCTL_PF0_CAN0RX 0x00000003 |
| #define | GPIO_PCTL_PF0_M1PWM4 0x00000005 |
| #define | GPIO_PCTL_PF0_PHA0 0x00000006 |
| #define | GPIO_PCTL_PF0_T0CCP0 0x00000007 |
| #define | GPIO_PCTL_PF0_NMI 0x00000008 |
| #define | GPIO_PCTL_PF0_C0O 0x00000009 |
| #define | GPIO_PCTL_PF0_TRD2 0x0000000E |
| #define | GPIO_PCTL_PG7_M 0xF0000000 |
| #define | GPIO_PCTL_PG7_I2C5SDA 0x30000000 |
| #define | GPIO_PCTL_PG7_M0PWM7 0x40000000 |
| #define | GPIO_PCTL_PG7_IDX1 0x50000000 |
| #define | GPIO_PCTL_PG7_WT1CCP1 0x70000000 |
| #define | GPIO_PCTL_PG6_M 0x0F000000 |
| #define | GPIO_PCTL_PG6_I2C5SCL 0x03000000 |
| #define | GPIO_PCTL_PG6_M0PWM6 0x04000000 |
| #define | GPIO_PCTL_PG6_WT1CCP0 0x07000000 |
| #define | GPIO_PCTL_PG5_M 0x00F00000 |
| #define | GPIO_PCTL_PG5_U2TX 0x00100000 |
| #define | GPIO_PCTL_PG5_I2C1SDA 0x00300000 |
| #define | GPIO_PCTL_PG5_M0PWM5 0x00400000 |
| #define | GPIO_PCTL_PG5_M1PWM3 0x00500000 |
| #define | GPIO_PCTL_PG5_IDX1 0x00600000 |
| #define | GPIO_PCTL_PG5_WT0CCP1 0x00700000 |
| #define | GPIO_PCTL_PG5_USB0PFLT 0x00800000 |
| #define | GPIO_PCTL_PG4_M 0x000F0000 |
| #define | GPIO_PCTL_PG4_U2RX 0x00010000 |
| #define | GPIO_PCTL_PG4_I2C1SCL 0x00030000 |
| #define | GPIO_PCTL_PG4_M0PWM4 0x00040000 |
| #define | GPIO_PCTL_PG4_M1PWM2 0x00050000 |
| #define | GPIO_PCTL_PG4_PHB1 0x00060000 |
| #define | GPIO_PCTL_PG4_WT0CCP0 0x00070000 |
| #define | GPIO_PCTL_PG4_USB0EPEN 0x00080000 |
| #define | GPIO_PCTL_PG3_M 0x0000F000 |
| #define | GPIO_PCTL_PG3_I2C4SDA 0x00003000 |
| #define | GPIO_PCTL_PG3_M0FAULT2 0x00004000 |
| #define | GPIO_PCTL_PG3_M1PWM1 0x00005000 |
| #define | GPIO_PCTL_PG3_PHA1 0x00006000 |
| #define | GPIO_PCTL_PG3_T5CCP1 0x00007000 |
| #define | GPIO_PCTL_PG2_M 0x00000F00 |
| #define | GPIO_PCTL_PG2_I2C4SCL 0x00000300 |
| #define | GPIO_PCTL_PG2_M0FAULT1 0x00000400 |
| #define | GPIO_PCTL_PG2_M1PWM0 0x00000500 |
| #define | GPIO_PCTL_PG2_T5CCP0 0x00000700 |
| #define | GPIO_PCTL_PG1_M 0x000000F0 |
| #define | GPIO_PCTL_PG1_I2C3SDA 0x00000030 |
| #define | GPIO_PCTL_PG1_M1FAULT2 0x00000050 |
| #define | GPIO_PCTL_PG1_PHB1 0x00000060 |
| #define | GPIO_PCTL_PG1_T4CCP1 0x00000070 |
| #define | GPIO_PCTL_PG0_M 0x0000000F |
| #define | GPIO_PCTL_PG0_I2C3SCL 0x00000003 |
| #define | GPIO_PCTL_PG0_M1FAULT1 0x00000005 |
| #define | GPIO_PCTL_PG0_PHA1 0x00000006 |
| #define | GPIO_PCTL_PG0_T4CCP0 0x00000007 |
| #define | GPIO_PCTL_PH7_M 0xF0000000 |
| #define | GPIO_PCTL_PH7_SSI2TX 0x20000000 |
| #define | GPIO_PCTL_PH7_M0PWM7 0x40000000 |
| #define | GPIO_PCTL_PH7_WT4CCP1 0x70000000 |
| #define | GPIO_PCTL_PH6_M 0x0F000000 |
| #define | GPIO_PCTL_PH6_SSI2RX 0x02000000 |
| #define | GPIO_PCTL_PH6_M0PWM6 0x04000000 |
| #define | GPIO_PCTL_PH6_WT4CCP0 0x07000000 |
| #define | GPIO_PCTL_PH5_M 0x00F00000 |
| #define | GPIO_PCTL_PH5_SSI2FSS 0x00200000 |
| #define | GPIO_PCTL_PH5_M0PWM5 0x00400000 |
| #define | GPIO_PCTL_PH5_PHB0 0x00500000 |
| #define | GPIO_PCTL_PH5_WT3CCP1 0x00700000 |
| #define | GPIO_PCTL_PH4_M 0x000F0000 |
| #define | GPIO_PCTL_PH4_SSI2CLK 0x00020000 |
| #define | GPIO_PCTL_PH4_M0PWM4 0x00040000 |
| #define | GPIO_PCTL_PH4_PHA0 0x00050000 |
| #define | GPIO_PCTL_PH4_WT3CCP0 0x00070000 |
| #define | GPIO_PCTL_PH3_M 0x0000F000 |
| #define | GPIO_PCTL_PH3_SSI3TX 0x00002000 |
| #define | GPIO_PCTL_PH3_M0PWM3 0x00004000 |
| #define | GPIO_PCTL_PH3_M0FAULT3 0x00006000 |
| #define | GPIO_PCTL_PH3_WT5CCP1 0x00007000 |
| #define | GPIO_PCTL_PH2_M 0x00000F00 |
| #define | GPIO_PCTL_PH2_SSI3RX 0x00000200 |
| #define | GPIO_PCTL_PH2_M0PWM2 0x00000400 |
| #define | GPIO_PCTL_PH2_M0FAULT2 0x00000600 |
| #define | GPIO_PCTL_PH2_WT5CCP0 0x00000700 |
| #define | GPIO_PCTL_PH1_M 0x000000F0 |
| #define | GPIO_PCTL_PH1_SSI3FSS 0x00000020 |
| #define | GPIO_PCTL_PH1_M0PWM1 0x00000040 |
| #define | GPIO_PCTL_PH1_IDX0 0x00000050 |
| #define | GPIO_PCTL_PH1_M0FAULT1 0x00000060 |
| #define | GPIO_PCTL_PH1_WT2CCP1 0x00000070 |
| #define | GPIO_PCTL_PH0_M 0x0000000F |
| #define | GPIO_PCTL_PH0_SSI3CLK 0x00000002 |
| #define | GPIO_PCTL_PH0_M0PWM0 0x00000004 |
| #define | GPIO_PCTL_PH0_M0FAULT0 0x00000006 |
| #define | GPIO_PCTL_PH0_WT2CCP0 0x00000007 |
| #define | GPIO_PCTL_PJ7_M 0xF0000000 |
| #define | GPIO_PCTL_PJ6_M 0x0F000000 |
| #define | GPIO_PCTL_PJ5_M 0x00F00000 |
| #define | GPIO_PCTL_PJ5_C2M 0x00000000 |
| #define | GPIO_PCTL_PJ5_U6TX 0x00100000 |
| #define | GPIO_PCTL_PJ5_T3CCP1 0x00700000 |
| #define | GPIO_PCTL_PJ4_M 0x000F0000 |
| #define | GPIO_PCTL_PJ4_C2P 0x00000000 |
| #define | GPIO_PCTL_PJ4_U6RX 0x00010000 |
| #define | GPIO_PCTL_PJ4_T3CCP0 0x00070000 |
| #define | GPIO_PCTL_PJ3_M 0x0000F000 |
| #define | GPIO_PCTL_PJ3_U5TX 0x00001000 |
| #define | GPIO_PCTL_PJ3_T2CCP1 0x00007000 |
| #define | GPIO_PCTL_PJ2_M 0x00000F00 |
| #define | GPIO_PCTL_PJ2_U5RX 0x00000100 |
| #define | GPIO_PCTL_PJ2_IDX0 0x00000500 |
| #define | GPIO_PCTL_PJ2_T2CCP0 0x00000700 |
| #define | GPIO_PCTL_PJ1_M 0x000000F0 |
| #define | GPIO_PCTL_PJ1_U4TX 0x00000010 |
| #define | GPIO_PCTL_PJ1_T1CCP1 0x00000070 |
| #define | GPIO_PCTL_PJ0_M 0x0000000F |
| #define | GPIO_PCTL_PJ0_U4RX 0x00000001 |
| #define | GPIO_PCTL_PJ0_T1CCP0 0x00000007 |
| #define | GPIO_PCTL_PK7_M 0xF0000000 |
| #define | GPIO_PCTL_PK7_M0FAULT3 0x60000000 |
| #define | GPIO_PCTL_PK7_WT1CCP1 0x70000000 |
| #define | GPIO_PCTL_PK6_M 0x0F000000 |
| #define | GPIO_PCTL_PK6_M0FAULT2 0x06000000 |
| #define | GPIO_PCTL_PK6_WT1CCP0 0x07000000 |
| #define | GPIO_PCTL_PK6_C2O 0x08000000 |
| #define | GPIO_PCTL_PK5_M 0x00F00000 |
| #define | GPIO_PCTL_PK5_U7TX 0x00100000 |
| #define | GPIO_PCTL_PK5_M0FAULT1 0x00600000 |
| #define | GPIO_PCTL_PK5_C1O 0x00800000 |
| #define | GPIO_PCTL_PK4_M 0x000F0000 |
| #define | GPIO_PCTL_PK4_U7RX 0x00010000 |
| #define | GPIO_PCTL_PK4_M0FAULT0 0x00060000 |
| #define | GPIO_PCTL_PK4_RTCCLK 0x00070000 |
| #define | GPIO_PCTL_PK4_C0O 0x00080000 |
| #define | GPIO_PCTL_PK3_M 0x0000F000 |
| #define | GPIO_PCTL_PK3_AIN19 0x00000000 |
| #define | GPIO_PCTL_PK3_SSI3TX 0x00002000 |
| #define | GPIO_PCTL_PK3_M1FAULT3 0x00006000 |
| #define | GPIO_PCTL_PK2_M 0x00000F00 |
| #define | GPIO_PCTL_PK2_AIN18 0x00000000 |
| #define | GPIO_PCTL_PK2_SSI3RX 0x00000200 |
| #define | GPIO_PCTL_PK2_M1FAULT2 0x00000600 |
| #define | GPIO_PCTL_PK1_M 0x000000F0 |
| #define | GPIO_PCTL_PK1_AIN17 0x00000000 |
| #define | GPIO_PCTL_PK1_SSI3FSS 0x00000020 |
| #define | GPIO_PCTL_PK1_M1FAULT1 0x00000060 |
| #define | GPIO_PCTL_PK0_M 0x0000000F |
| #define | GPIO_PCTL_PK0_AIN16 0x00000000 |
| #define | GPIO_PCTL_PK0_SSI3CLK 0x00000002 |
| #define | GPIO_PCTL_PK0_M1FAULT0 0x00000006 |
| #define | GPIO_PCTL_PL7_M 0xF0000000 |
| #define | GPIO_PCTL_PL7_USB0DM 0x00000000 |
| #define | GPIO_PCTL_PL7_T3CCP1 0x70000000 |
| #define | GPIO_PCTL_PL7_WT3CCP1 0x80000000 |
| #define | GPIO_PCTL_PL6_M 0x0F000000 |
| #define | GPIO_PCTL_PL6_USB0DP 0x00000000 |
| #define | GPIO_PCTL_PL6_T3CCP0 0x07000000 |
| #define | GPIO_PCTL_PL6_WT3CCP0 0x08000000 |
| #define | GPIO_PCTL_PL5_M 0x00F00000 |
| #define | GPIO_PCTL_PL5_T2CCP1 0x00700000 |
| #define | GPIO_PCTL_PL5_WT2CCP1 0x00800000 |
| #define | GPIO_PCTL_PL4_M 0x000F0000 |
| #define | GPIO_PCTL_PL4_T2CCP0 0x00070000 |
| #define | GPIO_PCTL_PL4_WT2CCP0 0x00080000 |
| #define | GPIO_PCTL_PL3_M 0x0000F000 |
| #define | GPIO_PCTL_PL3_T1CCP1 0x00007000 |
| #define | GPIO_PCTL_PL3_WT1CCP1 0x00008000 |
| #define | GPIO_PCTL_PL2_M 0x00000F00 |
| #define | GPIO_PCTL_PL2_T1CCP0 0x00000700 |
| #define | GPIO_PCTL_PL2_WT1CCP0 0x00000800 |
| #define | GPIO_PCTL_PL1_M 0x000000F0 |
| #define | GPIO_PCTL_PL1_T0CCP1 0x00000070 |
| #define | GPIO_PCTL_PL1_WT0CCP1 0x00000080 |
| #define | GPIO_PCTL_PL0_M 0x0000000F |
| #define | GPIO_PCTL_PL0_T0CCP0 0x00000007 |
| #define | GPIO_PCTL_PL0_WT0CCP0 0x00000008 |
| #define | GPIO_PCTL_PM7_M 0xF0000000 |
| #define | GPIO_PCTL_PM7_M0PWM5 0x20000000 |
| #define | GPIO_PCTL_PM7_WT0CCP1 0x70000000 |
| #define | GPIO_PCTL_PM6_M 0x0F000000 |
| #define | GPIO_PCTL_PM6_M0PWM4 0x02000000 |
| #define | GPIO_PCTL_PM6_WT0CCP0 0x07000000 |
| #define | GPIO_PCTL_PM5_M 0x00F00000 |
| #define | GPIO_PCTL_PM4_M 0x000F0000 |
| #define | GPIO_PCTL_PM3_M 0x0000F000 |
| #define | GPIO_PCTL_PM3_T5CCP1 0x00007000 |
| #define | GPIO_PCTL_PM3_WT5CCP1 0x00008000 |
| #define | GPIO_PCTL_PM2_M 0x00000F00 |
| #define | GPIO_PCTL_PM2_T5CCP0 0x00000700 |
| #define | GPIO_PCTL_PM2_WT5CCP0 0x00000800 |
| #define | GPIO_PCTL_PM1_M 0x000000F0 |
| #define | GPIO_PCTL_PM1_T4CCP1 0x00000070 |
| #define | GPIO_PCTL_PM1_WT4CCP1 0x00000080 |
| #define | GPIO_PCTL_PM0_M 0x0000000F |
| #define | GPIO_PCTL_PM0_T4CCP0 0x00000007 |
| #define | GPIO_PCTL_PM0_WT4CCP0 0x00000008 |
| #define | GPIO_PCTL_PN7_M 0xF0000000 |
| #define | GPIO_PCTL_PN7_M1PWM7 0x20000000 |
| #define | GPIO_PCTL_PN7_WT4CCP1 0x70000000 |
| #define | GPIO_PCTL_PN6_M 0x0F000000 |
| #define | GPIO_PCTL_PN6_M1PWM6 0x02000000 |
| #define | GPIO_PCTL_PN6_WT4CCP0 0x07000000 |
| #define | GPIO_PCTL_PN5_M 0x00F00000 |
| #define | GPIO_PCTL_PN5_M1PWM5 0x00200000 |
| #define | GPIO_PCTL_PN5_WT3CCP1 0x00700000 |
| #define | GPIO_PCTL_PN4_M 0x000F0000 |
| #define | GPIO_PCTL_PN4_M1PWM4 0x00020000 |
| #define | GPIO_PCTL_PN4_WT3CCP0 0x00070000 |
| #define | GPIO_PCTL_PN3_M 0x0000F000 |
| #define | GPIO_PCTL_PN3_M0PWM7 0x00002000 |
| #define | GPIO_PCTL_PN3_WT2CCP1 0x00007000 |
| #define | GPIO_PCTL_PN2_M 0x00000F00 |
| #define | GPIO_PCTL_PN2_M0PWM6 0x00000200 |
| #define | GPIO_PCTL_PN2_WT2CCP0 0x00000700 |
| #define | GPIO_PCTL_PN1_M 0x000000F0 |
| #define | GPIO_PCTL_PN1_CAN0TX 0x00000010 |
| #define | GPIO_PCTL_PN0_M 0x0000000F |
| #define | GPIO_PCTL_PN0_CAN0RX 0x00000001 |
| #define | GPIO_PCTL_PP2_M 0x00000F00 |
| #define | GPIO_PCTL_PP2_M0PWM2 0x00000100 |
| #define | GPIO_PCTL_PP2_T5CCP0 0x00000700 |
| #define | GPIO_PCTL_PP1_M 0x000000F0 |
| #define | GPIO_PCTL_PP1_AIN22 0x00000000 |
| #define | GPIO_PCTL_PP1_M0PWM1 0x00000010 |
| #define | GPIO_PCTL_PP1_T4CCP1 0x00000070 |
| #define | GPIO_PCTL_PP0_M 0x0000000F |
| #define | GPIO_PCTL_PP0_AIN23 0x00000000 |
| #define | GPIO_PCTL_PP0_M0PWM0 0x00000001 |
| #define | GPIO_PCTL_PP0_T4CCP0 0x00000007 |
| #define | SSI_CR0_SCR_M 0x0000FF00 |
| #define | SSI_CR0_SPH 0x00000080 |
| #define | SSI_CR0_SPO 0x00000040 |
| #define | SSI_CR0_FRF_M 0x00000030 |
| #define | SSI_CR0_FRF_MOTO 0x00000000 |
| #define | SSI_CR0_FRF_TI 0x00000010 |
| #define | SSI_CR0_FRF_NMW 0x00000020 |
| #define | SSI_CR0_DSS_M 0x0000000F |
| #define | SSI_CR0_DSS_4 0x00000003 |
| #define | SSI_CR0_DSS_5 0x00000004 |
| #define | SSI_CR0_DSS_6 0x00000005 |
| #define | SSI_CR0_DSS_7 0x00000006 |
| #define | SSI_CR0_DSS_8 0x00000007 |
| #define | SSI_CR0_DSS_9 0x00000008 |
| #define | SSI_CR0_DSS_10 0x00000009 |
| #define | SSI_CR0_DSS_11 0x0000000A |
| #define | SSI_CR0_DSS_12 0x0000000B |
| #define | SSI_CR0_DSS_13 0x0000000C |
| #define | SSI_CR0_DSS_14 0x0000000D |
| #define | SSI_CR0_DSS_15 0x0000000E |
| #define | SSI_CR0_DSS_16 0x0000000F |
| #define | SSI_CR0_SCR_S 8 |
| #define | SSI_CR1_EOT 0x00000010 |
| #define | SSI_CR1_MS 0x00000004 |
| #define | SSI_CR1_SSE 0x00000002 |
| #define | SSI_CR1_LBM 0x00000001 |
| #define | SSI_DR_DATA_M 0x0000FFFF |
| #define | SSI_DR_DATA_S 0 |
| #define | SSI_SR_BSY 0x00000010 |
| #define | SSI_SR_RFF 0x00000008 |
| #define | SSI_SR_RNE 0x00000004 |
| #define | SSI_SR_TNF 0x00000002 |
| #define | SSI_SR_TFE 0x00000001 |
| #define | SSI_CPSR_CPSDVSR_M 0x000000FF |
| #define | SSI_CPSR_CPSDVSR_S 0 |
| #define | SSI_IM_TXIM 0x00000008 |
| #define | SSI_IM_RXIM 0x00000004 |
| #define | SSI_IM_RTIM 0x00000002 |
| #define | SSI_IM_RORIM 0x00000001 |
| #define | SSI_RIS_TXRIS 0x00000008 |
| #define | SSI_RIS_RXRIS 0x00000004 |
| #define | SSI_RIS_RTRIS 0x00000002 |
| #define | SSI_RIS_RORRIS 0x00000001 |
| #define | SSI_MIS_TXMIS 0x00000008 |
| #define | SSI_MIS_RXMIS 0x00000004 |
| #define | SSI_MIS_RTMIS 0x00000002 |
| #define | SSI_MIS_RORMIS 0x00000001 |
| #define | SSI_ICR_RTIC 0x00000002 |
| #define | SSI_ICR_RORIC 0x00000001 |
| #define | SSI_DMACTL_TXDMAE 0x00000002 |
| #define | SSI_DMACTL_RXDMAE 0x00000001 |
| #define | SSI_CC_CS_M 0x0000000F |
| #define | SSI_CC_CS_SYSPLL 0x00000000 |
| #define | SSI_CC_CS_PIOSC 0x00000005 |
| #define | UART_DR_OE 0x00000800 |
| #define | UART_DR_BE 0x00000400 |
| #define | UART_DR_PE 0x00000200 |
| #define | UART_DR_FE 0x00000100 |
| #define | UART_DR_DATA_M 0x000000FF |
| #define | UART_DR_DATA_S 0 |
| #define | UART_RSR_OE 0x00000008 |
| #define | UART_RSR_BE 0x00000004 |
| #define | UART_RSR_PE 0x00000002 |
| #define | UART_RSR_FE 0x00000001 |
| #define | UART_ECR_DATA_M 0x000000FF |
| #define | UART_ECR_DATA_S 0 |
| #define | UART_FR_RI 0x00000100 |
| #define | UART_FR_TXFE 0x00000080 |
| #define | UART_FR_RXFF 0x00000040 |
| #define | UART_FR_TXFF 0x00000020 |
| #define | UART_FR_RXFE 0x00000010 |
| #define | UART_FR_BUSY 0x00000008 |
| #define | UART_FR_DCD 0x00000004 |
| #define | UART_FR_DSR 0x00000002 |
| #define | UART_FR_CTS 0x00000001 |
| #define | UART_ILPR_ILPDVSR_M 0x000000FF |
| #define | UART_ILPR_ILPDVSR_S 0 |
| #define | UART_IBRD_DIVINT_M 0x0000FFFF |
| #define | UART_IBRD_DIVINT_S 0 |
| #define | UART_FBRD_DIVFRAC_M 0x0000003F |
| #define | UART_FBRD_DIVFRAC_S 0 |
| #define | UART_LCRH_SPS 0x00000080 |
| #define | UART_LCRH_WLEN_M 0x00000060 |
| #define | UART_LCRH_WLEN_5 0x00000000 |
| #define | UART_LCRH_WLEN_6 0x00000020 |
| #define | UART_LCRH_WLEN_7 0x00000040 |
| #define | UART_LCRH_WLEN_8 0x00000060 |
| #define | UART_LCRH_FEN 0x00000010 |
| #define | UART_LCRH_STP2 0x00000008 |
| #define | UART_LCRH_EPS 0x00000004 |
| #define | UART_LCRH_PEN 0x00000002 |
| #define | UART_LCRH_BRK 0x00000001 |
| #define | UART_CTL_CTSEN 0x00008000 |
| #define | UART_CTL_RTSEN 0x00004000 |
| #define | UART_CTL_RTS 0x00000800 |
| #define | UART_CTL_DTR 0x00000400 |
| #define | UART_CTL_RXE 0x00000200 |
| #define | UART_CTL_TXE 0x00000100 |
| #define | UART_CTL_LBE 0x00000080 |
| #define | UART_CTL_HSE 0x00000020 |
| #define | UART_CTL_EOT 0x00000010 |
| #define | UART_CTL_SMART 0x00000008 |
| #define | UART_CTL_SIRLP 0x00000004 |
| #define | UART_CTL_SIREN 0x00000002 |
| #define | UART_CTL_UARTEN 0x00000001 |
| #define | UART_IFLS_RX_M 0x00000038 |
| #define | UART_IFLS_RX1_8 0x00000000 |
| #define | UART_IFLS_RX2_8 0x00000008 |
| #define | UART_IFLS_RX4_8 0x00000010 |
| #define | UART_IFLS_RX6_8 0x00000018 |
| #define | UART_IFLS_RX7_8 0x00000020 |
| #define | UART_IFLS_TX_M 0x00000007 |
| #define | UART_IFLS_TX1_8 0x00000000 |
| #define | UART_IFLS_TX2_8 0x00000001 |
| #define | UART_IFLS_TX4_8 0x00000002 |
| #define | UART_IFLS_TX6_8 0x00000003 |
| #define | UART_IFLS_TX7_8 0x00000004 |
| #define | UART_IM_9BITIM 0x00001000 |
| #define | UART_IM_OEIM 0x00000400 |
| #define | UART_IM_BEIM 0x00000200 |
| #define | UART_IM_PEIM 0x00000100 |
| #define | UART_IM_FEIM 0x00000080 |
| #define | UART_IM_RTIM 0x00000040 |
| #define | UART_IM_TXIM 0x00000020 |
| #define | UART_IM_RXIM 0x00000010 |
| #define | UART_IM_DSRMIM 0x00000008 |
| #define | UART_IM_DCDMIM 0x00000004 |
| #define | UART_IM_CTSMIM 0x00000002 |
| #define | UART_IM_RIMIM 0x00000001 |
| #define | UART_RIS_9BITRIS 0x00001000 |
| #define | UART_RIS_OERIS 0x00000400 |
| #define | UART_RIS_BERIS 0x00000200 |
| #define | UART_RIS_PERIS 0x00000100 |
| #define | UART_RIS_FERIS 0x00000080 |
| #define | UART_RIS_RTRIS 0x00000040 |
| #define | UART_RIS_TXRIS 0x00000020 |
| #define | UART_RIS_RXRIS 0x00000010 |
| #define | UART_RIS_DSRRIS 0x00000008 |
| #define | UART_RIS_DCDRIS 0x00000004 |
| #define | UART_RIS_CTSRIS 0x00000002 |
| #define | UART_RIS_RIRIS 0x00000001 |
| #define | UART_MIS_9BITMIS 0x00001000 |
| #define | UART_MIS_OEMIS 0x00000400 |
| #define | UART_MIS_BEMIS 0x00000200 |
| #define | UART_MIS_PEMIS 0x00000100 |
| #define | UART_MIS_FEMIS 0x00000080 |
| #define | UART_MIS_RTMIS 0x00000040 |
| #define | UART_MIS_TXMIS 0x00000020 |
| #define | UART_MIS_RXMIS 0x00000010 |
| #define | UART_MIS_DSRMIS 0x00000008 |
| #define | UART_MIS_DCDMIS 0x00000004 |
| #define | UART_MIS_CTSMIS 0x00000002 |
| #define | UART_MIS_RIMIS 0x00000001 |
| #define | UART_ICR_9BITIC 0x00001000 |
| #define | UART_ICR_OEIC 0x00000400 |
| #define | UART_ICR_BEIC 0x00000200 |
| #define | UART_ICR_PEIC 0x00000100 |
| #define | UART_ICR_FEIC 0x00000080 |
| #define | UART_ICR_RTIC 0x00000040 |
| #define | UART_ICR_TXIC 0x00000020 |
| #define | UART_ICR_RXIC 0x00000010 |
| #define | UART_ICR_DSRMIC 0x00000008 |
| #define | UART_ICR_DCDMIC 0x00000004 |
| #define | UART_ICR_CTSMIC 0x00000002 |
| #define | UART_ICR_RIMIC 0x00000001 |
| #define | UART_DMACTL_DMAERR 0x00000004 |
| #define | UART_DMACTL_TXDMAE 0x00000002 |
| #define | UART_DMACTL_RXDMAE 0x00000001 |
| #define | UART_9BITADDR_9BITEN 0x00008000 |
| #define | UART_9BITADDR_ADDR_M 0x000000FF |
| #define | UART_9BITADDR_ADDR_S 0 |
| #define | UART_9BITAMASK_MASK_M 0x000000FF |
| #define | UART_9BITAMASK_MASK_S 0 |
| #define | UART_PP_NB 0x00000002 |
| #define | UART_PP_SC 0x00000001 |
| #define | UART_CC_CS_M 0x0000000F |
| #define | UART_CC_CS_SYSCLK 0x00000000 |
| #define | UART_CC_CS_PIOSC 0x00000005 |
| #define | I2C_MSA_SA_M 0x000000FE |
| #define | I2C_MSA_RS 0x00000001 |
| #define | I2C_MSA_SA_S 1 |
| #define | I2C_MCS_CLKTO 0x00000080 |
| #define | I2C_MCS_BUSBSY 0x00000040 |
| #define | I2C_MCS_IDLE 0x00000020 |
| #define | I2C_MCS_ARBLST 0x00000010 |
| #define | I2C_MCS_HS 0x00000010 |
| #define | I2C_MCS_ACK 0x00000008 |
| #define | I2C_MCS_DATACK 0x00000008 |
| #define | I2C_MCS_ADRACK 0x00000004 |
| #define | I2C_MCS_STOP 0x00000004 |
| #define | I2C_MCS_ERROR 0x00000002 |
| #define | I2C_MCS_START 0x00000002 |
| #define | I2C_MCS_RUN 0x00000001 |
| #define | I2C_MCS_BUSY 0x00000001 |
| #define | I2C_MDR_DATA_M 0x000000FF |
| #define | I2C_MDR_DATA_S 0 |
| #define | I2C_MTPR_HS 0x00000080 |
| #define | I2C_MTPR_TPR_M 0x0000007F |
| #define | I2C_MTPR_TPR_S 0 |
| #define | I2C_MIMR_CLKIM 0x00000002 |
| #define | I2C_MIMR_IM 0x00000001 |
| #define | I2C_MRIS_CLKRIS 0x00000002 |
| #define | I2C_MRIS_RIS 0x00000001 |
| #define | I2C_MMIS_CLKMIS 0x00000002 |
| #define | I2C_MMIS_MIS 0x00000001 |
| #define | I2C_MICR_CLKIC 0x00000002 |
| #define | I2C_MICR_IC 0x00000001 |
| #define | I2C_MCR_GFE 0x00000040 |
| #define | I2C_MCR_SFE 0x00000020 |
| #define | I2C_MCR_MFE 0x00000010 |
| #define | I2C_MCR_LPBK 0x00000001 |
| #define | I2C_MCLKOCNT_CNTL_M 0x000000FF |
| #define | I2C_MCLKOCNT_CNTL_S 0 |
| #define | I2C_MBMON_SDA 0x00000002 |
| #define | I2C_MBMON_SCL 0x00000001 |
| #define | I2C_MCR2_GFPW_M 0x00000070 |
| #define | I2C_MCR2_GFPW_BYPASS 0x00000000 |
| #define | I2C_MCR2_GFPW_1 0x00000010 |
| #define | I2C_MCR2_GFPW_2 0x00000020 |
| #define | I2C_MCR2_GFPW_3 0x00000030 |
| #define | I2C_MCR2_GFPW_4 0x00000040 |
| #define | I2C_MCR2_GFPW_8 0x00000050 |
| #define | I2C_MCR2_GFPW_16 0x00000060 |
| #define | I2C_MCR2_GFPW_31 0x00000070 |
| #define | I2C_SOAR_OAR_M 0x0000007F |
| #define | I2C_SOAR_OAR_S 0 |
| #define | I2C_SCSR_OAR2SEL 0x00000008 |
| #define | I2C_SCSR_FBR 0x00000004 |
| #define | I2C_SCSR_TREQ 0x00000002 |
| #define | I2C_SCSR_DA 0x00000001 |
| #define | I2C_SCSR_RREQ 0x00000001 |
| #define | I2C_SDR_DATA_M 0x000000FF |
| #define | I2C_SDR_DATA_S 0 |
| #define | I2C_SIMR_STOPIM 0x00000004 |
| #define | I2C_SIMR_STARTIM 0x00000002 |
| #define | I2C_SIMR_DATAIM 0x00000001 |
| #define | I2C_SRIS_STOPRIS 0x00000004 |
| #define | I2C_SRIS_STARTRIS 0x00000002 |
| #define | I2C_SRIS_DATARIS 0x00000001 |
| #define | I2C_SMIS_STOPMIS 0x00000004 |
| #define | I2C_SMIS_STARTMIS 0x00000002 |
| #define | I2C_SMIS_DATAMIS 0x00000001 |
| #define | I2C_SICR_STOPIC 0x00000004 |
| #define | I2C_SICR_STARTIC 0x00000002 |
| #define | I2C_SICR_DATAIC 0x00000001 |
| #define | I2C_SOAR2_OAR2EN 0x00000080 |
| #define | I2C_SOAR2_OAR2_M 0x0000007F |
| #define | I2C_SOAR2_OAR2_S 0 |
| #define | I2C_SACKCTL_ACKOVAL 0x00000002 |
| #define | I2C_SACKCTL_ACKOEN 0x00000001 |
| #define | I2C_PP_HS 0x00000001 |
| #define | I2C_PC_HS 0x00000001 |
| #define | PWM_CTL_GLOBALSYNC3 0x00000008 |
| #define | PWM_CTL_GLOBALSYNC2 0x00000004 |
| #define | PWM_CTL_GLOBALSYNC1 0x00000002 |
| #define | PWM_CTL_GLOBALSYNC0 0x00000001 |
| #define | PWM_SYNC_SYNC3 0x00000008 |
| #define | PWM_SYNC_SYNC2 0x00000004 |
| #define | PWM_SYNC_SYNC1 0x00000002 |
| #define | PWM_SYNC_SYNC0 0x00000001 |
| #define | PWM_ENABLE_PWM7EN 0x00000080 |
| #define | PWM_ENABLE_PWM6EN 0x00000040 |
| #define | PWM_ENABLE_PWM5EN 0x00000020 |
| #define | PWM_ENABLE_PWM4EN 0x00000010 |
| #define | PWM_ENABLE_PWM3EN 0x00000008 |
| #define | PWM_ENABLE_PWM2EN 0x00000004 |
| #define | PWM_ENABLE_PWM1EN 0x00000002 |
| #define | PWM_ENABLE_PWM0EN 0x00000001 |
| #define | PWM_INVERT_PWM7INV 0x00000080 |
| #define | PWM_INVERT_PWM6INV 0x00000040 |
| #define | PWM_INVERT_PWM5INV 0x00000020 |
| #define | PWM_INVERT_PWM4INV 0x00000010 |
| #define | PWM_INVERT_PWM3INV 0x00000008 |
| #define | PWM_INVERT_PWM2INV 0x00000004 |
| #define | PWM_INVERT_PWM1INV 0x00000002 |
| #define | PWM_INVERT_PWM0INV 0x00000001 |
| #define | PWM_FAULT_FAULT7 0x00000080 |
| #define | PWM_FAULT_FAULT6 0x00000040 |
| #define | PWM_FAULT_FAULT5 0x00000020 |
| #define | PWM_FAULT_FAULT4 0x00000010 |
| #define | PWM_FAULT_FAULT3 0x00000008 |
| #define | PWM_FAULT_FAULT2 0x00000004 |
| #define | PWM_FAULT_FAULT1 0x00000002 |
| #define | PWM_FAULT_FAULT0 0x00000001 |
| #define | PWM_INTEN_INTFAULT3 0x00080000 |
| #define | PWM_INTEN_INTFAULT2 0x00040000 |
| #define | PWM_INTEN_INTFAULT1 0x00020000 |
| #define | PWM_INTEN_INTFAULT0 0x00010000 |
| #define | PWM_INTEN_INTPWM3 0x00000008 |
| #define | PWM_INTEN_INTPWM2 0x00000004 |
| #define | PWM_INTEN_INTPWM1 0x00000002 |
| #define | PWM_INTEN_INTPWM0 0x00000001 |
| #define | PWM_RIS_INTFAULT3 0x00080000 |
| #define | PWM_RIS_INTFAULT2 0x00040000 |
| #define | PWM_RIS_INTFAULT1 0x00020000 |
| #define | PWM_RIS_INTFAULT0 0x00010000 |
| #define | PWM_RIS_INTPWM3 0x00000008 |
| #define | PWM_RIS_INTPWM2 0x00000004 |
| #define | PWM_RIS_INTPWM1 0x00000002 |
| #define | PWM_RIS_INTPWM0 0x00000001 |
| #define | PWM_ISC_INTFAULT3 0x00080000 |
| #define | PWM_ISC_INTFAULT2 0x00040000 |
| #define | PWM_ISC_INTFAULT1 0x00020000 |
| #define | PWM_ISC_INTFAULT0 0x00010000 |
| #define | PWM_ISC_INTPWM3 0x00000008 |
| #define | PWM_ISC_INTPWM2 0x00000004 |
| #define | PWM_ISC_INTPWM1 0x00000002 |
| #define | PWM_ISC_INTPWM0 0x00000001 |
| #define | PWM_STATUS_FAULT3 0x00000008 |
| #define | PWM_STATUS_FAULT2 0x00000004 |
| #define | PWM_STATUS_FAULT1 0x00000002 |
| #define | PWM_STATUS_FAULT0 0x00000001 |
| #define | PWM_FAULTVAL_PWM7 0x00000080 |
| #define | PWM_FAULTVAL_PWM6 0x00000040 |
| #define | PWM_FAULTVAL_PWM5 0x00000020 |
| #define | PWM_FAULTVAL_PWM4 0x00000010 |
| #define | PWM_FAULTVAL_PWM3 0x00000008 |
| #define | PWM_FAULTVAL_PWM2 0x00000004 |
| #define | PWM_FAULTVAL_PWM1 0x00000002 |
| #define | PWM_FAULTVAL_PWM0 0x00000001 |
| #define | PWM_ENUPD_ENUPD7_M 0x0000C000 |
| #define | PWM_ENUPD_ENUPD7_IMM 0x00000000 |
| #define | PWM_ENUPD_ENUPD7_LSYNC 0x00008000 |
| #define | PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 |
| #define | PWM_ENUPD_ENUPD6_M 0x00003000 |
| #define | PWM_ENUPD_ENUPD6_IMM 0x00000000 |
| #define | PWM_ENUPD_ENUPD6_LSYNC 0x00002000 |
| #define | PWM_ENUPD_ENUPD6_GSYNC 0x00003000 |
| #define | PWM_ENUPD_ENUPD5_M 0x00000C00 |
| #define | PWM_ENUPD_ENUPD5_IMM 0x00000000 |
| #define | PWM_ENUPD_ENUPD5_LSYNC 0x00000800 |
| #define | PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 |
| #define | PWM_ENUPD_ENUPD4_M 0x00000300 |
| #define | PWM_ENUPD_ENUPD4_IMM 0x00000000 |
| #define | PWM_ENUPD_ENUPD4_LSYNC 0x00000200 |
| #define | PWM_ENUPD_ENUPD4_GSYNC 0x00000300 |
| #define | PWM_ENUPD_ENUPD3_M 0x000000C0 |
| #define | PWM_ENUPD_ENUPD3_IMM 0x00000000 |
| #define | PWM_ENUPD_ENUPD3_LSYNC 0x00000080 |
| #define | PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 |
| #define | PWM_ENUPD_ENUPD2_M 0x00000030 |
| #define | PWM_ENUPD_ENUPD2_IMM 0x00000000 |
| #define | PWM_ENUPD_ENUPD2_LSYNC 0x00000020 |
| #define | PWM_ENUPD_ENUPD2_GSYNC 0x00000030 |
| #define | PWM_ENUPD_ENUPD1_M 0x0000000C |
| #define | PWM_ENUPD_ENUPD1_IMM 0x00000000 |
| #define | PWM_ENUPD_ENUPD1_LSYNC 0x00000008 |
| #define | PWM_ENUPD_ENUPD1_GSYNC 0x0000000C |
| #define | PWM_ENUPD_ENUPD0_M 0x00000003 |
| #define | PWM_ENUPD_ENUPD0_IMM 0x00000000 |
| #define | PWM_ENUPD_ENUPD0_LSYNC 0x00000002 |
| #define | PWM_ENUPD_ENUPD0_GSYNC 0x00000003 |
| #define | PWM_0_CTL_LATCH 0x00040000 |
| #define | PWM_0_CTL_MINFLTPER 0x00020000 |
| #define | PWM_0_CTL_FLTSRC 0x00010000 |
| #define | PWM_0_CTL_DBFALLUPD_M 0x0000C000 |
| #define | PWM_0_CTL_DBFALLUPD_I 0x00000000 |
| #define | PWM_0_CTL_DBFALLUPD_LS 0x00008000 |
| #define | PWM_0_CTL_DBFALLUPD_GS 0x0000C000 |
| #define | PWM_0_CTL_DBRISEUPD_M 0x00003000 |
| #define | PWM_0_CTL_DBRISEUPD_I 0x00000000 |
| #define | PWM_0_CTL_DBRISEUPD_LS 0x00002000 |
| #define | PWM_0_CTL_DBRISEUPD_GS 0x00003000 |
| #define | PWM_0_CTL_DBCTLUPD_M 0x00000C00 |
| #define | PWM_0_CTL_DBCTLUPD_I 0x00000000 |
| #define | PWM_0_CTL_DBCTLUPD_LS 0x00000800 |
| #define | PWM_0_CTL_DBCTLUPD_GS 0x00000C00 |
| #define | PWM_0_CTL_GENBUPD_M 0x00000300 |
| #define | PWM_0_CTL_GENBUPD_I 0x00000000 |
| #define | PWM_0_CTL_GENBUPD_LS 0x00000200 |
| #define | PWM_0_CTL_GENBUPD_GS 0x00000300 |
| #define | PWM_0_CTL_GENAUPD_M 0x000000C0 |
| #define | PWM_0_CTL_GENAUPD_I 0x00000000 |
| #define | PWM_0_CTL_GENAUPD_LS 0x00000080 |
| #define | PWM_0_CTL_GENAUPD_GS 0x000000C0 |
| #define | PWM_0_CTL_CMPBUPD 0x00000020 |
| #define | PWM_0_CTL_CMPAUPD 0x00000010 |
| #define | PWM_0_CTL_LOADUPD 0x00000008 |
| #define | PWM_0_CTL_DEBUG 0x00000004 |
| #define | PWM_0_CTL_MODE 0x00000002 |
| #define | PWM_0_CTL_ENABLE 0x00000001 |
| #define | PWM_0_INTEN_TRCMPBD 0x00002000 |
| #define | PWM_0_INTEN_TRCMPBU 0x00001000 |
| #define | PWM_0_INTEN_TRCMPAD 0x00000800 |
| #define | PWM_0_INTEN_TRCMPAU 0x00000400 |
| #define | PWM_0_INTEN_TRCNTLOAD 0x00000200 |
| #define | PWM_0_INTEN_TRCNTZERO 0x00000100 |
| #define | PWM_0_INTEN_INTCMPBD 0x00000020 |
| #define | PWM_0_INTEN_INTCMPBU 0x00000010 |
| #define | PWM_0_INTEN_INTCMPAD 0x00000008 |
| #define | PWM_0_INTEN_INTCMPAU 0x00000004 |
| #define | PWM_0_INTEN_INTCNTLOAD 0x00000002 |
| #define | PWM_0_INTEN_INTCNTZERO 0x00000001 |
| #define | PWM_0_RIS_INTCMPBD 0x00000020 |
| #define | PWM_0_RIS_INTCMPBU 0x00000010 |
| #define | PWM_0_RIS_INTCMPAD 0x00000008 |
| #define | PWM_0_RIS_INTCMPAU 0x00000004 |
| #define | PWM_0_RIS_INTCNTLOAD 0x00000002 |
| #define | PWM_0_RIS_INTCNTZERO 0x00000001 |
| #define | PWM_0_ISC_INTCMPBD 0x00000020 |
| #define | PWM_0_ISC_INTCMPBU 0x00000010 |
| #define | PWM_0_ISC_INTCMPAD 0x00000008 |
| #define | PWM_0_ISC_INTCMPAU 0x00000004 |
| #define | PWM_0_ISC_INTCNTLOAD 0x00000002 |
| #define | PWM_0_ISC_INTCNTZERO 0x00000001 |
| #define | PWM_0_LOAD_M 0x0000FFFF |
| #define | PWM_0_LOAD_S 0 |
| #define | PWM_0_COUNT_M 0x0000FFFF |
| #define | PWM_0_COUNT_S 0 |
| #define | PWM_0_CMPA_M 0x0000FFFF |
| #define | PWM_0_CMPA_S 0 |
| #define | PWM_0_CMPB_M 0x0000FFFF |
| #define | PWM_0_CMPB_S 0 |
| #define | PWM_0_GENA_ACTCMPBD_M 0x00000C00 |
| #define | PWM_0_GENA_ACTCMPBD_NONE 0x00000000 |
| #define | PWM_0_GENA_ACTCMPBD_INV 0x00000400 |
| #define | PWM_0_GENA_ACTCMPBD_ZERO 0x00000800 |
| #define | PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 |
| #define | PWM_0_GENA_ACTCMPBU_M 0x00000300 |
| #define | PWM_0_GENA_ACTCMPBU_NONE 0x00000000 |
| #define | PWM_0_GENA_ACTCMPBU_INV 0x00000100 |
| #define | PWM_0_GENA_ACTCMPBU_ZERO 0x00000200 |
| #define | PWM_0_GENA_ACTCMPBU_ONE 0x00000300 |
| #define | PWM_0_GENA_ACTCMPAD_M 0x000000C0 |
| #define | PWM_0_GENA_ACTCMPAD_NONE 0x00000000 |
| #define | PWM_0_GENA_ACTCMPAD_INV 0x00000040 |
| #define | PWM_0_GENA_ACTCMPAD_ZERO 0x00000080 |
| #define | PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 |
| #define | PWM_0_GENA_ACTCMPAU_M 0x00000030 |
| #define | PWM_0_GENA_ACTCMPAU_NONE 0x00000000 |
| #define | PWM_0_GENA_ACTCMPAU_INV 0x00000010 |
| #define | PWM_0_GENA_ACTCMPAU_ZERO 0x00000020 |
| #define | PWM_0_GENA_ACTCMPAU_ONE 0x00000030 |
| #define | PWM_0_GENA_ACTLOAD_M 0x0000000C |
| #define | PWM_0_GENA_ACTLOAD_NONE 0x00000000 |
| #define | PWM_0_GENA_ACTLOAD_INV 0x00000004 |
| #define | PWM_0_GENA_ACTLOAD_ZERO 0x00000008 |
| #define | PWM_0_GENA_ACTLOAD_ONE 0x0000000C |
| #define | PWM_0_GENA_ACTZERO_M 0x00000003 |
| #define | PWM_0_GENA_ACTZERO_NONE 0x00000000 |
| #define | PWM_0_GENA_ACTZERO_INV 0x00000001 |
| #define | PWM_0_GENA_ACTZERO_ZERO 0x00000002 |
| #define | PWM_0_GENA_ACTZERO_ONE 0x00000003 |
| #define | PWM_0_GENB_ACTCMPBD_M 0x00000C00 |
| #define | PWM_0_GENB_ACTCMPBD_NONE 0x00000000 |
| #define | PWM_0_GENB_ACTCMPBD_INV 0x00000400 |
| #define | PWM_0_GENB_ACTCMPBD_ZERO 0x00000800 |
| #define | PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 |
| #define | PWM_0_GENB_ACTCMPBU_M 0x00000300 |
| #define | PWM_0_GENB_ACTCMPBU_NONE 0x00000000 |
| #define | PWM_0_GENB_ACTCMPBU_INV 0x00000100 |
| #define | PWM_0_GENB_ACTCMPBU_ZERO 0x00000200 |
| #define | PWM_0_GENB_ACTCMPBU_ONE 0x00000300 |
| #define | PWM_0_GENB_ACTCMPAD_M 0x000000C0 |
| #define | PWM_0_GENB_ACTCMPAD_NONE 0x00000000 |
| #define | PWM_0_GENB_ACTCMPAD_INV 0x00000040 |
| #define | PWM_0_GENB_ACTCMPAD_ZERO 0x00000080 |
| #define | PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 |
| #define | PWM_0_GENB_ACTCMPAU_M 0x00000030 |
| #define | PWM_0_GENB_ACTCMPAU_NONE 0x00000000 |
| #define | PWM_0_GENB_ACTCMPAU_INV 0x00000010 |
| #define | PWM_0_GENB_ACTCMPAU_ZERO 0x00000020 |
| #define | PWM_0_GENB_ACTCMPAU_ONE 0x00000030 |
| #define | PWM_0_GENB_ACTLOAD_M 0x0000000C |
| #define | PWM_0_GENB_ACTLOAD_NONE 0x00000000 |
| #define | PWM_0_GENB_ACTLOAD_INV 0x00000004 |
| #define | PWM_0_GENB_ACTLOAD_ZERO 0x00000008 |
| #define | PWM_0_GENB_ACTLOAD_ONE 0x0000000C |
| #define | PWM_0_GENB_ACTZERO_M 0x00000003 |
| #define | PWM_0_GENB_ACTZERO_NONE 0x00000000 |
| #define | PWM_0_GENB_ACTZERO_INV 0x00000001 |
| #define | PWM_0_GENB_ACTZERO_ZERO 0x00000002 |
| #define | PWM_0_GENB_ACTZERO_ONE 0x00000003 |
| #define | PWM_0_DBCTL_ENABLE 0x00000001 |
| #define | PWM_0_DBRISE_DELAY_M 0x00000FFF |
| #define | PWM_0_DBRISE_DELAY_S 0 |
| #define | PWM_0_DBFALL_DELAY_M 0x00000FFF |
| #define | PWM_0_DBFALL_DELAY_S 0 |
| #define | PWM_0_FLTSRC0_FAULT3 0x00000008 |
| #define | PWM_0_FLTSRC0_FAULT2 0x00000004 |
| #define | PWM_0_FLTSRC0_FAULT1 0x00000002 |
| #define | PWM_0_FLTSRC0_FAULT0 0x00000001 |
| #define | PWM_0_FLTSRC1_DCMP7 0x00000080 |
| #define | PWM_0_FLTSRC1_DCMP6 0x00000040 |
| #define | PWM_0_FLTSRC1_DCMP5 0x00000020 |
| #define | PWM_0_FLTSRC1_DCMP4 0x00000010 |
| #define | PWM_0_FLTSRC1_DCMP3 0x00000008 |
| #define | PWM_0_FLTSRC1_DCMP2 0x00000004 |
| #define | PWM_0_FLTSRC1_DCMP1 0x00000002 |
| #define | PWM_0_FLTSRC1_DCMP0 0x00000001 |
| #define | PWM_0_MINFLTPER_M 0x0000FFFF |
| #define | PWM_0_MINFLTPER_S 0 |
| #define | PWM_1_CTL_LATCH 0x00040000 |
| #define | PWM_1_CTL_MINFLTPER 0x00020000 |
| #define | PWM_1_CTL_FLTSRC 0x00010000 |
| #define | PWM_1_CTL_DBFALLUPD_M 0x0000C000 |
| #define | PWM_1_CTL_DBFALLUPD_I 0x00000000 |
| #define | PWM_1_CTL_DBFALLUPD_LS 0x00008000 |
| #define | PWM_1_CTL_DBFALLUPD_GS 0x0000C000 |
| #define | PWM_1_CTL_DBRISEUPD_M 0x00003000 |
| #define | PWM_1_CTL_DBRISEUPD_I 0x00000000 |
| #define | PWM_1_CTL_DBRISEUPD_LS 0x00002000 |
| #define | PWM_1_CTL_DBRISEUPD_GS 0x00003000 |
| #define | PWM_1_CTL_DBCTLUPD_M 0x00000C00 |
| #define | PWM_1_CTL_DBCTLUPD_I 0x00000000 |
| #define | PWM_1_CTL_DBCTLUPD_LS 0x00000800 |
| #define | PWM_1_CTL_DBCTLUPD_GS 0x00000C00 |
| #define | PWM_1_CTL_GENBUPD_M 0x00000300 |
| #define | PWM_1_CTL_GENBUPD_I 0x00000000 |
| #define | PWM_1_CTL_GENBUPD_LS 0x00000200 |
| #define | PWM_1_CTL_GENBUPD_GS 0x00000300 |
| #define | PWM_1_CTL_GENAUPD_M 0x000000C0 |
| #define | PWM_1_CTL_GENAUPD_I 0x00000000 |
| #define | PWM_1_CTL_GENAUPD_LS 0x00000080 |
| #define | PWM_1_CTL_GENAUPD_GS 0x000000C0 |
| #define | PWM_1_CTL_CMPBUPD 0x00000020 |
| #define | PWM_1_CTL_CMPAUPD 0x00000010 |
| #define | PWM_1_CTL_LOADUPD 0x00000008 |
| #define | PWM_1_CTL_DEBUG 0x00000004 |
| #define | PWM_1_CTL_MODE 0x00000002 |
| #define | PWM_1_CTL_ENABLE 0x00000001 |
| #define | PWM_1_INTEN_TRCMPBD 0x00002000 |
| #define | PWM_1_INTEN_TRCMPBU 0x00001000 |
| #define | PWM_1_INTEN_TRCMPAD 0x00000800 |
| #define | PWM_1_INTEN_TRCMPAU 0x00000400 |
| #define | PWM_1_INTEN_TRCNTLOAD 0x00000200 |
| #define | PWM_1_INTEN_TRCNTZERO 0x00000100 |
| #define | PWM_1_INTEN_INTCMPBD 0x00000020 |
| #define | PWM_1_INTEN_INTCMPBU 0x00000010 |
| #define | PWM_1_INTEN_INTCMPAD 0x00000008 |
| #define | PWM_1_INTEN_INTCMPAU 0x00000004 |
| #define | PWM_1_INTEN_INTCNTLOAD 0x00000002 |
| #define | PWM_1_INTEN_INTCNTZERO 0x00000001 |
| #define | PWM_1_RIS_INTCMPBD 0x00000020 |
| #define | PWM_1_RIS_INTCMPBU 0x00000010 |
| #define | PWM_1_RIS_INTCMPAD 0x00000008 |
| #define | PWM_1_RIS_INTCMPAU 0x00000004 |
| #define | PWM_1_RIS_INTCNTLOAD 0x00000002 |
| #define | PWM_1_RIS_INTCNTZERO 0x00000001 |
| #define | PWM_1_ISC_INTCMPBD 0x00000020 |
| #define | PWM_1_ISC_INTCMPBU 0x00000010 |
| #define | PWM_1_ISC_INTCMPAD 0x00000008 |
| #define | PWM_1_ISC_INTCMPAU 0x00000004 |
| #define | PWM_1_ISC_INTCNTLOAD 0x00000002 |
| #define | PWM_1_ISC_INTCNTZERO 0x00000001 |
| #define | PWM_1_LOAD_LOAD_M 0x0000FFFF |
| #define | PWM_1_LOAD_LOAD_S 0 |
| #define | PWM_1_COUNT_COUNT_M 0x0000FFFF |
| #define | PWM_1_COUNT_COUNT_S 0 |
| #define | PWM_1_CMPA_COMPA_M 0x0000FFFF |
| #define | PWM_1_CMPA_COMPA_S 0 |
| #define | PWM_1_CMPB_COMPB_M 0x0000FFFF |
| #define | PWM_1_CMPB_COMPB_S 0 |
| #define | PWM_1_GENA_ACTCMPBD_M 0x00000C00 |
| #define | PWM_1_GENA_ACTCMPBD_NONE 0x00000000 |
| #define | PWM_1_GENA_ACTCMPBD_INV 0x00000400 |
| #define | PWM_1_GENA_ACTCMPBD_ZERO 0x00000800 |
| #define | PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 |
| #define | PWM_1_GENA_ACTCMPBU_M 0x00000300 |
| #define | PWM_1_GENA_ACTCMPBU_NONE 0x00000000 |
| #define | PWM_1_GENA_ACTCMPBU_INV 0x00000100 |
| #define | PWM_1_GENA_ACTCMPBU_ZERO 0x00000200 |
| #define | PWM_1_GENA_ACTCMPBU_ONE 0x00000300 |
| #define | PWM_1_GENA_ACTCMPAD_M 0x000000C0 |
| #define | PWM_1_GENA_ACTCMPAD_NONE 0x00000000 |
| #define | PWM_1_GENA_ACTCMPAD_INV 0x00000040 |
| #define | PWM_1_GENA_ACTCMPAD_ZERO 0x00000080 |
| #define | PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 |
| #define | PWM_1_GENA_ACTCMPAU_M 0x00000030 |
| #define | PWM_1_GENA_ACTCMPAU_NONE 0x00000000 |
| #define | PWM_1_GENA_ACTCMPAU_INV 0x00000010 |
| #define | PWM_1_GENA_ACTCMPAU_ZERO 0x00000020 |
| #define | PWM_1_GENA_ACTCMPAU_ONE 0x00000030 |
| #define | PWM_1_GENA_ACTLOAD_M 0x0000000C |
| #define | PWM_1_GENA_ACTLOAD_NONE 0x00000000 |
| #define | PWM_1_GENA_ACTLOAD_INV 0x00000004 |
| #define | PWM_1_GENA_ACTLOAD_ZERO 0x00000008 |
| #define | PWM_1_GENA_ACTLOAD_ONE 0x0000000C |
| #define | PWM_1_GENA_ACTZERO_M 0x00000003 |
| #define | PWM_1_GENA_ACTZERO_NONE 0x00000000 |
| #define | PWM_1_GENA_ACTZERO_INV 0x00000001 |
| #define | PWM_1_GENA_ACTZERO_ZERO 0x00000002 |
| #define | PWM_1_GENA_ACTZERO_ONE 0x00000003 |
| #define | PWM_1_GENB_ACTCMPBD_M 0x00000C00 |
| #define | PWM_1_GENB_ACTCMPBD_NONE 0x00000000 |
| #define | PWM_1_GENB_ACTCMPBD_INV 0x00000400 |
| #define | PWM_1_GENB_ACTCMPBD_ZERO 0x00000800 |
| #define | PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 |
| #define | PWM_1_GENB_ACTCMPBU_M 0x00000300 |
| #define | PWM_1_GENB_ACTCMPBU_NONE 0x00000000 |
| #define | PWM_1_GENB_ACTCMPBU_INV 0x00000100 |
| #define | PWM_1_GENB_ACTCMPBU_ZERO 0x00000200 |
| #define | PWM_1_GENB_ACTCMPBU_ONE 0x00000300 |
| #define | PWM_1_GENB_ACTCMPAD_M 0x000000C0 |
| #define | PWM_1_GENB_ACTCMPAD_NONE 0x00000000 |
| #define | PWM_1_GENB_ACTCMPAD_INV 0x00000040 |
| #define | PWM_1_GENB_ACTCMPAD_ZERO 0x00000080 |
| #define | PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 |
| #define | PWM_1_GENB_ACTCMPAU_M 0x00000030 |
| #define | PWM_1_GENB_ACTCMPAU_NONE 0x00000000 |
| #define | PWM_1_GENB_ACTCMPAU_INV 0x00000010 |
| #define | PWM_1_GENB_ACTCMPAU_ZERO 0x00000020 |
| #define | PWM_1_GENB_ACTCMPAU_ONE 0x00000030 |
| #define | PWM_1_GENB_ACTLOAD_M 0x0000000C |
| #define | PWM_1_GENB_ACTLOAD_NONE 0x00000000 |
| #define | PWM_1_GENB_ACTLOAD_INV 0x00000004 |
| #define | PWM_1_GENB_ACTLOAD_ZERO 0x00000008 |
| #define | PWM_1_GENB_ACTLOAD_ONE 0x0000000C |
| #define | PWM_1_GENB_ACTZERO_M 0x00000003 |
| #define | PWM_1_GENB_ACTZERO_NONE 0x00000000 |
| #define | PWM_1_GENB_ACTZERO_INV 0x00000001 |
| #define | PWM_1_GENB_ACTZERO_ZERO 0x00000002 |
| #define | PWM_1_GENB_ACTZERO_ONE 0x00000003 |
| #define | PWM_1_DBCTL_ENABLE 0x00000001 |
| #define | PWM_1_DBRISE_RISEDELAY_M 0x00000FFF |
| #define | PWM_1_DBRISE_RISEDELAY_S 0 |
| #define | PWM_1_DBFALL_FALLDELAY_M 0x00000FFF |
| #define | PWM_1_DBFALL_FALLDELAY_S 0 |
| #define | PWM_1_FLTSRC0_FAULT3 0x00000008 |
| #define | PWM_1_FLTSRC0_FAULT2 0x00000004 |
| #define | PWM_1_FLTSRC0_FAULT1 0x00000002 |
| #define | PWM_1_FLTSRC0_FAULT0 0x00000001 |
| #define | PWM_1_FLTSRC1_DCMP7 0x00000080 |
| #define | PWM_1_FLTSRC1_DCMP6 0x00000040 |
| #define | PWM_1_FLTSRC1_DCMP5 0x00000020 |
| #define | PWM_1_FLTSRC1_DCMP4 0x00000010 |
| #define | PWM_1_FLTSRC1_DCMP3 0x00000008 |
| #define | PWM_1_FLTSRC1_DCMP2 0x00000004 |
| #define | PWM_1_FLTSRC1_DCMP1 0x00000002 |
| #define | PWM_1_FLTSRC1_DCMP0 0x00000001 |
| #define | PWM_1_MINFLTPER_MFP_M 0x0000FFFF |
| #define | PWM_1_MINFLTPER_MFP_S 0 |
| #define | PWM_2_CTL_LATCH 0x00040000 |
| #define | PWM_2_CTL_MINFLTPER 0x00020000 |
| #define | PWM_2_CTL_FLTSRC 0x00010000 |
| #define | PWM_2_CTL_DBFALLUPD_M 0x0000C000 |
| #define | PWM_2_CTL_DBFALLUPD_I 0x00000000 |
| #define | PWM_2_CTL_DBFALLUPD_LS 0x00008000 |
| #define | PWM_2_CTL_DBFALLUPD_GS 0x0000C000 |
| #define | PWM_2_CTL_DBRISEUPD_M 0x00003000 |
| #define | PWM_2_CTL_DBRISEUPD_I 0x00000000 |
| #define | PWM_2_CTL_DBRISEUPD_LS 0x00002000 |
| #define | PWM_2_CTL_DBRISEUPD_GS 0x00003000 |
| #define | PWM_2_CTL_DBCTLUPD_M 0x00000C00 |
| #define | PWM_2_CTL_DBCTLUPD_I 0x00000000 |
| #define | PWM_2_CTL_DBCTLUPD_LS 0x00000800 |
| #define | PWM_2_CTL_DBCTLUPD_GS 0x00000C00 |
| #define | PWM_2_CTL_GENBUPD_M 0x00000300 |
| #define | PWM_2_CTL_GENBUPD_I 0x00000000 |
| #define | PWM_2_CTL_GENBUPD_LS 0x00000200 |
| #define | PWM_2_CTL_GENBUPD_GS 0x00000300 |
| #define | PWM_2_CTL_GENAUPD_M 0x000000C0 |
| #define | PWM_2_CTL_GENAUPD_I 0x00000000 |
| #define | PWM_2_CTL_GENAUPD_LS 0x00000080 |
| #define | PWM_2_CTL_GENAUPD_GS 0x000000C0 |
| #define | PWM_2_CTL_CMPBUPD 0x00000020 |
| #define | PWM_2_CTL_CMPAUPD 0x00000010 |
| #define | PWM_2_CTL_LOADUPD 0x00000008 |
| #define | PWM_2_CTL_DEBUG 0x00000004 |
| #define | PWM_2_CTL_MODE 0x00000002 |
| #define | PWM_2_CTL_ENABLE 0x00000001 |
| #define | PWM_2_INTEN_TRCMPBD 0x00002000 |
| #define | PWM_2_INTEN_TRCMPBU 0x00001000 |
| #define | PWM_2_INTEN_TRCMPAD 0x00000800 |
| #define | PWM_2_INTEN_TRCMPAU 0x00000400 |
| #define | PWM_2_INTEN_TRCNTLOAD 0x00000200 |
| #define | PWM_2_INTEN_TRCNTZERO 0x00000100 |
| #define | PWM_2_INTEN_INTCMPBD 0x00000020 |
| #define | PWM_2_INTEN_INTCMPBU 0x00000010 |
| #define | PWM_2_INTEN_INTCMPAD 0x00000008 |
| #define | PWM_2_INTEN_INTCMPAU 0x00000004 |
| #define | PWM_2_INTEN_INTCNTLOAD 0x00000002 |
| #define | PWM_2_INTEN_INTCNTZERO 0x00000001 |
| #define | PWM_2_RIS_INTCMPBD 0x00000020 |
| #define | PWM_2_RIS_INTCMPBU 0x00000010 |
| #define | PWM_2_RIS_INTCMPAD 0x00000008 |
| #define | PWM_2_RIS_INTCMPAU 0x00000004 |
| #define | PWM_2_RIS_INTCNTLOAD 0x00000002 |
| #define | PWM_2_RIS_INTCNTZERO 0x00000001 |
| #define | PWM_2_ISC_INTCMPBD 0x00000020 |
| #define | PWM_2_ISC_INTCMPBU 0x00000010 |
| #define | PWM_2_ISC_INTCMPAD 0x00000008 |
| #define | PWM_2_ISC_INTCMPAU 0x00000004 |
| #define | PWM_2_ISC_INTCNTLOAD 0x00000002 |
| #define | PWM_2_ISC_INTCNTZERO 0x00000001 |
| #define | PWM_2_LOAD_LOAD_M 0x0000FFFF |
| #define | PWM_2_LOAD_LOAD_S 0 |
| #define | PWM_2_COUNT_COUNT_M 0x0000FFFF |
| #define | PWM_2_COUNT_COUNT_S 0 |
| #define | PWM_2_CMPA_COMPA_M 0x0000FFFF |
| #define | PWM_2_CMPA_COMPA_S 0 |
| #define | PWM_2_CMPB_COMPB_M 0x0000FFFF |
| #define | PWM_2_CMPB_COMPB_S 0 |
| #define | PWM_2_GENA_ACTCMPBD_M 0x00000C00 |
| #define | PWM_2_GENA_ACTCMPBD_NONE 0x00000000 |
| #define | PWM_2_GENA_ACTCMPBD_INV 0x00000400 |
| #define | PWM_2_GENA_ACTCMPBD_ZERO 0x00000800 |
| #define | PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 |
| #define | PWM_2_GENA_ACTCMPBU_M 0x00000300 |
| #define | PWM_2_GENA_ACTCMPBU_NONE 0x00000000 |
| #define | PWM_2_GENA_ACTCMPBU_INV 0x00000100 |
| #define | PWM_2_GENA_ACTCMPBU_ZERO 0x00000200 |
| #define | PWM_2_GENA_ACTCMPBU_ONE 0x00000300 |
| #define | PWM_2_GENA_ACTCMPAD_M 0x000000C0 |
| #define | PWM_2_GENA_ACTCMPAD_NONE 0x00000000 |
| #define | PWM_2_GENA_ACTCMPAD_INV 0x00000040 |
| #define | PWM_2_GENA_ACTCMPAD_ZERO 0x00000080 |
| #define | PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 |
| #define | PWM_2_GENA_ACTCMPAU_M 0x00000030 |
| #define | PWM_2_GENA_ACTCMPAU_NONE 0x00000000 |
| #define | PWM_2_GENA_ACTCMPAU_INV 0x00000010 |
| #define | PWM_2_GENA_ACTCMPAU_ZERO 0x00000020 |
| #define | PWM_2_GENA_ACTCMPAU_ONE 0x00000030 |
| #define | PWM_2_GENA_ACTLOAD_M 0x0000000C |
| #define | PWM_2_GENA_ACTLOAD_NONE 0x00000000 |
| #define | PWM_2_GENA_ACTLOAD_INV 0x00000004 |
| #define | PWM_2_GENA_ACTLOAD_ZERO 0x00000008 |
| #define | PWM_2_GENA_ACTLOAD_ONE 0x0000000C |
| #define | PWM_2_GENA_ACTZERO_M 0x00000003 |
| #define | PWM_2_GENA_ACTZERO_NONE 0x00000000 |
| #define | PWM_2_GENA_ACTZERO_INV 0x00000001 |
| #define | PWM_2_GENA_ACTZERO_ZERO 0x00000002 |
| #define | PWM_2_GENA_ACTZERO_ONE 0x00000003 |
| #define | PWM_2_GENB_ACTCMPBD_M 0x00000C00 |
| #define | PWM_2_GENB_ACTCMPBD_NONE 0x00000000 |
| #define | PWM_2_GENB_ACTCMPBD_INV 0x00000400 |
| #define | PWM_2_GENB_ACTCMPBD_ZERO 0x00000800 |
| #define | PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 |
| #define | PWM_2_GENB_ACTCMPBU_M 0x00000300 |
| #define | PWM_2_GENB_ACTCMPBU_NONE 0x00000000 |
| #define | PWM_2_GENB_ACTCMPBU_INV 0x00000100 |
| #define | PWM_2_GENB_ACTCMPBU_ZERO 0x00000200 |
| #define | PWM_2_GENB_ACTCMPBU_ONE 0x00000300 |
| #define | PWM_2_GENB_ACTCMPAD_M 0x000000C0 |
| #define | PWM_2_GENB_ACTCMPAD_NONE 0x00000000 |
| #define | PWM_2_GENB_ACTCMPAD_INV 0x00000040 |
| #define | PWM_2_GENB_ACTCMPAD_ZERO 0x00000080 |
| #define | PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 |
| #define | PWM_2_GENB_ACTCMPAU_M 0x00000030 |
| #define | PWM_2_GENB_ACTCMPAU_NONE 0x00000000 |
| #define | PWM_2_GENB_ACTCMPAU_INV 0x00000010 |
| #define | PWM_2_GENB_ACTCMPAU_ZERO 0x00000020 |
| #define | PWM_2_GENB_ACTCMPAU_ONE 0x00000030 |
| #define | PWM_2_GENB_ACTLOAD_M 0x0000000C |
| #define | PWM_2_GENB_ACTLOAD_NONE 0x00000000 |
| #define | PWM_2_GENB_ACTLOAD_INV 0x00000004 |
| #define | PWM_2_GENB_ACTLOAD_ZERO 0x00000008 |
| #define | PWM_2_GENB_ACTLOAD_ONE 0x0000000C |
| #define | PWM_2_GENB_ACTZERO_M 0x00000003 |
| #define | PWM_2_GENB_ACTZERO_NONE 0x00000000 |
| #define | PWM_2_GENB_ACTZERO_INV 0x00000001 |
| #define | PWM_2_GENB_ACTZERO_ZERO 0x00000002 |
| #define | PWM_2_GENB_ACTZERO_ONE 0x00000003 |
| #define | PWM_2_DBCTL_ENABLE 0x00000001 |
| #define | PWM_2_DBRISE_RISEDELAY_M 0x00000FFF |
| #define | PWM_2_DBRISE_RISEDELAY_S 0 |
| #define | PWM_2_DBFALL_FALLDELAY_M 0x00000FFF |
| #define | PWM_2_DBFALL_FALLDELAY_S 0 |
| #define | PWM_2_FLTSRC0_FAULT3 0x00000008 |
| #define | PWM_2_FLTSRC0_FAULT2 0x00000004 |
| #define | PWM_2_FLTSRC0_FAULT1 0x00000002 |
| #define | PWM_2_FLTSRC0_FAULT0 0x00000001 |
| #define | PWM_2_FLTSRC1_DCMP7 0x00000080 |
| #define | PWM_2_FLTSRC1_DCMP6 0x00000040 |
| #define | PWM_2_FLTSRC1_DCMP5 0x00000020 |
| #define | PWM_2_FLTSRC1_DCMP4 0x00000010 |
| #define | PWM_2_FLTSRC1_DCMP3 0x00000008 |
| #define | PWM_2_FLTSRC1_DCMP2 0x00000004 |
| #define | PWM_2_FLTSRC1_DCMP1 0x00000002 |
| #define | PWM_2_FLTSRC1_DCMP0 0x00000001 |
| #define | PWM_2_MINFLTPER_MFP_M 0x0000FFFF |
| #define | PWM_2_MINFLTPER_MFP_S 0 |
| #define | PWM_3_CTL_LATCH 0x00040000 |
| #define | PWM_3_CTL_MINFLTPER 0x00020000 |
| #define | PWM_3_CTL_FLTSRC 0x00010000 |
| #define | PWM_3_CTL_DBFALLUPD_M 0x0000C000 |
| #define | PWM_3_CTL_DBFALLUPD_I 0x00000000 |
| #define | PWM_3_CTL_DBFALLUPD_LS 0x00008000 |
| #define | PWM_3_CTL_DBFALLUPD_GS 0x0000C000 |
| #define | PWM_3_CTL_DBRISEUPD_M 0x00003000 |
| #define | PWM_3_CTL_DBRISEUPD_I 0x00000000 |
| #define | PWM_3_CTL_DBRISEUPD_LS 0x00002000 |
| #define | PWM_3_CTL_DBRISEUPD_GS 0x00003000 |
| #define | PWM_3_CTL_DBCTLUPD_M 0x00000C00 |
| #define | PWM_3_CTL_DBCTLUPD_I 0x00000000 |
| #define | PWM_3_CTL_DBCTLUPD_LS 0x00000800 |
| #define | PWM_3_CTL_DBCTLUPD_GS 0x00000C00 |
| #define | PWM_3_CTL_GENBUPD_M 0x00000300 |
| #define | PWM_3_CTL_GENBUPD_I 0x00000000 |
| #define | PWM_3_CTL_GENBUPD_LS 0x00000200 |
| #define | PWM_3_CTL_GENBUPD_GS 0x00000300 |
| #define | PWM_3_CTL_GENAUPD_M 0x000000C0 |
| #define | PWM_3_CTL_GENAUPD_I 0x00000000 |
| #define | PWM_3_CTL_GENAUPD_LS 0x00000080 |
| #define | PWM_3_CTL_GENAUPD_GS 0x000000C0 |
| #define | PWM_3_CTL_CMPBUPD 0x00000020 |
| #define | PWM_3_CTL_CMPAUPD 0x00000010 |
| #define | PWM_3_CTL_LOADUPD 0x00000008 |
| #define | PWM_3_CTL_DEBUG 0x00000004 |
| #define | PWM_3_CTL_MODE 0x00000002 |
| #define | PWM_3_CTL_ENABLE 0x00000001 |
| #define | PWM_3_INTEN_TRCMPBD 0x00002000 |
| #define | PWM_3_INTEN_TRCMPBU 0x00001000 |
| #define | PWM_3_INTEN_TRCMPAD 0x00000800 |
| #define | PWM_3_INTEN_TRCMPAU 0x00000400 |
| #define | PWM_3_INTEN_TRCNTLOAD 0x00000200 |
| #define | PWM_3_INTEN_TRCNTZERO 0x00000100 |
| #define | PWM_3_INTEN_INTCMPBD 0x00000020 |
| #define | PWM_3_INTEN_INTCMPBU 0x00000010 |
| #define | PWM_3_INTEN_INTCMPAD 0x00000008 |
| #define | PWM_3_INTEN_INTCMPAU 0x00000004 |
| #define | PWM_3_INTEN_INTCNTLOAD 0x00000002 |
| #define | PWM_3_INTEN_INTCNTZERO 0x00000001 |
| #define | PWM_3_RIS_INTCMPBD 0x00000020 |
| #define | PWM_3_RIS_INTCMPBU 0x00000010 |
| #define | PWM_3_RIS_INTCMPAD 0x00000008 |
| #define | PWM_3_RIS_INTCMPAU 0x00000004 |
| #define | PWM_3_RIS_INTCNTLOAD 0x00000002 |
| #define | PWM_3_RIS_INTCNTZERO 0x00000001 |
| #define | PWM_3_ISC_INTCMPBD 0x00000020 |
| #define | PWM_3_ISC_INTCMPBU 0x00000010 |
| #define | PWM_3_ISC_INTCMPAD 0x00000008 |
| #define | PWM_3_ISC_INTCMPAU 0x00000004 |
| #define | PWM_3_ISC_INTCNTLOAD 0x00000002 |
| #define | PWM_3_ISC_INTCNTZERO 0x00000001 |
| #define | PWM_3_LOAD_LOAD_M 0x0000FFFF |
| #define | PWM_3_LOAD_LOAD_S 0 |
| #define | PWM_3_COUNT_COUNT_M 0x0000FFFF |
| #define | PWM_3_COUNT_COUNT_S 0 |
| #define | PWM_3_CMPA_COMPA_M 0x0000FFFF |
| #define | PWM_3_CMPA_COMPA_S 0 |
| #define | PWM_3_CMPB_COMPB_M 0x0000FFFF |
| #define | PWM_3_CMPB_COMPB_S 0 |
| #define | PWM_3_GENA_ACTCMPBD_M 0x00000C00 |
| #define | PWM_3_GENA_ACTCMPBD_NONE 0x00000000 |
| #define | PWM_3_GENA_ACTCMPBD_INV 0x00000400 |
| #define | PWM_3_GENA_ACTCMPBD_ZERO 0x00000800 |
| #define | PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 |
| #define | PWM_3_GENA_ACTCMPBU_M 0x00000300 |
| #define | PWM_3_GENA_ACTCMPBU_NONE 0x00000000 |
| #define | PWM_3_GENA_ACTCMPBU_INV 0x00000100 |
| #define | PWM_3_GENA_ACTCMPBU_ZERO 0x00000200 |
| #define | PWM_3_GENA_ACTCMPBU_ONE 0x00000300 |
| #define | PWM_3_GENA_ACTCMPAD_M 0x000000C0 |
| #define | PWM_3_GENA_ACTCMPAD_NONE 0x00000000 |
| #define | PWM_3_GENA_ACTCMPAD_INV 0x00000040 |
| #define | PWM_3_GENA_ACTCMPAD_ZERO 0x00000080 |
| #define | PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 |
| #define | PWM_3_GENA_ACTCMPAU_M 0x00000030 |
| #define | PWM_3_GENA_ACTCMPAU_NONE 0x00000000 |
| #define | PWM_3_GENA_ACTCMPAU_INV 0x00000010 |
| #define | PWM_3_GENA_ACTCMPAU_ZERO 0x00000020 |
| #define | PWM_3_GENA_ACTCMPAU_ONE 0x00000030 |
| #define | PWM_3_GENA_ACTLOAD_M 0x0000000C |
| #define | PWM_3_GENA_ACTLOAD_NONE 0x00000000 |
| #define | PWM_3_GENA_ACTLOAD_INV 0x00000004 |
| #define | PWM_3_GENA_ACTLOAD_ZERO 0x00000008 |
| #define | PWM_3_GENA_ACTLOAD_ONE 0x0000000C |
| #define | PWM_3_GENA_ACTZERO_M 0x00000003 |
| #define | PWM_3_GENA_ACTZERO_NONE 0x00000000 |
| #define | PWM_3_GENA_ACTZERO_INV 0x00000001 |
| #define | PWM_3_GENA_ACTZERO_ZERO 0x00000002 |
| #define | PWM_3_GENA_ACTZERO_ONE 0x00000003 |
| #define | PWM_3_GENB_ACTCMPBD_M 0x00000C00 |
| #define | PWM_3_GENB_ACTCMPBD_NONE 0x00000000 |
| #define | PWM_3_GENB_ACTCMPBD_INV 0x00000400 |
| #define | PWM_3_GENB_ACTCMPBD_ZERO 0x00000800 |
| #define | PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 |
| #define | PWM_3_GENB_ACTCMPBU_M 0x00000300 |
| #define | PWM_3_GENB_ACTCMPBU_NONE 0x00000000 |
| #define | PWM_3_GENB_ACTCMPBU_INV 0x00000100 |
| #define | PWM_3_GENB_ACTCMPBU_ZERO 0x00000200 |
| #define | PWM_3_GENB_ACTCMPBU_ONE 0x00000300 |
| #define | PWM_3_GENB_ACTCMPAD_M 0x000000C0 |
| #define | PWM_3_GENB_ACTCMPAD_NONE 0x00000000 |
| #define | PWM_3_GENB_ACTCMPAD_INV 0x00000040 |
| #define | PWM_3_GENB_ACTCMPAD_ZERO 0x00000080 |
| #define | PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 |
| #define | PWM_3_GENB_ACTCMPAU_M 0x00000030 |
| #define | PWM_3_GENB_ACTCMPAU_NONE 0x00000000 |
| #define | PWM_3_GENB_ACTCMPAU_INV 0x00000010 |
| #define | PWM_3_GENB_ACTCMPAU_ZERO 0x00000020 |
| #define | PWM_3_GENB_ACTCMPAU_ONE 0x00000030 |
| #define | PWM_3_GENB_ACTLOAD_M 0x0000000C |
| #define | PWM_3_GENB_ACTLOAD_NONE 0x00000000 |
| #define | PWM_3_GENB_ACTLOAD_INV 0x00000004 |
| #define | PWM_3_GENB_ACTLOAD_ZERO 0x00000008 |
| #define | PWM_3_GENB_ACTLOAD_ONE 0x0000000C |
| #define | PWM_3_GENB_ACTZERO_M 0x00000003 |
| #define | PWM_3_GENB_ACTZERO_NONE 0x00000000 |
| #define | PWM_3_GENB_ACTZERO_INV 0x00000001 |
| #define | PWM_3_GENB_ACTZERO_ZERO 0x00000002 |
| #define | PWM_3_GENB_ACTZERO_ONE 0x00000003 |
| #define | PWM_3_DBCTL_ENABLE 0x00000001 |
| #define | PWM_3_DBRISE_RISEDELAY_M 0x00000FFF |
| #define | PWM_3_DBRISE_RISEDELAY_S 0 |
| #define | PWM_3_DBFALL_FALLDELAY_M 0x00000FFF |
| #define | PWM_3_DBFALL_FALLDELAY_S 0 |
| #define | PWM_3_FLTSRC0_FAULT3 0x00000008 |
| #define | PWM_3_FLTSRC0_FAULT2 0x00000004 |
| #define | PWM_3_FLTSRC0_FAULT1 0x00000002 |
| #define | PWM_3_FLTSRC0_FAULT0 0x00000001 |
| #define | PWM_3_FLTSRC1_DCMP7 0x00000080 |
| #define | PWM_3_FLTSRC1_DCMP6 0x00000040 |
| #define | PWM_3_FLTSRC1_DCMP5 0x00000020 |
| #define | PWM_3_FLTSRC1_DCMP4 0x00000010 |
| #define | PWM_3_FLTSRC1_DCMP3 0x00000008 |
| #define | PWM_3_FLTSRC1_DCMP2 0x00000004 |
| #define | PWM_3_FLTSRC1_DCMP1 0x00000002 |
| #define | PWM_3_FLTSRC1_DCMP0 0x00000001 |
| #define | PWM_3_MINFLTPER_MFP_M 0x0000FFFF |
| #define | PWM_3_MINFLTPER_MFP_S 0 |
| #define | PWM_0_FLTSEN_FAULT3 0x00000008 |
| #define | PWM_0_FLTSEN_FAULT2 0x00000004 |
| #define | PWM_0_FLTSEN_FAULT1 0x00000002 |
| #define | PWM_0_FLTSEN_FAULT0 0x00000001 |
| #define | PWM_0_FLTSTAT0_FAULT3 0x00000008 |
| #define | PWM_0_FLTSTAT0_FAULT2 0x00000004 |
| #define | PWM_0_FLTSTAT0_FAULT1 0x00000002 |
| #define | PWM_0_FLTSTAT0_FAULT0 0x00000001 |
| #define | PWM_0_FLTSTAT1_DCMP7 0x00000080 |
| #define | PWM_0_FLTSTAT1_DCMP6 0x00000040 |
| #define | PWM_0_FLTSTAT1_DCMP5 0x00000020 |
| #define | PWM_0_FLTSTAT1_DCMP4 0x00000010 |
| #define | PWM_0_FLTSTAT1_DCMP3 0x00000008 |
| #define | PWM_0_FLTSTAT1_DCMP2 0x00000004 |
| #define | PWM_0_FLTSTAT1_DCMP1 0x00000002 |
| #define | PWM_0_FLTSTAT1_DCMP0 0x00000001 |
| #define | PWM_1_FLTSEN_FAULT3 0x00000008 |
| #define | PWM_1_FLTSEN_FAULT2 0x00000004 |
| #define | PWM_1_FLTSEN_FAULT1 0x00000002 |
| #define | PWM_1_FLTSEN_FAULT0 0x00000001 |
| #define | PWM_1_FLTSTAT0_FAULT3 0x00000008 |
| #define | PWM_1_FLTSTAT0_FAULT2 0x00000004 |
| #define | PWM_1_FLTSTAT0_FAULT1 0x00000002 |
| #define | PWM_1_FLTSTAT0_FAULT0 0x00000001 |
| #define | PWM_1_FLTSTAT1_DCMP7 0x00000080 |
| #define | PWM_1_FLTSTAT1_DCMP6 0x00000040 |
| #define | PWM_1_FLTSTAT1_DCMP5 0x00000020 |
| #define | PWM_1_FLTSTAT1_DCMP4 0x00000010 |
| #define | PWM_1_FLTSTAT1_DCMP3 0x00000008 |
| #define | PWM_1_FLTSTAT1_DCMP2 0x00000004 |
| #define | PWM_1_FLTSTAT1_DCMP1 0x00000002 |
| #define | PWM_1_FLTSTAT1_DCMP0 0x00000001 |
| #define | PWM_2_FLTSEN_FAULT3 0x00000008 |
| #define | PWM_2_FLTSEN_FAULT2 0x00000004 |
| #define | PWM_2_FLTSEN_FAULT1 0x00000002 |
| #define | PWM_2_FLTSEN_FAULT0 0x00000001 |
| #define | PWM_2_FLTSTAT0_FAULT3 0x00000008 |
| #define | PWM_2_FLTSTAT0_FAULT2 0x00000004 |
| #define | PWM_2_FLTSTAT0_FAULT1 0x00000002 |
| #define | PWM_2_FLTSTAT0_FAULT0 0x00000001 |
| #define | PWM_2_FLTSTAT1_DCMP7 0x00000080 |
| #define | PWM_2_FLTSTAT1_DCMP6 0x00000040 |
| #define | PWM_2_FLTSTAT1_DCMP5 0x00000020 |
| #define | PWM_2_FLTSTAT1_DCMP4 0x00000010 |
| #define | PWM_2_FLTSTAT1_DCMP3 0x00000008 |
| #define | PWM_2_FLTSTAT1_DCMP2 0x00000004 |
| #define | PWM_2_FLTSTAT1_DCMP1 0x00000002 |
| #define | PWM_2_FLTSTAT1_DCMP0 0x00000001 |
| #define | PWM_3_FLTSEN_FAULT3 0x00000008 |
| #define | PWM_3_FLTSEN_FAULT2 0x00000004 |
| #define | PWM_3_FLTSEN_FAULT1 0x00000002 |
| #define | PWM_3_FLTSEN_FAULT0 0x00000001 |
| #define | PWM_3_FLTSTAT0_FAULT3 0x00000008 |
| #define | PWM_3_FLTSTAT0_FAULT2 0x00000004 |
| #define | PWM_3_FLTSTAT0_FAULT1 0x00000002 |
| #define | PWM_3_FLTSTAT0_FAULT0 0x00000001 |
| #define | PWM_3_FLTSTAT1_DCMP7 0x00000080 |
| #define | PWM_3_FLTSTAT1_DCMP6 0x00000040 |
| #define | PWM_3_FLTSTAT1_DCMP5 0x00000020 |
| #define | PWM_3_FLTSTAT1_DCMP4 0x00000010 |
| #define | PWM_3_FLTSTAT1_DCMP3 0x00000008 |
| #define | PWM_3_FLTSTAT1_DCMP2 0x00000004 |
| #define | PWM_3_FLTSTAT1_DCMP1 0x00000002 |
| #define | PWM_3_FLTSTAT1_DCMP0 0x00000001 |
| #define | PWM_PP_ONE 0x00000400 |
| #define | PWM_PP_EFAULT 0x00000200 |
| #define | PWM_PP_ESYNC 0x00000100 |
| #define | PWM_PP_FCNT_M 0x000000F0 |
| #define | PWM_PP_GCNT_M 0x0000000F |
| #define | PWM_PP_FCNT_S 4 |
| #define | PWM_PP_GCNT_S 0 |
| #define | QEI_CTL_FILTCNT_M 0x000F0000 |
| #define | QEI_CTL_FILTEN 0x00002000 |
| #define | QEI_CTL_STALLEN 0x00001000 |
| #define | QEI_CTL_INVI 0x00000800 |
| #define | QEI_CTL_INVB 0x00000400 |
| #define | QEI_CTL_INVA 0x00000200 |
| #define | QEI_CTL_VELDIV_M 0x000001C0 |
| #define | QEI_CTL_VELDIV_1 0x00000000 |
| #define | QEI_CTL_VELDIV_2 0x00000040 |
| #define | QEI_CTL_VELDIV_4 0x00000080 |
| #define | QEI_CTL_VELDIV_8 0x000000C0 |
| #define | QEI_CTL_VELDIV_16 0x00000100 |
| #define | QEI_CTL_VELDIV_32 0x00000140 |
| #define | QEI_CTL_VELDIV_64 0x00000180 |
| #define | QEI_CTL_VELDIV_128 0x000001C0 |
| #define | QEI_CTL_VELEN 0x00000020 |
| #define | QEI_CTL_RESMODE 0x00000010 |
| #define | QEI_CTL_CAPMODE 0x00000008 |
| #define | QEI_CTL_SIGMODE 0x00000004 |
| #define | QEI_CTL_SWAP 0x00000002 |
| #define | QEI_CTL_ENABLE 0x00000001 |
| #define | QEI_CTL_FILTCNT_S 16 |
| #define | QEI_STAT_DIRECTION 0x00000002 |
| #define | QEI_STAT_ERROR 0x00000001 |
| #define | QEI_POS_M 0xFFFFFFFF |
| #define | QEI_POS_S 0 |
| #define | QEI_MAXPOS_M 0xFFFFFFFF |
| #define | QEI_MAXPOS_S 0 |
| #define | QEI_LOAD_M 0xFFFFFFFF |
| #define | QEI_LOAD_S 0 |
| #define | QEI_TIME_M 0xFFFFFFFF |
| #define | QEI_TIME_S 0 |
| #define | QEI_COUNT_M 0xFFFFFFFF |
| #define | QEI_COUNT_S 0 |
| #define | QEI_SPEED_M 0xFFFFFFFF |
| #define | QEI_SPEED_S 0 |
| #define | QEI_INTEN_ERROR 0x00000008 |
| #define | QEI_INTEN_DIR 0x00000004 |
| #define | QEI_INTEN_TIMER 0x00000002 |
| #define | QEI_INTEN_INDEX 0x00000001 |
| #define | QEI_RIS_ERROR 0x00000008 |
| #define | QEI_RIS_DIR 0x00000004 |
| #define | QEI_RIS_TIMER 0x00000002 |
| #define | QEI_RIS_INDEX 0x00000001 |
| #define | QEI_ISC_ERROR 0x00000008 |
| #define | QEI_ISC_DIR 0x00000004 |
| #define | QEI_ISC_TIMER 0x00000002 |
| #define | QEI_ISC_INDEX 0x00000001 |
| #define | TIMER_CFG_M 0x00000007 |
| #define | TIMER_CFG_32_BIT_TIMER 0x00000000 |
| #define | TIMER_CFG_32_BIT_RTC 0x00000001 |
| #define | TIMER_CFG_16_BIT 0x00000004 |
| #define | TIMER_TAMR_TAPLO 0x00000800 |
| #define | TIMER_TAMR_TAMRSU 0x00000400 |
| #define | TIMER_TAMR_TAPWMIE 0x00000200 |
| #define | TIMER_TAMR_TAILD 0x00000100 |
| #define | TIMER_TAMR_TASNAPS 0x00000080 |
| #define | TIMER_TAMR_TAWOT 0x00000040 |
| #define | TIMER_TAMR_TAMIE 0x00000020 |
| #define | TIMER_TAMR_TACDIR 0x00000010 |
| #define | TIMER_TAMR_TAAMS 0x00000008 |
| #define | TIMER_TAMR_TACMR 0x00000004 |
| #define | TIMER_TAMR_TAMR_M 0x00000003 |
| #define | TIMER_TAMR_TAMR_1_SHOT 0x00000001 |
| #define | TIMER_TAMR_TAMR_PERIOD 0x00000002 |
| #define | TIMER_TAMR_TAMR_CAP 0x00000003 |
| #define | TIMER_TBMR_TBPLO 0x00000800 |
| #define | TIMER_TBMR_TBMRSU 0x00000400 |
| #define | TIMER_TBMR_TBPWMIE 0x00000200 |
| #define | TIMER_TBMR_TBILD 0x00000100 |
| #define | TIMER_TBMR_TBSNAPS 0x00000080 |
| #define | TIMER_TBMR_TBWOT 0x00000040 |
| #define | TIMER_TBMR_TBMIE 0x00000020 |
| #define | TIMER_TBMR_TBCDIR 0x00000010 |
| #define | TIMER_TBMR_TBAMS 0x00000008 |
| #define | TIMER_TBMR_TBCMR 0x00000004 |
| #define | TIMER_TBMR_TBMR_M 0x00000003 |
| #define | TIMER_TBMR_TBMR_1_SHOT 0x00000001 |
| #define | TIMER_TBMR_TBMR_PERIOD 0x00000002 |
| #define | TIMER_TBMR_TBMR_CAP 0x00000003 |
| #define | TIMER_CTL_TBPWML 0x00004000 |
| #define | TIMER_CTL_TBOTE 0x00002000 |
| #define | TIMER_CTL_TBEVENT_M 0x00000C00 |
| #define | TIMER_CTL_TBEVENT_POS 0x00000000 |
| #define | TIMER_CTL_TBEVENT_NEG 0x00000400 |
| #define | TIMER_CTL_TBEVENT_BOTH 0x00000C00 |
| #define | TIMER_CTL_TBSTALL 0x00000200 |
| #define | TIMER_CTL_TBEN 0x00000100 |
| #define | TIMER_CTL_TAPWML 0x00000040 |
| #define | TIMER_CTL_TAOTE 0x00000020 |
| #define | TIMER_CTL_RTCEN 0x00000010 |
| #define | TIMER_CTL_TAEVENT_M 0x0000000C |
| #define | TIMER_CTL_TAEVENT_POS 0x00000000 |
| #define | TIMER_CTL_TAEVENT_NEG 0x00000004 |
| #define | TIMER_CTL_TAEVENT_BOTH 0x0000000C |
| #define | TIMER_CTL_TASTALL 0x00000002 |
| #define | TIMER_CTL_TAEN 0x00000001 |
| #define | TIMER_SYNC_SYNCWT5_M 0x00C00000 |
| #define | TIMER_SYNC_SYNCWT5_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCWT5_TA 0x00400000 |
| #define | TIMER_SYNC_SYNCWT5_TB 0x00800000 |
| #define | TIMER_SYNC_SYNCWT5_TATB 0x00C00000 |
| #define | TIMER_SYNC_SYNCWT4_M 0x00300000 |
| #define | TIMER_SYNC_SYNCWT4_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCWT4_TA 0x00100000 |
| #define | TIMER_SYNC_SYNCWT4_TB 0x00200000 |
| #define | TIMER_SYNC_SYNCWT4_TATB 0x00300000 |
| #define | TIMER_SYNC_SYNCWT3_M 0x000C0000 |
| #define | TIMER_SYNC_SYNCWT3_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCWT3_TA 0x00040000 |
| #define | TIMER_SYNC_SYNCWT3_TB 0x00080000 |
| #define | TIMER_SYNC_SYNCWT3_TATB 0x000C0000 |
| #define | TIMER_SYNC_SYNCWT2_M 0x00030000 |
| #define | TIMER_SYNC_SYNCWT2_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCWT2_TA 0x00010000 |
| #define | TIMER_SYNC_SYNCWT2_TB 0x00020000 |
| #define | TIMER_SYNC_SYNCWT2_TATB 0x00030000 |
| #define | TIMER_SYNC_SYNCWT1_M 0x0000C000 |
| #define | TIMER_SYNC_SYNCWT1_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCWT1_TA 0x00004000 |
| #define | TIMER_SYNC_SYNCWT1_TB 0x00008000 |
| #define | TIMER_SYNC_SYNCWT1_TATB 0x0000C000 |
| #define | TIMER_SYNC_SYNCWT0_M 0x00003000 |
| #define | TIMER_SYNC_SYNCWT0_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCWT0_TA 0x00001000 |
| #define | TIMER_SYNC_SYNCWT0_TB 0x00002000 |
| #define | TIMER_SYNC_SYNCWT0_TATB 0x00003000 |
| #define | TIMER_SYNC_SYNCT5_M 0x00000C00 |
| #define | TIMER_SYNC_SYNCT5_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCT5_TA 0x00000400 |
| #define | TIMER_SYNC_SYNCT5_TB 0x00000800 |
| #define | TIMER_SYNC_SYNCT5_TATB 0x00000C00 |
| #define | TIMER_SYNC_SYNCT4_M 0x00000300 |
| #define | TIMER_SYNC_SYNCT4_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCT4_TA 0x00000100 |
| #define | TIMER_SYNC_SYNCT4_TB 0x00000200 |
| #define | TIMER_SYNC_SYNCT4_TATB 0x00000300 |
| #define | TIMER_SYNC_SYNCT3_M 0x000000C0 |
| #define | TIMER_SYNC_SYNCT3_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCT3_TA 0x00000040 |
| #define | TIMER_SYNC_SYNCT3_TB 0x00000080 |
| #define | TIMER_SYNC_SYNCT3_TATB 0x000000C0 |
| #define | TIMER_SYNC_SYNCT2_M 0x00000030 |
| #define | TIMER_SYNC_SYNCT2_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCT2_TA 0x00000010 |
| #define | TIMER_SYNC_SYNCT2_TB 0x00000020 |
| #define | TIMER_SYNC_SYNCT2_TATB 0x00000030 |
| #define | TIMER_SYNC_SYNCT1_M 0x0000000C |
| #define | TIMER_SYNC_SYNCT1_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCT1_TA 0x00000004 |
| #define | TIMER_SYNC_SYNCT1_TB 0x00000008 |
| #define | TIMER_SYNC_SYNCT1_TATB 0x0000000C |
| #define | TIMER_SYNC_SYNCT0_M 0x00000003 |
| #define | TIMER_SYNC_SYNCT0_NONE 0x00000000 |
| #define | TIMER_SYNC_SYNCT0_TA 0x00000001 |
| #define | TIMER_SYNC_SYNCT0_TB 0x00000002 |
| #define | TIMER_SYNC_SYNCT0_TATB 0x00000003 |
| #define | TIMER_IMR_WUEIM 0x00010000 |
| #define | TIMER_IMR_TBMIM 0x00000800 |
| #define | TIMER_IMR_CBEIM 0x00000400 |
| #define | TIMER_IMR_CBMIM 0x00000200 |
| #define | TIMER_IMR_TBTOIM 0x00000100 |
| #define | TIMER_IMR_TAMIM 0x00000010 |
| #define | TIMER_IMR_RTCIM 0x00000008 |
| #define | TIMER_IMR_CAEIM 0x00000004 |
| #define | TIMER_IMR_CAMIM 0x00000002 |
| #define | TIMER_IMR_TATOIM 0x00000001 |
| #define | TIMER_RIS_WUERIS 0x00010000 |
| #define | TIMER_RIS_TBMRIS 0x00000800 |
| #define | TIMER_RIS_CBERIS 0x00000400 |
| #define | TIMER_RIS_CBMRIS 0x00000200 |
| #define | TIMER_RIS_TBTORIS 0x00000100 |
| #define | TIMER_RIS_TAMRIS 0x00000010 |
| #define | TIMER_RIS_RTCRIS 0x00000008 |
| #define | TIMER_RIS_CAERIS 0x00000004 |
| #define | TIMER_RIS_CAMRIS 0x00000002 |
| #define | TIMER_RIS_TATORIS 0x00000001 |
| #define | TIMER_MIS_WUEMIS 0x00010000 |
| #define | TIMER_MIS_TBMMIS 0x00000800 |
| #define | TIMER_MIS_CBEMIS 0x00000400 |
| #define | TIMER_MIS_CBMMIS 0x00000200 |
| #define | TIMER_MIS_TBTOMIS 0x00000100 |
| #define | TIMER_MIS_TAMMIS 0x00000010 |
| #define | TIMER_MIS_RTCMIS 0x00000008 |
| #define | TIMER_MIS_CAEMIS 0x00000004 |
| #define | TIMER_MIS_CAMMIS 0x00000002 |
| #define | TIMER_MIS_TATOMIS 0x00000001 |
| #define | TIMER_ICR_WUECINT 0x00010000 |
| #define | TIMER_ICR_TBMCINT 0x00000800 |
| #define | TIMER_ICR_CBECINT 0x00000400 |
| #define | TIMER_ICR_CBMCINT 0x00000200 |
| #define | TIMER_ICR_TBTOCINT 0x00000100 |
| #define | TIMER_ICR_TAMCINT 0x00000010 |
| #define | TIMER_ICR_RTCCINT 0x00000008 |
| #define | TIMER_ICR_CAECINT 0x00000004 |
| #define | TIMER_ICR_CAMCINT 0x00000002 |
| #define | TIMER_ICR_TATOCINT 0x00000001 |
| #define | TIMER_TAILR_M 0xFFFFFFFF |
| #define | TIMER_TAILR_S 0 |
| #define | TIMER_TBILR_M 0xFFFFFFFF |
| #define | TIMER_TBILR_S 0 |
| #define | TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF |
| #define | TIMER_TAMATCHR_TAMR_S 0 |
| #define | TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF |
| #define | TIMER_TBMATCHR_TBMR_S 0 |
| #define | TIMER_TAPR_TAPSRH_M 0x0000FF00 |
| #define | TIMER_TAPR_TAPSR_M 0x000000FF |
| #define | TIMER_TAPR_TAPSRH_S 8 |
| #define | TIMER_TAPR_TAPSR_S 0 |
| #define | TIMER_TBPR_TBPSRH_M 0x0000FF00 |
| #define | TIMER_TBPR_TBPSR_M 0x000000FF |
| #define | TIMER_TBPR_TBPSRH_S 8 |
| #define | TIMER_TBPR_TBPSR_S 0 |
| #define | TIMER_TAPMR_TAPSMRH_M 0x0000FF00 |
| #define | TIMER_TAPMR_TAPSMR_M 0x000000FF |
| #define | TIMER_TAPMR_TAPSMRH_S 8 |
| #define | TIMER_TAPMR_TAPSMR_S 0 |
| #define | TIMER_TBPMR_TBPSMRH_M 0x0000FF00 |
| #define | TIMER_TBPMR_TBPSMR_M 0x000000FF |
| #define | TIMER_TBPMR_TBPSMRH_S 8 |
| #define | TIMER_TBPMR_TBPSMR_S 0 |
| #define | TIMER_TAR_M 0xFFFFFFFF |
| #define | TIMER_TAR_S 0 |
| #define | TIMER_TBR_M 0xFFFFFFFF |
| #define | TIMER_TBR_S 0 |
| #define | TIMER_TAV_M 0xFFFFFFFF |
| #define | TIMER_TAV_S 0 |
| #define | TIMER_TBV_M 0xFFFFFFFF |
| #define | TIMER_TBV_S 0 |
| #define | TIMER_RTCPD_RTCPD_M 0x0000FFFF |
| #define | TIMER_RTCPD_RTCPD_S 0 |
| #define | TIMER_TAPS_PSS_M 0x0000FFFF |
| #define | TIMER_TAPS_PSS_S 0 |
| #define | TIMER_TBPS_PSS_M 0x0000FFFF |
| #define | TIMER_TBPS_PSS_S 0 |
| #define | TIMER_TAPV_PSV_M 0x0000FFFF |
| #define | TIMER_TAPV_PSV_S 0 |
| #define | TIMER_TBPV_PSV_M 0x0000FFFF |
| #define | TIMER_TBPV_PSV_S 0 |
| #define | TIMER_PP_SIZE_M 0x0000000F |
| #define | TIMER_PP_SIZE_16 0x00000000 |
| #define | TIMER_PP_SIZE_32 0x00000001 |
| #define | ADC_ACTSS_BUSY 0x00010000 |
| #define | ADC_ACTSS_ASEN3 0x00000008 |
| #define | ADC_ACTSS_ASEN2 0x00000004 |
| #define | ADC_ACTSS_ASEN1 0x00000002 |
| #define | ADC_ACTSS_ASEN0 0x00000001 |
| #define | ADC_RIS_INRDC 0x00010000 |
| #define | ADC_RIS_INR3 0x00000008 |
| #define | ADC_RIS_INR2 0x00000004 |
| #define | ADC_RIS_INR1 0x00000002 |
| #define | ADC_RIS_INR0 0x00000001 |
| #define | ADC_IM_DCONSS3 0x00080000 |
| #define | ADC_IM_DCONSS2 0x00040000 |
| #define | ADC_IM_DCONSS1 0x00020000 |
| #define | ADC_IM_DCONSS0 0x00010000 |
| #define | ADC_IM_MASK3 0x00000008 |
| #define | ADC_IM_MASK2 0x00000004 |
| #define | ADC_IM_MASK1 0x00000002 |
| #define | ADC_IM_MASK0 0x00000001 |
| #define | ADC_ISC_DCINSS3 0x00080000 |
| #define | ADC_ISC_DCINSS2 0x00040000 |
| #define | ADC_ISC_DCINSS1 0x00020000 |
| #define | ADC_ISC_DCINSS0 0x00010000 |
| #define | ADC_ISC_IN3 0x00000008 |
| #define | ADC_ISC_IN2 0x00000004 |
| #define | ADC_ISC_IN1 0x00000002 |
| #define | ADC_ISC_IN0 0x00000001 |
| #define | ADC_OSTAT_OV3 0x00000008 |
| #define | ADC_OSTAT_OV2 0x00000004 |
| #define | ADC_OSTAT_OV1 0x00000002 |
| #define | ADC_OSTAT_OV0 0x00000001 |
| #define | ADC_EMUX_EM3_M 0x0000F000 |
| #define | ADC_EMUX_EM3_PROCESSOR 0x00000000 |
| #define | ADC_EMUX_EM3_COMP0 0x00001000 |
| #define | ADC_EMUX_EM3_COMP1 0x00002000 |
| #define | ADC_EMUX_EM3_COMP2 0x00003000 |
| #define | ADC_EMUX_EM3_EXTERNAL 0x00004000 |
| #define | ADC_EMUX_EM3_TIMER 0x00005000 |
| #define | ADC_EMUX_EM3_PWM0 0x00006000 |
| #define | ADC_EMUX_EM3_PWM1 0x00007000 |
| #define | ADC_EMUX_EM3_PWM2 0x00008000 |
| #define | ADC_EMUX_EM3_PWM3 0x00009000 |
| #define | ADC_EMUX_EM3_ALWAYS 0x0000F000 |
| #define | ADC_EMUX_EM2_M 0x00000F00 |
| #define | ADC_EMUX_EM2_PROCESSOR 0x00000000 |
| #define | ADC_EMUX_EM2_COMP0 0x00000100 |
| #define | ADC_EMUX_EM2_COMP1 0x00000200 |
| #define | ADC_EMUX_EM2_COMP2 0x00000300 |
| #define | ADC_EMUX_EM2_EXTERNAL 0x00000400 |
| #define | ADC_EMUX_EM2_TIMER 0x00000500 |
| #define | ADC_EMUX_EM2_PWM0 0x00000600 |
| #define | ADC_EMUX_EM2_PWM1 0x00000700 |
| #define | ADC_EMUX_EM2_PWM2 0x00000800 |
| #define | ADC_EMUX_EM2_PWM3 0x00000900 |
| #define | ADC_EMUX_EM2_ALWAYS 0x00000F00 |
| #define | ADC_EMUX_EM1_M 0x000000F0 |
| #define | ADC_EMUX_EM1_PROCESSOR 0x00000000 |
| #define | ADC_EMUX_EM1_COMP0 0x00000010 |
| #define | ADC_EMUX_EM1_COMP1 0x00000020 |
| #define | ADC_EMUX_EM1_COMP2 0x00000030 |
| #define | ADC_EMUX_EM1_EXTERNAL 0x00000040 |
| #define | ADC_EMUX_EM1_TIMER 0x00000050 |
| #define | ADC_EMUX_EM1_PWM0 0x00000060 |
| #define | ADC_EMUX_EM1_PWM1 0x00000070 |
| #define | ADC_EMUX_EM1_PWM2 0x00000080 |
| #define | ADC_EMUX_EM1_PWM3 0x00000090 |
| #define | ADC_EMUX_EM1_ALWAYS 0x000000F0 |
| #define | ADC_EMUX_EM0_M 0x0000000F |
| #define | ADC_EMUX_EM0_PROCESSOR 0x00000000 |
| #define | ADC_EMUX_EM0_COMP0 0x00000001 |
| #define | ADC_EMUX_EM0_COMP1 0x00000002 |
| #define | ADC_EMUX_EM0_COMP2 0x00000003 |
| #define | ADC_EMUX_EM0_EXTERNAL 0x00000004 |
| #define | ADC_EMUX_EM0_TIMER 0x00000005 |
| #define | ADC_EMUX_EM0_PWM0 0x00000006 |
| #define | ADC_EMUX_EM0_PWM1 0x00000007 |
| #define | ADC_EMUX_EM0_PWM2 0x00000008 |
| #define | ADC_EMUX_EM0_PWM3 0x00000009 |
| #define | ADC_EMUX_EM0_ALWAYS 0x0000000F |
| #define | ADC_USTAT_UV3 0x00000008 |
| #define | ADC_USTAT_UV2 0x00000004 |
| #define | ADC_USTAT_UV1 0x00000002 |
| #define | ADC_USTAT_UV0 0x00000001 |
| #define | ADC_TSSEL_PS3_M 0x30000000 |
| #define | ADC_TSSEL_PS3_0 0x00000000 |
| #define | ADC_TSSEL_PS3_1 0x10000000 |
| #define | ADC_TSSEL_PS2_M 0x00300000 |
| #define | ADC_TSSEL_PS2_0 0x00000000 |
| #define | ADC_TSSEL_PS2_1 0x00100000 |
| #define | ADC_TSSEL_PS1_M 0x00003000 |
| #define | ADC_TSSEL_PS1_0 0x00000000 |
| #define | ADC_TSSEL_PS1_1 0x00001000 |
| #define | ADC_TSSEL_PS0_M 0x00000030 |
| #define | ADC_TSSEL_PS0_0 0x00000000 |
| #define | ADC_TSSEL_PS0_1 0x00000010 |
| #define | ADC_SSPRI_SS3_M 0x00003000 |
| #define | ADC_SSPRI_SS2_M 0x00000300 |
| #define | ADC_SSPRI_SS1_M 0x00000030 |
| #define | ADC_SSPRI_SS0_M 0x00000003 |
| #define | ADC_SPC_PHASE_M 0x0000000F |
| #define | ADC_SPC_PHASE_0 0x00000000 |
| #define | ADC_SPC_PHASE_22_5 0x00000001 |
| #define | ADC_SPC_PHASE_45 0x00000002 |
| #define | ADC_SPC_PHASE_67_5 0x00000003 |
| #define | ADC_SPC_PHASE_90 0x00000004 |
| #define | ADC_SPC_PHASE_112_5 0x00000005 |
| #define | ADC_SPC_PHASE_135 0x00000006 |
| #define | ADC_SPC_PHASE_157_5 0x00000007 |
| #define | ADC_SPC_PHASE_180 0x00000008 |
| #define | ADC_SPC_PHASE_202_5 0x00000009 |
| #define | ADC_SPC_PHASE_225 0x0000000A |
| #define | ADC_SPC_PHASE_247_5 0x0000000B |
| #define | ADC_SPC_PHASE_270 0x0000000C |
| #define | ADC_SPC_PHASE_292_5 0x0000000D |
| #define | ADC_SPC_PHASE_315 0x0000000E |
| #define | ADC_SPC_PHASE_337_5 0x0000000F |
| #define | ADC_PSSI_GSYNC 0x80000000 |
| #define | ADC_PSSI_SYNCWAIT 0x08000000 |
| #define | ADC_PSSI_SS3 0x00000008 |
| #define | ADC_PSSI_SS2 0x00000004 |
| #define | ADC_PSSI_SS1 0x00000002 |
| #define | ADC_PSSI_SS0 0x00000001 |
| #define | ADC_SAC_AVG_M 0x00000007 |
| #define | ADC_SAC_AVG_OFF 0x00000000 |
| #define | ADC_SAC_AVG_2X 0x00000001 |
| #define | ADC_SAC_AVG_4X 0x00000002 |
| #define | ADC_SAC_AVG_8X 0x00000003 |
| #define | ADC_SAC_AVG_16X 0x00000004 |
| #define | ADC_SAC_AVG_32X 0x00000005 |
| #define | ADC_SAC_AVG_64X 0x00000006 |
| #define | ADC_DCISC_DCINT7 0x00000080 |
| #define | ADC_DCISC_DCINT6 0x00000040 |
| #define | ADC_DCISC_DCINT5 0x00000020 |
| #define | ADC_DCISC_DCINT4 0x00000010 |
| #define | ADC_DCISC_DCINT3 0x00000008 |
| #define | ADC_DCISC_DCINT2 0x00000004 |
| #define | ADC_DCISC_DCINT1 0x00000002 |
| #define | ADC_DCISC_DCINT0 0x00000001 |
| #define | ADC_CTL_VREF_M 0x00000001 |
| #define | ADC_CTL_VREF_INTERNAL 0x00000000 |
| #define | ADC_CTL_VREF_EXT_3V 0x00000001 |
| #define | ADC_SSMUX0_MUX7_M 0xF0000000 |
| #define | ADC_SSMUX0_MUX6_M 0x0F000000 |
| #define | ADC_SSMUX0_MUX5_M 0x00F00000 |
| #define | ADC_SSMUX0_MUX4_M 0x000F0000 |
| #define | ADC_SSMUX0_MUX3_M 0x0000F000 |
| #define | ADC_SSMUX0_MUX2_M 0x00000F00 |
| #define | ADC_SSMUX0_MUX1_M 0x000000F0 |
| #define | ADC_SSMUX0_MUX0_M 0x0000000F |
| #define | ADC_SSMUX0_MUX7_S 28 |
| #define | ADC_SSMUX0_MUX6_S 24 |
| #define | ADC_SSMUX0_MUX5_S 20 |
| #define | ADC_SSMUX0_MUX4_S 16 |
| #define | ADC_SSMUX0_MUX3_S 12 |
| #define | ADC_SSMUX0_MUX2_S 8 |
| #define | ADC_SSMUX0_MUX1_S 4 |
| #define | ADC_SSMUX0_MUX0_S 0 |
| #define | ADC_SSCTL0_TS7 0x80000000 |
| #define | ADC_SSCTL0_IE7 0x40000000 |
| #define | ADC_SSCTL0_END7 0x20000000 |
| #define | ADC_SSCTL0_D7 0x10000000 |
| #define | ADC_SSCTL0_TS6 0x08000000 |
| #define | ADC_SSCTL0_IE6 0x04000000 |
| #define | ADC_SSCTL0_END6 0x02000000 |
| #define | ADC_SSCTL0_D6 0x01000000 |
| #define | ADC_SSCTL0_TS5 0x00800000 |
| #define | ADC_SSCTL0_IE5 0x00400000 |
| #define | ADC_SSCTL0_END5 0x00200000 |
| #define | ADC_SSCTL0_D5 0x00100000 |
| #define | ADC_SSCTL0_TS4 0x00080000 |
| #define | ADC_SSCTL0_IE4 0x00040000 |
| #define | ADC_SSCTL0_END4 0x00020000 |
| #define | ADC_SSCTL0_D4 0x00010000 |
| #define | ADC_SSCTL0_TS3 0x00008000 |
| #define | ADC_SSCTL0_IE3 0x00004000 |
| #define | ADC_SSCTL0_END3 0x00002000 |
| #define | ADC_SSCTL0_D3 0x00001000 |
| #define | ADC_SSCTL0_TS2 0x00000800 |
| #define | ADC_SSCTL0_IE2 0x00000400 |
| #define | ADC_SSCTL0_END2 0x00000200 |
| #define | ADC_SSCTL0_D2 0x00000100 |
| #define | ADC_SSCTL0_TS1 0x00000080 |
| #define | ADC_SSCTL0_IE1 0x00000040 |
| #define | ADC_SSCTL0_END1 0x00000020 |
| #define | ADC_SSCTL0_D1 0x00000010 |
| #define | ADC_SSCTL0_TS0 0x00000008 |
| #define | ADC_SSCTL0_IE0 0x00000004 |
| #define | ADC_SSCTL0_END0 0x00000002 |
| #define | ADC_SSCTL0_D0 0x00000001 |
| #define | ADC_SSFIFO0_DATA_M 0x00000FFF |
| #define | ADC_SSFIFO0_DATA_S 0 |
| #define | ADC_SSFSTAT0_FULL 0x00001000 |
| #define | ADC_SSFSTAT0_EMPTY 0x00000100 |
| #define | ADC_SSFSTAT0_HPTR_M 0x000000F0 |
| #define | ADC_SSFSTAT0_TPTR_M 0x0000000F |
| #define | ADC_SSFSTAT0_HPTR_S 4 |
| #define | ADC_SSFSTAT0_TPTR_S 0 |
| #define | ADC_SSOP0_S7DCOP 0x10000000 |
| #define | ADC_SSOP0_S6DCOP 0x01000000 |
| #define | ADC_SSOP0_S5DCOP 0x00100000 |
| #define | ADC_SSOP0_S4DCOP 0x00010000 |
| #define | ADC_SSOP0_S3DCOP 0x00001000 |
| #define | ADC_SSOP0_S2DCOP 0x00000100 |
| #define | ADC_SSOP0_S1DCOP 0x00000010 |
| #define | ADC_SSOP0_S0DCOP 0x00000001 |
| #define | ADC_SSDC0_S7DCSEL_M 0xF0000000 |
| #define | ADC_SSDC0_S6DCSEL_M 0x0F000000 |
| #define | ADC_SSDC0_S5DCSEL_M 0x00F00000 |
| #define | ADC_SSDC0_S4DCSEL_M 0x000F0000 |
| #define | ADC_SSDC0_S3DCSEL_M 0x0000F000 |
| #define | ADC_SSDC0_S2DCSEL_M 0x00000F00 |
| #define | ADC_SSDC0_S1DCSEL_M 0x000000F0 |
| #define | ADC_SSDC0_S0DCSEL_M 0x0000000F |
| #define | ADC_SSDC0_S6DCSEL_S 24 |
| #define | ADC_SSDC0_S5DCSEL_S 20 |
| #define | ADC_SSDC0_S4DCSEL_S 16 |
| #define | ADC_SSDC0_S3DCSEL_S 12 |
| #define | ADC_SSDC0_S2DCSEL_S 8 |
| #define | ADC_SSDC0_S1DCSEL_S 4 |
| #define | ADC_SSDC0_S0DCSEL_S 0 |
| #define | ADC_SSEMUX0_EMUX7 0x10000000 |
| #define | ADC_SSEMUX0_EMUX6 0x01000000 |
| #define | ADC_SSEMUX0_EMUX5 0x00100000 |
| #define | ADC_SSEMUX0_EMUX4 0x00010000 |
| #define | ADC_SSEMUX0_EMUX3 0x00001000 |
| #define | ADC_SSEMUX0_EMUX2 0x00000100 |
| #define | ADC_SSEMUX0_EMUX1 0x00000010 |
| #define | ADC_SSEMUX0_EMUX0 0x00000001 |
| #define | ADC_SSMUX1_MUX3_M 0x0000F000 |
| #define | ADC_SSMUX1_MUX2_M 0x00000F00 |
| #define | ADC_SSMUX1_MUX1_M 0x000000F0 |
| #define | ADC_SSMUX1_MUX0_M 0x0000000F |
| #define | ADC_SSMUX1_MUX3_S 12 |
| #define | ADC_SSMUX1_MUX2_S 8 |
| #define | ADC_SSMUX1_MUX1_S 4 |
| #define | ADC_SSMUX1_MUX0_S 0 |
| #define | ADC_SSCTL1_TS3 0x00008000 |
| #define | ADC_SSCTL1_IE3 0x00004000 |
| #define | ADC_SSCTL1_END3 0x00002000 |
| #define | ADC_SSCTL1_D3 0x00001000 |
| #define | ADC_SSCTL1_TS2 0x00000800 |
| #define | ADC_SSCTL1_IE2 0x00000400 |
| #define | ADC_SSCTL1_END2 0x00000200 |
| #define | ADC_SSCTL1_D2 0x00000100 |
| #define | ADC_SSCTL1_TS1 0x00000080 |
| #define | ADC_SSCTL1_IE1 0x00000040 |
| #define | ADC_SSCTL1_END1 0x00000020 |
| #define | ADC_SSCTL1_D1 0x00000010 |
| #define | ADC_SSCTL1_TS0 0x00000008 |
| #define | ADC_SSCTL1_IE0 0x00000004 |
| #define | ADC_SSCTL1_END0 0x00000002 |
| #define | ADC_SSCTL1_D0 0x00000001 |
| #define | ADC_SSFIFO1_DATA_M 0x00000FFF |
| #define | ADC_SSFIFO1_DATA_S 0 |
| #define | ADC_SSFSTAT1_FULL 0x00001000 |
| #define | ADC_SSFSTAT1_EMPTY 0x00000100 |
| #define | ADC_SSFSTAT1_HPTR_M 0x000000F0 |
| #define | ADC_SSFSTAT1_TPTR_M 0x0000000F |
| #define | ADC_SSFSTAT1_HPTR_S 4 |
| #define | ADC_SSFSTAT1_TPTR_S 0 |
| #define | ADC_SSOP1_S3DCOP 0x00001000 |
| #define | ADC_SSOP1_S2DCOP 0x00000100 |
| #define | ADC_SSOP1_S1DCOP 0x00000010 |
| #define | ADC_SSOP1_S0DCOP 0x00000001 |
| #define | ADC_SSDC1_S3DCSEL_M 0x0000F000 |
| #define | ADC_SSDC1_S2DCSEL_M 0x00000F00 |
| #define | ADC_SSDC1_S1DCSEL_M 0x000000F0 |
| #define | ADC_SSDC1_S0DCSEL_M 0x0000000F |
| #define | ADC_SSDC1_S2DCSEL_S 8 |
| #define | ADC_SSDC1_S1DCSEL_S 4 |
| #define | ADC_SSDC1_S0DCSEL_S 0 |
| #define | ADC_SSEMUX1_EMUX3 0x00001000 |
| #define | ADC_SSEMUX1_EMUX2 0x00000100 |
| #define | ADC_SSEMUX1_EMUX1 0x00000010 |
| #define | ADC_SSEMUX1_EMUX0 0x00000001 |
| #define | ADC_SSMUX2_MUX3_M 0x0000F000 |
| #define | ADC_SSMUX2_MUX2_M 0x00000F00 |
| #define | ADC_SSMUX2_MUX1_M 0x000000F0 |
| #define | ADC_SSMUX2_MUX0_M 0x0000000F |
| #define | ADC_SSMUX2_MUX3_S 12 |
| #define | ADC_SSMUX2_MUX2_S 8 |
| #define | ADC_SSMUX2_MUX1_S 4 |
| #define | ADC_SSMUX2_MUX0_S 0 |
| #define | ADC_SSCTL2_TS3 0x00008000 |
| #define | ADC_SSCTL2_IE3 0x00004000 |
| #define | ADC_SSCTL2_END3 0x00002000 |
| #define | ADC_SSCTL2_D3 0x00001000 |
| #define | ADC_SSCTL2_TS2 0x00000800 |
| #define | ADC_SSCTL2_IE2 0x00000400 |
| #define | ADC_SSCTL2_END2 0x00000200 |
| #define | ADC_SSCTL2_D2 0x00000100 |
| #define | ADC_SSCTL2_TS1 0x00000080 |
| #define | ADC_SSCTL2_IE1 0x00000040 |
| #define | ADC_SSCTL2_END1 0x00000020 |
| #define | ADC_SSCTL2_D1 0x00000010 |
| #define | ADC_SSCTL2_TS0 0x00000008 |
| #define | ADC_SSCTL2_IE0 0x00000004 |
| #define | ADC_SSCTL2_END0 0x00000002 |
| #define | ADC_SSCTL2_D0 0x00000001 |
| #define | ADC_SSFIFO2_DATA_M 0x00000FFF |
| #define | ADC_SSFIFO2_DATA_S 0 |
| #define | ADC_SSFSTAT2_FULL 0x00001000 |
| #define | ADC_SSFSTAT2_EMPTY 0x00000100 |
| #define | ADC_SSFSTAT2_HPTR_M 0x000000F0 |
| #define | ADC_SSFSTAT2_TPTR_M 0x0000000F |
| #define | ADC_SSFSTAT2_HPTR_S 4 |
| #define | ADC_SSFSTAT2_TPTR_S 0 |
| #define | ADC_SSOP2_S3DCOP 0x00001000 |
| #define | ADC_SSOP2_S2DCOP 0x00000100 |
| #define | ADC_SSOP2_S1DCOP 0x00000010 |
| #define | ADC_SSOP2_S0DCOP 0x00000001 |
| #define | ADC_SSDC2_S3DCSEL_M 0x0000F000 |
| #define | ADC_SSDC2_S2DCSEL_M 0x00000F00 |
| #define | ADC_SSDC2_S1DCSEL_M 0x000000F0 |
| #define | ADC_SSDC2_S0DCSEL_M 0x0000000F |
| #define | ADC_SSDC2_S2DCSEL_S 8 |
| #define | ADC_SSDC2_S1DCSEL_S 4 |
| #define | ADC_SSDC2_S0DCSEL_S 0 |
| #define | ADC_SSEMUX2_EMUX3 0x00001000 |
| #define | ADC_SSEMUX2_EMUX2 0x00000100 |
| #define | ADC_SSEMUX2_EMUX1 0x00000010 |
| #define | ADC_SSEMUX2_EMUX0 0x00000001 |
| #define | ADC_SSMUX3_MUX0_M 0x0000000F |
| #define | ADC_SSMUX3_MUX0_S 0 |
| #define | ADC_SSCTL3_TS0 0x00000008 |
| #define | ADC_SSCTL3_IE0 0x00000004 |
| #define | ADC_SSCTL3_END0 0x00000002 |
| #define | ADC_SSCTL3_D0 0x00000001 |
| #define | ADC_SSFIFO3_DATA_M 0x00000FFF |
| #define | ADC_SSFIFO3_DATA_S 0 |
| #define | ADC_SSFSTAT3_FULL 0x00001000 |
| #define | ADC_SSFSTAT3_EMPTY 0x00000100 |
| #define | ADC_SSFSTAT3_HPTR_M 0x000000F0 |
| #define | ADC_SSFSTAT3_TPTR_M 0x0000000F |
| #define | ADC_SSFSTAT3_HPTR_S 4 |
| #define | ADC_SSFSTAT3_TPTR_S 0 |
| #define | ADC_SSOP3_S0DCOP 0x00000001 |
| #define | ADC_SSDC3_S0DCSEL_M 0x0000000F |
| #define | ADC_SSEMUX3_EMUX0 0x00000001 |
| #define | ADC_DCRIC_DCTRIG7 0x00800000 |
| #define | ADC_DCRIC_DCTRIG6 0x00400000 |
| #define | ADC_DCRIC_DCTRIG5 0x00200000 |
| #define | ADC_DCRIC_DCTRIG4 0x00100000 |
| #define | ADC_DCRIC_DCTRIG3 0x00080000 |
| #define | ADC_DCRIC_DCTRIG2 0x00040000 |
| #define | ADC_DCRIC_DCTRIG1 0x00020000 |
| #define | ADC_DCRIC_DCTRIG0 0x00010000 |
| #define | ADC_DCRIC_DCINT7 0x00000080 |
| #define | ADC_DCRIC_DCINT6 0x00000040 |
| #define | ADC_DCRIC_DCINT5 0x00000020 |
| #define | ADC_DCRIC_DCINT4 0x00000010 |
| #define | ADC_DCRIC_DCINT3 0x00000008 |
| #define | ADC_DCRIC_DCINT2 0x00000004 |
| #define | ADC_DCRIC_DCINT1 0x00000002 |
| #define | ADC_DCRIC_DCINT0 0x00000001 |
| #define | ADC_DCCTL0_CTE 0x00001000 |
| #define | ADC_DCCTL0_CTC_M 0x00000C00 |
| #define | ADC_DCCTL0_CTC_LOW 0x00000000 |
| #define | ADC_DCCTL0_CTC_MID 0x00000400 |
| #define | ADC_DCCTL0_CTC_HIGH 0x00000C00 |
| #define | ADC_DCCTL0_CTM_M 0x00000300 |
| #define | ADC_DCCTL0_CTM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL0_CTM_ONCE 0x00000100 |
| #define | ADC_DCCTL0_CTM_HALWAYS 0x00000200 |
| #define | ADC_DCCTL0_CTM_HONCE 0x00000300 |
| #define | ADC_DCCTL0_CIE 0x00000010 |
| #define | ADC_DCCTL0_CIC_M 0x0000000C |
| #define | ADC_DCCTL0_CIC_LOW 0x00000000 |
| #define | ADC_DCCTL0_CIC_MID 0x00000004 |
| #define | ADC_DCCTL0_CIC_HIGH 0x0000000C |
| #define | ADC_DCCTL0_CIM_M 0x00000003 |
| #define | ADC_DCCTL0_CIM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL0_CIM_ONCE 0x00000001 |
| #define | ADC_DCCTL0_CIM_HALWAYS 0x00000002 |
| #define | ADC_DCCTL0_CIM_HONCE 0x00000003 |
| #define | ADC_DCCTL1_CTE 0x00001000 |
| #define | ADC_DCCTL1_CTC_M 0x00000C00 |
| #define | ADC_DCCTL1_CTC_LOW 0x00000000 |
| #define | ADC_DCCTL1_CTC_MID 0x00000400 |
| #define | ADC_DCCTL1_CTC_HIGH 0x00000C00 |
| #define | ADC_DCCTL1_CTM_M 0x00000300 |
| #define | ADC_DCCTL1_CTM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL1_CTM_ONCE 0x00000100 |
| #define | ADC_DCCTL1_CTM_HALWAYS 0x00000200 |
| #define | ADC_DCCTL1_CTM_HONCE 0x00000300 |
| #define | ADC_DCCTL1_CIE 0x00000010 |
| #define | ADC_DCCTL1_CIC_M 0x0000000C |
| #define | ADC_DCCTL1_CIC_LOW 0x00000000 |
| #define | ADC_DCCTL1_CIC_MID 0x00000004 |
| #define | ADC_DCCTL1_CIC_HIGH 0x0000000C |
| #define | ADC_DCCTL1_CIM_M 0x00000003 |
| #define | ADC_DCCTL1_CIM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL1_CIM_ONCE 0x00000001 |
| #define | ADC_DCCTL1_CIM_HALWAYS 0x00000002 |
| #define | ADC_DCCTL1_CIM_HONCE 0x00000003 |
| #define | ADC_DCCTL2_CTE 0x00001000 |
| #define | ADC_DCCTL2_CTC_M 0x00000C00 |
| #define | ADC_DCCTL2_CTC_LOW 0x00000000 |
| #define | ADC_DCCTL2_CTC_MID 0x00000400 |
| #define | ADC_DCCTL2_CTC_HIGH 0x00000C00 |
| #define | ADC_DCCTL2_CTM_M 0x00000300 |
| #define | ADC_DCCTL2_CTM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL2_CTM_ONCE 0x00000100 |
| #define | ADC_DCCTL2_CTM_HALWAYS 0x00000200 |
| #define | ADC_DCCTL2_CTM_HONCE 0x00000300 |
| #define | ADC_DCCTL2_CIE 0x00000010 |
| #define | ADC_DCCTL2_CIC_M 0x0000000C |
| #define | ADC_DCCTL2_CIC_LOW 0x00000000 |
| #define | ADC_DCCTL2_CIC_MID 0x00000004 |
| #define | ADC_DCCTL2_CIC_HIGH 0x0000000C |
| #define | ADC_DCCTL2_CIM_M 0x00000003 |
| #define | ADC_DCCTL2_CIM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL2_CIM_ONCE 0x00000001 |
| #define | ADC_DCCTL2_CIM_HALWAYS 0x00000002 |
| #define | ADC_DCCTL2_CIM_HONCE 0x00000003 |
| #define | ADC_DCCTL3_CTE 0x00001000 |
| #define | ADC_DCCTL3_CTC_M 0x00000C00 |
| #define | ADC_DCCTL3_CTC_LOW 0x00000000 |
| #define | ADC_DCCTL3_CTC_MID 0x00000400 |
| #define | ADC_DCCTL3_CTC_HIGH 0x00000C00 |
| #define | ADC_DCCTL3_CTM_M 0x00000300 |
| #define | ADC_DCCTL3_CTM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL3_CTM_ONCE 0x00000100 |
| #define | ADC_DCCTL3_CTM_HALWAYS 0x00000200 |
| #define | ADC_DCCTL3_CTM_HONCE 0x00000300 |
| #define | ADC_DCCTL3_CIE 0x00000010 |
| #define | ADC_DCCTL3_CIC_M 0x0000000C |
| #define | ADC_DCCTL3_CIC_LOW 0x00000000 |
| #define | ADC_DCCTL3_CIC_MID 0x00000004 |
| #define | ADC_DCCTL3_CIC_HIGH 0x0000000C |
| #define | ADC_DCCTL3_CIM_M 0x00000003 |
| #define | ADC_DCCTL3_CIM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL3_CIM_ONCE 0x00000001 |
| #define | ADC_DCCTL3_CIM_HALWAYS 0x00000002 |
| #define | ADC_DCCTL3_CIM_HONCE 0x00000003 |
| #define | ADC_DCCTL4_CTE 0x00001000 |
| #define | ADC_DCCTL4_CTC_M 0x00000C00 |
| #define | ADC_DCCTL4_CTC_LOW 0x00000000 |
| #define | ADC_DCCTL4_CTC_MID 0x00000400 |
| #define | ADC_DCCTL4_CTC_HIGH 0x00000C00 |
| #define | ADC_DCCTL4_CTM_M 0x00000300 |
| #define | ADC_DCCTL4_CTM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL4_CTM_ONCE 0x00000100 |
| #define | ADC_DCCTL4_CTM_HALWAYS 0x00000200 |
| #define | ADC_DCCTL4_CTM_HONCE 0x00000300 |
| #define | ADC_DCCTL4_CIE 0x00000010 |
| #define | ADC_DCCTL4_CIC_M 0x0000000C |
| #define | ADC_DCCTL4_CIC_LOW 0x00000000 |
| #define | ADC_DCCTL4_CIC_MID 0x00000004 |
| #define | ADC_DCCTL4_CIC_HIGH 0x0000000C |
| #define | ADC_DCCTL4_CIM_M 0x00000003 |
| #define | ADC_DCCTL4_CIM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL4_CIM_ONCE 0x00000001 |
| #define | ADC_DCCTL4_CIM_HALWAYS 0x00000002 |
| #define | ADC_DCCTL4_CIM_HONCE 0x00000003 |
| #define | ADC_DCCTL5_CTE 0x00001000 |
| #define | ADC_DCCTL5_CTC_M 0x00000C00 |
| #define | ADC_DCCTL5_CTC_LOW 0x00000000 |
| #define | ADC_DCCTL5_CTC_MID 0x00000400 |
| #define | ADC_DCCTL5_CTC_HIGH 0x00000C00 |
| #define | ADC_DCCTL5_CTM_M 0x00000300 |
| #define | ADC_DCCTL5_CTM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL5_CTM_ONCE 0x00000100 |
| #define | ADC_DCCTL5_CTM_HALWAYS 0x00000200 |
| #define | ADC_DCCTL5_CTM_HONCE 0x00000300 |
| #define | ADC_DCCTL5_CIE 0x00000010 |
| #define | ADC_DCCTL5_CIC_M 0x0000000C |
| #define | ADC_DCCTL5_CIC_LOW 0x00000000 |
| #define | ADC_DCCTL5_CIC_MID 0x00000004 |
| #define | ADC_DCCTL5_CIC_HIGH 0x0000000C |
| #define | ADC_DCCTL5_CIM_M 0x00000003 |
| #define | ADC_DCCTL5_CIM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL5_CIM_ONCE 0x00000001 |
| #define | ADC_DCCTL5_CIM_HALWAYS 0x00000002 |
| #define | ADC_DCCTL5_CIM_HONCE 0x00000003 |
| #define | ADC_DCCTL6_CTE 0x00001000 |
| #define | ADC_DCCTL6_CTC_M 0x00000C00 |
| #define | ADC_DCCTL6_CTC_LOW 0x00000000 |
| #define | ADC_DCCTL6_CTC_MID 0x00000400 |
| #define | ADC_DCCTL6_CTC_HIGH 0x00000C00 |
| #define | ADC_DCCTL6_CTM_M 0x00000300 |
| #define | ADC_DCCTL6_CTM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL6_CTM_ONCE 0x00000100 |
| #define | ADC_DCCTL6_CTM_HALWAYS 0x00000200 |
| #define | ADC_DCCTL6_CTM_HONCE 0x00000300 |
| #define | ADC_DCCTL6_CIE 0x00000010 |
| #define | ADC_DCCTL6_CIC_M 0x0000000C |
| #define | ADC_DCCTL6_CIC_LOW 0x00000000 |
| #define | ADC_DCCTL6_CIC_MID 0x00000004 |
| #define | ADC_DCCTL6_CIC_HIGH 0x0000000C |
| #define | ADC_DCCTL6_CIM_M 0x00000003 |
| #define | ADC_DCCTL6_CIM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL6_CIM_ONCE 0x00000001 |
| #define | ADC_DCCTL6_CIM_HALWAYS 0x00000002 |
| #define | ADC_DCCTL6_CIM_HONCE 0x00000003 |
| #define | ADC_DCCTL7_CTE 0x00001000 |
| #define | ADC_DCCTL7_CTC_M 0x00000C00 |
| #define | ADC_DCCTL7_CTC_LOW 0x00000000 |
| #define | ADC_DCCTL7_CTC_MID 0x00000400 |
| #define | ADC_DCCTL7_CTC_HIGH 0x00000C00 |
| #define | ADC_DCCTL7_CTM_M 0x00000300 |
| #define | ADC_DCCTL7_CTM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL7_CTM_ONCE 0x00000100 |
| #define | ADC_DCCTL7_CTM_HALWAYS 0x00000200 |
| #define | ADC_DCCTL7_CTM_HONCE 0x00000300 |
| #define | ADC_DCCTL7_CIE 0x00000010 |
| #define | ADC_DCCTL7_CIC_M 0x0000000C |
| #define | ADC_DCCTL7_CIC_LOW 0x00000000 |
| #define | ADC_DCCTL7_CIC_MID 0x00000004 |
| #define | ADC_DCCTL7_CIC_HIGH 0x0000000C |
| #define | ADC_DCCTL7_CIM_M 0x00000003 |
| #define | ADC_DCCTL7_CIM_ALWAYS 0x00000000 |
| #define | ADC_DCCTL7_CIM_ONCE 0x00000001 |
| #define | ADC_DCCTL7_CIM_HALWAYS 0x00000002 |
| #define | ADC_DCCTL7_CIM_HONCE 0x00000003 |
| #define | ADC_DCCMP0_COMP1_M 0x0FFF0000 |
| #define | ADC_DCCMP0_COMP0_M 0x00000FFF |
| #define | ADC_DCCMP0_COMP1_S 16 |
| #define | ADC_DCCMP0_COMP0_S 0 |
| #define | ADC_DCCMP1_COMP1_M 0x0FFF0000 |
| #define | ADC_DCCMP1_COMP0_M 0x00000FFF |
| #define | ADC_DCCMP1_COMP1_S 16 |
| #define | ADC_DCCMP1_COMP0_S 0 |
| #define | ADC_DCCMP2_COMP1_M 0x0FFF0000 |
| #define | ADC_DCCMP2_COMP0_M 0x00000FFF |
| #define | ADC_DCCMP2_COMP1_S 16 |
| #define | ADC_DCCMP2_COMP0_S 0 |
| #define | ADC_DCCMP3_COMP1_M 0x0FFF0000 |
| #define | ADC_DCCMP3_COMP0_M 0x00000FFF |
| #define | ADC_DCCMP3_COMP1_S 16 |
| #define | ADC_DCCMP3_COMP0_S 0 |
| #define | ADC_DCCMP4_COMP1_M 0x0FFF0000 |
| #define | ADC_DCCMP4_COMP0_M 0x00000FFF |
| #define | ADC_DCCMP4_COMP1_S 16 |
| #define | ADC_DCCMP4_COMP0_S 0 |
| #define | ADC_DCCMP5_COMP1_M 0x0FFF0000 |
| #define | ADC_DCCMP5_COMP0_M 0x00000FFF |
| #define | ADC_DCCMP5_COMP1_S 16 |
| #define | ADC_DCCMP5_COMP0_S 0 |
| #define | ADC_DCCMP6_COMP1_M 0x0FFF0000 |
| #define | ADC_DCCMP6_COMP0_M 0x00000FFF |
| #define | ADC_DCCMP6_COMP1_S 16 |
| #define | ADC_DCCMP6_COMP0_S 0 |
| #define | ADC_DCCMP7_COMP1_M 0x0FFF0000 |
| #define | ADC_DCCMP7_COMP0_M 0x00000FFF |
| #define | ADC_DCCMP7_COMP1_S 16 |
| #define | ADC_DCCMP7_COMP0_S 0 |
| #define | ADC_PP_TS 0x00800000 |
| #define | ADC_PP_RSL_M 0x007C0000 |
| #define | ADC_PP_TYPE_M 0x00030000 |
| #define | ADC_PP_TYPE_SAR 0x00000000 |
| #define | ADC_PP_DC_M 0x0000FC00 |
| #define | ADC_PP_CH_M 0x000003F0 |
| #define | ADC_PP_MSR_M 0x0000000F |
| #define | ADC_PP_MSR_125K 0x00000001 |
| #define | ADC_PP_MSR_250K 0x00000003 |
| #define | ADC_PP_MSR_500K 0x00000005 |
| #define | ADC_PP_MSR_1M 0x00000007 |
| #define | ADC_PP_RSL_S 18 |
| #define | ADC_PP_DC_S 10 |
| #define | ADC_PP_CH_S 4 |
| #define | ADC_PC_SR_M 0x0000000F |
| #define | ADC_PC_SR_125K 0x00000001 |
| #define | ADC_PC_SR_250K 0x00000003 |
| #define | ADC_PC_SR_500K 0x00000005 |
| #define | ADC_PC_SR_1M 0x00000007 |
| #define | ADC_CC_CS_M 0x0000000F |
| #define | ADC_CC_CS_SYSPLL 0x00000000 |
| #define | ADC_CC_CS_PIOSC 0x00000001 |
| #define | COMP_ACMIS_IN2 0x00000004 |
| #define | COMP_ACMIS_IN1 0x00000002 |
| #define | COMP_ACMIS_IN0 0x00000001 |
| #define | COMP_ACRIS_IN2 0x00000004 |
| #define | COMP_ACRIS_IN1 0x00000002 |
| #define | COMP_ACRIS_IN0 0x00000001 |
| #define | COMP_ACINTEN_IN2 0x00000004 |
| #define | COMP_ACINTEN_IN1 0x00000002 |
| #define | COMP_ACINTEN_IN0 0x00000001 |
| #define | COMP_ACREFCTL_EN 0x00000200 |
| #define | COMP_ACREFCTL_RNG 0x00000100 |
| #define | COMP_ACREFCTL_VREF_M 0x0000000F |
| #define | COMP_ACREFCTL_VREF_S 0 |
| #define | COMP_ACSTAT0_OVAL 0x00000002 |
| #define | COMP_ACCTL0_TOEN 0x00000800 |
| #define | COMP_ACCTL0_ASRCP_M 0x00000600 |
| #define | COMP_ACCTL0_ASRCP_PIN 0x00000000 |
| #define | COMP_ACCTL0_ASRCP_PIN0 0x00000200 |
| #define | COMP_ACCTL0_ASRCP_REF 0x00000400 |
| #define | COMP_ACCTL0_TSLVAL 0x00000080 |
| #define | COMP_ACCTL0_TSEN_M 0x00000060 |
| #define | COMP_ACCTL0_TSEN_LEVEL 0x00000000 |
| #define | COMP_ACCTL0_TSEN_FALL 0x00000020 |
| #define | COMP_ACCTL0_TSEN_RISE 0x00000040 |
| #define | COMP_ACCTL0_TSEN_BOTH 0x00000060 |
| #define | COMP_ACCTL0_ISLVAL 0x00000010 |
| #define | COMP_ACCTL0_ISEN_M 0x0000000C |
| #define | COMP_ACCTL0_ISEN_LEVEL 0x00000000 |
| #define | COMP_ACCTL0_ISEN_FALL 0x00000004 |
| #define | COMP_ACCTL0_ISEN_RISE 0x00000008 |
| #define | COMP_ACCTL0_ISEN_BOTH 0x0000000C |
| #define | COMP_ACCTL0_CINV 0x00000002 |
| #define | COMP_ACSTAT1_OVAL 0x00000002 |
| #define | COMP_ACCTL1_TOEN 0x00000800 |
| #define | COMP_ACCTL1_ASRCP_M 0x00000600 |
| #define | COMP_ACCTL1_ASRCP_PIN 0x00000000 |
| #define | COMP_ACCTL1_ASRCP_PIN0 0x00000200 |
| #define | COMP_ACCTL1_ASRCP_REF 0x00000400 |
| #define | COMP_ACCTL1_TSLVAL 0x00000080 |
| #define | COMP_ACCTL1_TSEN_M 0x00000060 |
| #define | COMP_ACCTL1_TSEN_LEVEL 0x00000000 |
| #define | COMP_ACCTL1_TSEN_FALL 0x00000020 |
| #define | COMP_ACCTL1_TSEN_RISE 0x00000040 |
| #define | COMP_ACCTL1_TSEN_BOTH 0x00000060 |
| #define | COMP_ACCTL1_ISLVAL 0x00000010 |
| #define | COMP_ACCTL1_ISEN_M 0x0000000C |
| #define | COMP_ACCTL1_ISEN_LEVEL 0x00000000 |
| #define | COMP_ACCTL1_ISEN_FALL 0x00000004 |
| #define | COMP_ACCTL1_ISEN_RISE 0x00000008 |
| #define | COMP_ACCTL1_ISEN_BOTH 0x0000000C |
| #define | COMP_ACCTL1_CINV 0x00000002 |
| #define | COMP_ACSTAT2_OVAL 0x00000002 |
| #define | COMP_ACCTL2_TOEN 0x00000800 |
| #define | COMP_ACCTL2_ASRCP_M 0x00000600 |
| #define | COMP_ACCTL2_ASRCP_PIN 0x00000000 |
| #define | COMP_ACCTL2_ASRCP_PIN0 0x00000200 |
| #define | COMP_ACCTL2_ASRCP_REF 0x00000400 |
| #define | COMP_ACCTL2_TSLVAL 0x00000080 |
| #define | COMP_ACCTL2_TSEN_M 0x00000060 |
| #define | COMP_ACCTL2_TSEN_LEVEL 0x00000000 |
| #define | COMP_ACCTL2_TSEN_FALL 0x00000020 |
| #define | COMP_ACCTL2_TSEN_RISE 0x00000040 |
| #define | COMP_ACCTL2_TSEN_BOTH 0x00000060 |
| #define | COMP_ACCTL2_ISLVAL 0x00000010 |
| #define | COMP_ACCTL2_ISEN_M 0x0000000C |
| #define | COMP_ACCTL2_ISEN_LEVEL 0x00000000 |
| #define | COMP_ACCTL2_ISEN_FALL 0x00000004 |
| #define | COMP_ACCTL2_ISEN_RISE 0x00000008 |
| #define | COMP_ACCTL2_ISEN_BOTH 0x0000000C |
| #define | COMP_ACCTL2_CINV 0x00000002 |
| #define | COMP_PP_C2O 0x00040000 |
| #define | COMP_PP_C1O 0x00020000 |
| #define | COMP_PP_C0O 0x00010000 |
| #define | COMP_PP_CMP2 0x00000004 |
| #define | COMP_PP_CMP1 0x00000002 |
| #define | COMP_PP_CMP0 0x00000001 |
| #define | CAN_CTL_TEST 0x00000080 |
| #define | CAN_CTL_CCE 0x00000040 |
| #define | CAN_CTL_DAR 0x00000020 |
| #define | CAN_CTL_EIE 0x00000008 |
| #define | CAN_CTL_SIE 0x00000004 |
| #define | CAN_CTL_IE 0x00000002 |
| #define | CAN_CTL_INIT 0x00000001 |
| #define | CAN_STS_BOFF 0x00000080 |
| #define | CAN_STS_EWARN 0x00000040 |
| #define | CAN_STS_EPASS 0x00000020 |
| #define | CAN_STS_RXOK 0x00000010 |
| #define | CAN_STS_TXOK 0x00000008 |
| #define | CAN_STS_LEC_M 0x00000007 |
| #define | CAN_STS_LEC_NONE 0x00000000 |
| #define | CAN_STS_LEC_STUFF 0x00000001 |
| #define | CAN_STS_LEC_FORM 0x00000002 |
| #define | CAN_STS_LEC_ACK 0x00000003 |
| #define | CAN_STS_LEC_BIT1 0x00000004 |
| #define | CAN_STS_LEC_BIT0 0x00000005 |
| #define | CAN_STS_LEC_CRC 0x00000006 |
| #define | CAN_STS_LEC_NOEVENT 0x00000007 |
| #define | CAN_ERR_RP 0x00008000 |
| #define | CAN_ERR_REC_M 0x00007F00 |
| #define | CAN_ERR_TEC_M 0x000000FF |
| #define | CAN_ERR_REC_S 8 |
| #define | CAN_ERR_TEC_S 0 |
| #define | CAN_BIT_TSEG2_M 0x00007000 |
| #define | CAN_BIT_TSEG1_M 0x00000F00 |
| #define | CAN_BIT_SJW_M 0x000000C0 |
| #define | CAN_BIT_BRP_M 0x0000003F |
| #define | CAN_BIT_TSEG2_S 12 |
| #define | CAN_BIT_TSEG1_S 8 |
| #define | CAN_BIT_SJW_S 6 |
| #define | CAN_BIT_BRP_S 0 |
| #define | CAN_INT_INTID_M 0x0000FFFF |
| #define | CAN_INT_INTID_NONE 0x00000000 |
| #define | CAN_INT_INTID_STATUS 0x00008000 |
| #define | CAN_TST_RX 0x00000080 |
| #define | CAN_TST_TX_M 0x00000060 |
| #define | CAN_TST_TX_CANCTL 0x00000000 |
| #define | CAN_TST_TX_SAMPLE 0x00000020 |
| #define | CAN_TST_TX_DOMINANT 0x00000040 |
| #define | CAN_TST_TX_RECESSIVE 0x00000060 |
| #define | CAN_TST_LBACK 0x00000010 |
| #define | CAN_TST_SILENT 0x00000008 |
| #define | CAN_TST_BASIC 0x00000004 |
| #define | CAN_BRPE_BRPE_M 0x0000000F |
| #define | CAN_BRPE_BRPE_S 0 |
| #define | CAN_IF1CRQ_BUSY 0x00008000 |
| #define | CAN_IF1CRQ_MNUM_M 0x0000003F |
| #define | CAN_IF1CRQ_MNUM_S 0 |
| #define | CAN_IF1CMSK_WRNRD 0x00000080 |
| #define | CAN_IF1CMSK_MASK 0x00000040 |
| #define | CAN_IF1CMSK_ARB 0x00000020 |
| #define | CAN_IF1CMSK_CONTROL 0x00000010 |
| #define | CAN_IF1CMSK_CLRINTPND 0x00000008 |
| #define | CAN_IF1CMSK_NEWDAT 0x00000004 |
| #define | CAN_IF1CMSK_TXRQST 0x00000004 |
| #define | CAN_IF1CMSK_DATAA 0x00000002 |
| #define | CAN_IF1CMSK_DATAB 0x00000001 |
| #define | CAN_IF1MSK1_IDMSK_M 0x0000FFFF |
| #define | CAN_IF1MSK1_IDMSK_S 0 |
| #define | CAN_IF1MSK2_MXTD 0x00008000 |
| #define | CAN_IF1MSK2_MDIR 0x00004000 |
| #define | CAN_IF1MSK2_IDMSK_M 0x00001FFF |
| #define | CAN_IF1MSK2_IDMSK_S 0 |
| #define | CAN_IF1ARB1_ID_M 0x0000FFFF |
| #define | CAN_IF1ARB1_ID_S 0 |
| #define | CAN_IF1ARB2_MSGVAL 0x00008000 |
| #define | CAN_IF1ARB2_XTD 0x00004000 |
| #define | CAN_IF1ARB2_DIR 0x00002000 |
| #define | CAN_IF1ARB2_ID_M 0x00001FFF |
| #define | CAN_IF1ARB2_ID_S 0 |
| #define | CAN_IF1MCTL_NEWDAT 0x00008000 |
| #define | CAN_IF1MCTL_MSGLST 0x00004000 |
| #define | CAN_IF1MCTL_INTPND 0x00002000 |
| #define | CAN_IF1MCTL_UMASK 0x00001000 |
| #define | CAN_IF1MCTL_TXIE 0x00000800 |
| #define | CAN_IF1MCTL_RXIE 0x00000400 |
| #define | CAN_IF1MCTL_RMTEN 0x00000200 |
| #define | CAN_IF1MCTL_TXRQST 0x00000100 |
| #define | CAN_IF1MCTL_EOB 0x00000080 |
| #define | CAN_IF1MCTL_DLC_M 0x0000000F |
| #define | CAN_IF1MCTL_DLC_S 0 |
| #define | CAN_IF1DA1_DATA_M 0x0000FFFF |
| #define | CAN_IF1DA1_DATA_S 0 |
| #define | CAN_IF1DA2_DATA_M 0x0000FFFF |
| #define | CAN_IF1DA2_DATA_S 0 |
| #define | CAN_IF1DB1_DATA_M 0x0000FFFF |
| #define | CAN_IF1DB1_DATA_S 0 |
| #define | CAN_IF1DB2_DATA_M 0x0000FFFF |
| #define | CAN_IF1DB2_DATA_S 0 |
| #define | CAN_IF2CRQ_BUSY 0x00008000 |
| #define | CAN_IF2CRQ_MNUM_M 0x0000003F |
| #define | CAN_IF2CRQ_MNUM_S 0 |
| #define | CAN_IF2CMSK_WRNRD 0x00000080 |
| #define | CAN_IF2CMSK_MASK 0x00000040 |
| #define | CAN_IF2CMSK_ARB 0x00000020 |
| #define | CAN_IF2CMSK_CONTROL 0x00000010 |
| #define | CAN_IF2CMSK_CLRINTPND 0x00000008 |
| #define | CAN_IF2CMSK_NEWDAT 0x00000004 |
| #define | CAN_IF2CMSK_TXRQST 0x00000004 |
| #define | CAN_IF2CMSK_DATAA 0x00000002 |
| #define | CAN_IF2CMSK_DATAB 0x00000001 |
| #define | CAN_IF2MSK1_IDMSK_M 0x0000FFFF |
| #define | CAN_IF2MSK1_IDMSK_S 0 |
| #define | CAN_IF2MSK2_MXTD 0x00008000 |
| #define | CAN_IF2MSK2_MDIR 0x00004000 |
| #define | CAN_IF2MSK2_IDMSK_M 0x00001FFF |
| #define | CAN_IF2MSK2_IDMSK_S 0 |
| #define | CAN_IF2ARB1_ID_M 0x0000FFFF |
| #define | CAN_IF2ARB1_ID_S 0 |
| #define | CAN_IF2ARB2_MSGVAL 0x00008000 |
| #define | CAN_IF2ARB2_XTD 0x00004000 |
| #define | CAN_IF2ARB2_DIR 0x00002000 |
| #define | CAN_IF2ARB2_ID_M 0x00001FFF |
| #define | CAN_IF2ARB2_ID_S 0 |
| #define | CAN_IF2MCTL_NEWDAT 0x00008000 |
| #define | CAN_IF2MCTL_MSGLST 0x00004000 |
| #define | CAN_IF2MCTL_INTPND 0x00002000 |
| #define | CAN_IF2MCTL_UMASK 0x00001000 |
| #define | CAN_IF2MCTL_TXIE 0x00000800 |
| #define | CAN_IF2MCTL_RXIE 0x00000400 |
| #define | CAN_IF2MCTL_RMTEN 0x00000200 |
| #define | CAN_IF2MCTL_TXRQST 0x00000100 |
| #define | CAN_IF2MCTL_EOB 0x00000080 |
| #define | CAN_IF2MCTL_DLC_M 0x0000000F |
| #define | CAN_IF2MCTL_DLC_S 0 |
| #define | CAN_IF2DA1_DATA_M 0x0000FFFF |
| #define | CAN_IF2DA1_DATA_S 0 |
| #define | CAN_IF2DA2_DATA_M 0x0000FFFF |
| #define | CAN_IF2DA2_DATA_S 0 |
| #define | CAN_IF2DB1_DATA_M 0x0000FFFF |
| #define | CAN_IF2DB1_DATA_S 0 |
| #define | CAN_IF2DB2_DATA_M 0x0000FFFF |
| #define | CAN_IF2DB2_DATA_S 0 |
| #define | CAN_TXRQ1_TXRQST_M 0x0000FFFF |
| #define | CAN_TXRQ1_TXRQST_S 0 |
| #define | CAN_TXRQ2_TXRQST_M 0x0000FFFF |
| #define | CAN_TXRQ2_TXRQST_S 0 |
| #define | CAN_NWDA1_NEWDAT_M 0x0000FFFF |
| #define | CAN_NWDA1_NEWDAT_S 0 |
| #define | CAN_NWDA2_NEWDAT_M 0x0000FFFF |
| #define | CAN_NWDA2_NEWDAT_S 0 |
| #define | CAN_MSG1INT_INTPND_M 0x0000FFFF |
| #define | CAN_MSG1INT_INTPND_S 0 |
| #define | CAN_MSG2INT_INTPND_M 0x0000FFFF |
| #define | CAN_MSG2INT_INTPND_S 0 |
| #define | CAN_MSG1VAL_MSGVAL_M 0x0000FFFF |
| #define | CAN_MSG1VAL_MSGVAL_S 0 |
| #define | CAN_MSG2VAL_MSGVAL_M 0x0000FFFF |
| #define | CAN_MSG2VAL_MSGVAL_S 0 |
| #define | USB_FADDR_M 0x0000007F |
| #define | USB_FADDR_S 0 |
| #define | USB_POWER_ISOUP 0x00000080 |
| #define | USB_POWER_SOFTCONN 0x00000040 |
| #define | USB_POWER_RESET 0x00000008 |
| #define | USB_POWER_RESUME 0x00000004 |
| #define | USB_POWER_SUSPEND 0x00000002 |
| #define | USB_POWER_PWRDNPHY 0x00000001 |
| #define | USB_TXIS_EP7 0x00000080 |
| #define | USB_TXIS_EP6 0x00000040 |
| #define | USB_TXIS_EP5 0x00000020 |
| #define | USB_TXIS_EP4 0x00000010 |
| #define | USB_TXIS_EP3 0x00000008 |
| #define | USB_TXIS_EP2 0x00000004 |
| #define | USB_TXIS_EP1 0x00000002 |
| #define | USB_TXIS_EP0 0x00000001 |
| #define | USB_RXIS_EP7 0x00000080 |
| #define | USB_RXIS_EP6 0x00000040 |
| #define | USB_RXIS_EP5 0x00000020 |
| #define | USB_RXIS_EP4 0x00000010 |
| #define | USB_RXIS_EP3 0x00000008 |
| #define | USB_RXIS_EP2 0x00000004 |
| #define | USB_RXIS_EP1 0x00000002 |
| #define | USB_TXIE_EP7 0x00000080 |
| #define | USB_TXIE_EP6 0x00000040 |
| #define | USB_TXIE_EP5 0x00000020 |
| #define | USB_TXIE_EP4 0x00000010 |
| #define | USB_TXIE_EP3 0x00000008 |
| #define | USB_TXIE_EP2 0x00000004 |
| #define | USB_TXIE_EP1 0x00000002 |
| #define | USB_TXIE_EP0 0x00000001 |
| #define | USB_RXIE_EP7 0x00000080 |
| #define | USB_RXIE_EP6 0x00000040 |
| #define | USB_RXIE_EP5 0x00000020 |
| #define | USB_RXIE_EP4 0x00000010 |
| #define | USB_RXIE_EP3 0x00000008 |
| #define | USB_RXIE_EP2 0x00000004 |
| #define | USB_RXIE_EP1 0x00000002 |
| #define | USB_IS_VBUSERR 0x00000080 |
| #define | USB_IS_SESREQ 0x00000040 |
| #define | USB_IS_DISCON 0x00000020 |
| #define | USB_IS_CONN 0x00000010 |
| #define | USB_IS_SOF 0x00000008 |
| #define | USB_IS_BABBLE 0x00000004 |
| #define | USB_IS_RESET 0x00000004 |
| #define | USB_IS_RESUME 0x00000002 |
| #define | USB_IS_SUSPEND 0x00000001 |
| #define | USB_IE_VBUSERR 0x00000080 |
| #define | USB_IE_SESREQ 0x00000040 |
| #define | USB_IE_DISCON 0x00000020 |
| #define | USB_IE_CONN 0x00000010 |
| #define | USB_IE_SOF 0x00000008 |
| #define | USB_IE_BABBLE 0x00000004 |
| #define | USB_IE_RESET 0x00000004 |
| #define | USB_IE_RESUME 0x00000002 |
| #define | USB_IE_SUSPND 0x00000001 |
| #define | USB_FRAME_M 0x000007FF |
| #define | USB_FRAME_S 0 |
| #define | USB_EPIDX_EPIDX_M 0x0000000F |
| #define | USB_EPIDX_EPIDX_S 0 |
| #define | USB_TEST_FORCEH 0x00000080 |
| #define | USB_TEST_FIFOACC 0x00000040 |
| #define | USB_TEST_FORCEFS 0x00000020 |
| #define | USB_FIFO0_EPDATA_M 0xFFFFFFFF |
| #define | USB_FIFO0_EPDATA_S 0 |
| #define | USB_FIFO1_EPDATA_M 0xFFFFFFFF |
| #define | USB_FIFO1_EPDATA_S 0 |
| #define | USB_FIFO2_EPDATA_M 0xFFFFFFFF |
| #define | USB_FIFO2_EPDATA_S 0 |
| #define | USB_FIFO3_EPDATA_M 0xFFFFFFFF |
| #define | USB_FIFO3_EPDATA_S 0 |
| #define | USB_FIFO4_EPDATA_M 0xFFFFFFFF |
| #define | USB_FIFO4_EPDATA_S 0 |
| #define | USB_FIFO5_EPDATA_M 0xFFFFFFFF |
| #define | USB_FIFO5_EPDATA_S 0 |
| #define | USB_FIFO6_EPDATA_M 0xFFFFFFFF |
| #define | USB_FIFO6_EPDATA_S 0 |
| #define | USB_FIFO7_EPDATA_M 0xFFFFFFFF |
| #define | USB_FIFO7_EPDATA_S 0 |
| #define | USB_DEVCTL_DEV 0x00000080 |
| #define | USB_DEVCTL_FSDEV 0x00000040 |
| #define | USB_DEVCTL_LSDEV 0x00000020 |
| #define | USB_DEVCTL_VBUS_M 0x00000018 |
| #define | USB_DEVCTL_VBUS_NONE 0x00000000 |
| #define | USB_DEVCTL_VBUS_SEND 0x00000008 |
| #define | USB_DEVCTL_VBUS_AVALID 0x00000010 |
| #define | USB_DEVCTL_VBUS_VALID 0x00000018 |
| #define | USB_DEVCTL_HOST 0x00000004 |
| #define | USB_DEVCTL_HOSTREQ 0x00000002 |
| #define | USB_DEVCTL_SESSION 0x00000001 |
| #define | USB_TXFIFOSZ_DPB 0x00000010 |
| #define | USB_TXFIFOSZ_SIZE_M 0x0000000F |
| #define | USB_TXFIFOSZ_SIZE_8 0x00000000 |
| #define | USB_TXFIFOSZ_SIZE_16 0x00000001 |
| #define | USB_TXFIFOSZ_SIZE_32 0x00000002 |
| #define | USB_TXFIFOSZ_SIZE_64 0x00000003 |
| #define | USB_TXFIFOSZ_SIZE_128 0x00000004 |
| #define | USB_TXFIFOSZ_SIZE_256 0x00000005 |
| #define | USB_TXFIFOSZ_SIZE_512 0x00000006 |
| #define | USB_TXFIFOSZ_SIZE_1024 0x00000007 |
| #define | USB_TXFIFOSZ_SIZE_2048 0x00000008 |
| #define | USB_RXFIFOSZ_DPB 0x00000010 |
| #define | USB_RXFIFOSZ_SIZE_M 0x0000000F |
| #define | USB_RXFIFOSZ_SIZE_8 0x00000000 |
| #define | USB_RXFIFOSZ_SIZE_16 0x00000001 |
| #define | USB_RXFIFOSZ_SIZE_32 0x00000002 |
| #define | USB_RXFIFOSZ_SIZE_64 0x00000003 |
| #define | USB_RXFIFOSZ_SIZE_128 0x00000004 |
| #define | USB_RXFIFOSZ_SIZE_256 0x00000005 |
| #define | USB_RXFIFOSZ_SIZE_512 0x00000006 |
| #define | USB_RXFIFOSZ_SIZE_1024 0x00000007 |
| #define | USB_RXFIFOSZ_SIZE_2048 0x00000008 |
| #define | USB_TXFIFOADD_ADDR_M 0x000001FF |
| #define | USB_TXFIFOADD_ADDR_S 0 |
| #define | USB_RXFIFOADD_ADDR_M 0x000001FF |
| #define | USB_RXFIFOADD_ADDR_S 0 |
| #define | USB_CONTIM_WTCON_M 0x000000F0 |
| #define | USB_CONTIM_WTID_M 0x0000000F |
| #define | USB_CONTIM_WTCON_S 4 |
| #define | USB_CONTIM_WTID_S 0 |
| #define | USB_VPLEN_VPLEN_M 0x000000FF |
| #define | USB_VPLEN_VPLEN_S 0 |
| #define | USB_FSEOF_FSEOFG_M 0x000000FF |
| #define | USB_FSEOF_FSEOFG_S 0 |
| #define | USB_LSEOF_LSEOFG_M 0x000000FF |
| #define | USB_LSEOF_LSEOFG_S 0 |
| #define | USB_TXFUNCADDR0_ADDR_M 0x0000007F |
| #define | USB_TXFUNCADDR0_ADDR_S 0 |
| #define | USB_TXHUBADDR0_ADDR_M 0x0000007F |
| #define | USB_TXHUBADDR0_ADDR_S 0 |
| #define | USB_TXHUBPORT0_PORT_M 0x0000007F |
| #define | USB_TXHUBPORT0_PORT_S 0 |
| #define | USB_TXFUNCADDR1_ADDR_M 0x0000007F |
| #define | USB_TXFUNCADDR1_ADDR_S 0 |
| #define | USB_TXHUBADDR1_ADDR_M 0x0000007F |
| #define | USB_TXHUBADDR1_ADDR_S 0 |
| #define | USB_TXHUBPORT1_PORT_M 0x0000007F |
| #define | USB_TXHUBPORT1_PORT_S 0 |
| #define | USB_RXFUNCADDR1_ADDR_M 0x0000007F |
| #define | USB_RXFUNCADDR1_ADDR_S 0 |
| #define | USB_RXHUBADDR1_ADDR_M 0x0000007F |
| #define | USB_RXHUBADDR1_ADDR_S 0 |
| #define | USB_RXHUBPORT1_PORT_M 0x0000007F |
| #define | USB_RXHUBPORT1_PORT_S 0 |
| #define | USB_TXFUNCADDR2_ADDR_M 0x0000007F |
| #define | USB_TXFUNCADDR2_ADDR_S 0 |
| #define | USB_TXHUBADDR2_ADDR_M 0x0000007F |
| #define | USB_TXHUBADDR2_ADDR_S 0 |
| #define | USB_TXHUBPORT2_PORT_M 0x0000007F |
| #define | USB_TXHUBPORT2_PORT_S 0 |
| #define | USB_RXFUNCADDR2_ADDR_M 0x0000007F |
| #define | USB_RXFUNCADDR2_ADDR_S 0 |
| #define | USB_RXHUBADDR2_ADDR_M 0x0000007F |
| #define | USB_RXHUBADDR2_ADDR_S 0 |
| #define | USB_RXHUBPORT2_PORT_M 0x0000007F |
| #define | USB_RXHUBPORT2_PORT_S 0 |
| #define | USB_TXFUNCADDR3_ADDR_M 0x0000007F |
| #define | USB_TXFUNCADDR3_ADDR_S 0 |
| #define | USB_TXHUBADDR3_ADDR_M 0x0000007F |
| #define | USB_TXHUBADDR3_ADDR_S 0 |
| #define | USB_TXHUBPORT3_PORT_M 0x0000007F |
| #define | USB_TXHUBPORT3_PORT_S 0 |
| #define | USB_RXFUNCADDR3_ADDR_M 0x0000007F |
| #define | USB_RXFUNCADDR3_ADDR_S 0 |
| #define | USB_RXHUBADDR3_ADDR_M 0x0000007F |
| #define | USB_RXHUBADDR3_ADDR_S 0 |
| #define | USB_RXHUBPORT3_PORT_M 0x0000007F |
| #define | USB_RXHUBPORT3_PORT_S 0 |
| #define | USB_TXFUNCADDR4_ADDR_M 0x0000007F |
| #define | USB_TXFUNCADDR4_ADDR_S 0 |
| #define | USB_TXHUBADDR4_ADDR_M 0x0000007F |
| #define | USB_TXHUBADDR4_ADDR_S 0 |
| #define | USB_TXHUBPORT4_PORT_M 0x0000007F |
| #define | USB_TXHUBPORT4_PORT_S 0 |
| #define | USB_RXFUNCADDR4_ADDR_M 0x0000007F |
| #define | USB_RXFUNCADDR4_ADDR_S 0 |
| #define | USB_RXHUBADDR4_ADDR_M 0x0000007F |
| #define | USB_RXHUBADDR4_ADDR_S 0 |
| #define | USB_RXHUBPORT4_PORT_M 0x0000007F |
| #define | USB_RXHUBPORT4_PORT_S 0 |
| #define | USB_TXFUNCADDR5_ADDR_M 0x0000007F |
| #define | USB_TXFUNCADDR5_ADDR_S 0 |
| #define | USB_TXHUBADDR5_ADDR_M 0x0000007F |
| #define | USB_TXHUBADDR5_ADDR_S 0 |
| #define | USB_TXHUBPORT5_PORT_M 0x0000007F |
| #define | USB_TXHUBPORT5_PORT_S 0 |
| #define | USB_RXFUNCADDR5_ADDR_M 0x0000007F |
| #define | USB_RXFUNCADDR5_ADDR_S 0 |
| #define | USB_RXHUBADDR5_ADDR_M 0x0000007F |
| #define | USB_RXHUBADDR5_ADDR_S 0 |
| #define | USB_RXHUBPORT5_PORT_M 0x0000007F |
| #define | USB_RXHUBPORT5_PORT_S 0 |
| #define | USB_TXFUNCADDR6_ADDR_M 0x0000007F |
| #define | USB_TXFUNCADDR6_ADDR_S 0 |
| #define | USB_TXHUBADDR6_ADDR_M 0x0000007F |
| #define | USB_TXHUBADDR6_ADDR_S 0 |
| #define | USB_TXHUBPORT6_PORT_M 0x0000007F |
| #define | USB_TXHUBPORT6_PORT_S 0 |
| #define | USB_RXFUNCADDR6_ADDR_M 0x0000007F |
| #define | USB_RXFUNCADDR6_ADDR_S 0 |
| #define | USB_RXHUBADDR6_ADDR_M 0x0000007F |
| #define | USB_RXHUBADDR6_ADDR_S 0 |
| #define | USB_RXHUBPORT6_PORT_M 0x0000007F |
| #define | USB_RXHUBPORT6_PORT_S 0 |
| #define | USB_TXFUNCADDR7_ADDR_M 0x0000007F |
| #define | USB_TXFUNCADDR7_ADDR_S 0 |
| #define | USB_TXHUBADDR7_ADDR_M 0x0000007F |
| #define | USB_TXHUBADDR7_ADDR_S 0 |
| #define | USB_TXHUBPORT7_PORT_M 0x0000007F |
| #define | USB_TXHUBPORT7_PORT_S 0 |
| #define | USB_RXFUNCADDR7_ADDR_M 0x0000007F |
| #define | USB_RXFUNCADDR7_ADDR_S 0 |
| #define | USB_RXHUBADDR7_ADDR_M 0x0000007F |
| #define | USB_RXHUBADDR7_ADDR_S 0 |
| #define | USB_RXHUBPORT7_PORT_M 0x0000007F |
| #define | USB_RXHUBPORT7_PORT_S 0 |
| #define | USB_CSRL0_NAKTO 0x00000080 |
| #define | USB_CSRL0_SETENDC 0x00000080 |
| #define | USB_CSRL0_STATUS 0x00000040 |
| #define | USB_CSRL0_RXRDYC 0x00000040 |
| #define | USB_CSRL0_REQPKT 0x00000020 |
| #define | USB_CSRL0_STALL 0x00000020 |
| #define | USB_CSRL0_SETEND 0x00000010 |
| #define | USB_CSRL0_ERROR 0x00000010 |
| #define | USB_CSRL0_DATAEND 0x00000008 |
| #define | USB_CSRL0_SETUP 0x00000008 |
| #define | USB_CSRL0_STALLED 0x00000004 |
| #define | USB_CSRL0_TXRDY 0x00000002 |
| #define | USB_CSRL0_RXRDY 0x00000001 |
| #define | USB_CSRH0_DTWE 0x00000004 |
| #define | USB_CSRH0_DT 0x00000002 |
| #define | USB_CSRH0_FLUSH 0x00000001 |
| #define | USB_COUNT0_COUNT_M 0x0000007F |
| #define | USB_COUNT0_COUNT_S 0 |
| #define | USB_TYPE0_SPEED_M 0x000000C0 |
| #define | USB_TYPE0_SPEED_FULL 0x00000080 |
| #define | USB_TYPE0_SPEED_LOW 0x000000C0 |
| #define | USB_NAKLMT_NAKLMT_M 0x0000001F |
| #define | USB_NAKLMT_NAKLMT_S 0 |
| #define | USB_TXMAXP1_MAXLOAD_M 0x000007FF |
| #define | USB_TXMAXP1_MAXLOAD_S 0 |
| #define | USB_TXCSRL1_NAKTO 0x00000080 |
| #define | USB_TXCSRL1_CLRDT 0x00000040 |
| #define | USB_TXCSRL1_STALLED 0x00000020 |
| #define | USB_TXCSRL1_STALL 0x00000010 |
| #define | USB_TXCSRL1_SETUP 0x00000010 |
| #define | USB_TXCSRL1_FLUSH 0x00000008 |
| #define | USB_TXCSRL1_ERROR 0x00000004 |
| #define | USB_TXCSRL1_UNDRN 0x00000004 |
| #define | USB_TXCSRL1_FIFONE 0x00000002 |
| #define | USB_TXCSRL1_TXRDY 0x00000001 |
| #define | USB_TXCSRH1_AUTOSET 0x00000080 |
| #define | USB_TXCSRH1_ISO 0x00000040 |
| #define | USB_TXCSRH1_MODE 0x00000020 |
| #define | USB_TXCSRH1_DMAEN 0x00000010 |
| #define | USB_TXCSRH1_FDT 0x00000008 |
| #define | USB_TXCSRH1_DMAMOD 0x00000004 |
| #define | USB_TXCSRH1_DTWE 0x00000002 |
| #define | USB_TXCSRH1_DT 0x00000001 |
| #define | USB_RXMAXP1_MAXLOAD_M 0x000007FF |
| #define | USB_RXMAXP1_MAXLOAD_S 0 |
| #define | USB_RXCSRL1_CLRDT 0x00000080 |
| #define | USB_RXCSRL1_STALLED 0x00000040 |
| #define | USB_RXCSRL1_STALL 0x00000020 |
| #define | USB_RXCSRL1_REQPKT 0x00000020 |
| #define | USB_RXCSRL1_FLUSH 0x00000010 |
| #define | USB_RXCSRL1_DATAERR 0x00000008 |
| #define | USB_RXCSRL1_NAKTO 0x00000008 |
| #define | USB_RXCSRL1_OVER 0x00000004 |
| #define | USB_RXCSRL1_ERROR 0x00000004 |
| #define | USB_RXCSRL1_FULL 0x00000002 |
| #define | USB_RXCSRL1_RXRDY 0x00000001 |
| #define | USB_RXCSRH1_AUTOCL 0x00000080 |
| #define | USB_RXCSRH1_AUTORQ 0x00000040 |
| #define | USB_RXCSRH1_ISO 0x00000040 |
| #define | USB_RXCSRH1_DMAEN 0x00000020 |
| #define | USB_RXCSRH1_DISNYET 0x00000010 |
| #define | USB_RXCSRH1_PIDERR 0x00000010 |
| #define | USB_RXCSRH1_DMAMOD 0x00000008 |
| #define | USB_RXCSRH1_DTWE 0x00000004 |
| #define | USB_RXCSRH1_DT 0x00000002 |
| #define | USB_RXCOUNT1_COUNT_M 0x00001FFF |
| #define | USB_RXCOUNT1_COUNT_S 0 |
| #define | USB_TXTYPE1_SPEED_M 0x000000C0 |
| #define | USB_TXTYPE1_SPEED_DFLT 0x00000000 |
| #define | USB_TXTYPE1_SPEED_FULL 0x00000080 |
| #define | USB_TXTYPE1_SPEED_LOW 0x000000C0 |
| #define | USB_TXTYPE1_PROTO_M 0x00000030 |
| #define | USB_TXTYPE1_PROTO_CTRL 0x00000000 |
| #define | USB_TXTYPE1_PROTO_ISOC 0x00000010 |
| #define | USB_TXTYPE1_PROTO_BULK 0x00000020 |
| #define | USB_TXTYPE1_PROTO_INT 0x00000030 |
| #define | USB_TXTYPE1_TEP_M 0x0000000F |
| #define | USB_TXTYPE1_TEP_S 0 |
| #define | USB_TXINTERVAL1_NAKLMT_M 0x000000FF |
| #define | USB_TXINTERVAL1_TXPOLL_M 0x000000FF |
| #define | USB_TXINTERVAL1_TXPOLL_S 0 |
| #define | USB_TXINTERVAL1_NAKLMT_S 0 |
| #define | USB_RXTYPE1_SPEED_M 0x000000C0 |
| #define | USB_RXTYPE1_SPEED_DFLT 0x00000000 |
| #define | USB_RXTYPE1_SPEED_FULL 0x00000080 |
| #define | USB_RXTYPE1_SPEED_LOW 0x000000C0 |
| #define | USB_RXTYPE1_PROTO_M 0x00000030 |
| #define | USB_RXTYPE1_PROTO_CTRL 0x00000000 |
| #define | USB_RXTYPE1_PROTO_ISOC 0x00000010 |
| #define | USB_RXTYPE1_PROTO_BULK 0x00000020 |
| #define | USB_RXTYPE1_PROTO_INT 0x00000030 |
| #define | USB_RXTYPE1_TEP_M 0x0000000F |
| #define | USB_RXTYPE1_TEP_S 0 |
| #define | USB_RXINTERVAL1_TXPOLL_M 0x000000FF |
| #define | USB_RXINTERVAL1_NAKLMT_M 0x000000FF |
| #define | USB_RXINTERVAL1_TXPOLL_S 0 |
| #define | USB_RXINTERVAL1_NAKLMT_S 0 |
| #define | USB_TXMAXP2_MAXLOAD_M 0x000007FF |
| #define | USB_TXMAXP2_MAXLOAD_S 0 |
| #define | USB_TXCSRL2_NAKTO 0x00000080 |
| #define | USB_TXCSRL2_CLRDT 0x00000040 |
| #define | USB_TXCSRL2_STALLED 0x00000020 |
| #define | USB_TXCSRL2_SETUP 0x00000010 |
| #define | USB_TXCSRL2_STALL 0x00000010 |
| #define | USB_TXCSRL2_FLUSH 0x00000008 |
| #define | USB_TXCSRL2_ERROR 0x00000004 |
| #define | USB_TXCSRL2_UNDRN 0x00000004 |
| #define | USB_TXCSRL2_FIFONE 0x00000002 |
| #define | USB_TXCSRL2_TXRDY 0x00000001 |
| #define | USB_TXCSRH2_AUTOSET 0x00000080 |
| #define | USB_TXCSRH2_ISO 0x00000040 |
| #define | USB_TXCSRH2_MODE 0x00000020 |
| #define | USB_TXCSRH2_DMAEN 0x00000010 |
| #define | USB_TXCSRH2_FDT 0x00000008 |
| #define | USB_TXCSRH2_DMAMOD 0x00000004 |
| #define | USB_TXCSRH2_DTWE 0x00000002 |
| #define | USB_TXCSRH2_DT 0x00000001 |
| #define | USB_RXMAXP2_MAXLOAD_M 0x000007FF |
| #define | USB_RXMAXP2_MAXLOAD_S 0 |
| #define | USB_RXCSRL2_CLRDT 0x00000080 |
| #define | USB_RXCSRL2_STALLED 0x00000040 |
| #define | USB_RXCSRL2_REQPKT 0x00000020 |
| #define | USB_RXCSRL2_STALL 0x00000020 |
| #define | USB_RXCSRL2_FLUSH 0x00000010 |
| #define | USB_RXCSRL2_DATAERR 0x00000008 |
| #define | USB_RXCSRL2_NAKTO 0x00000008 |
| #define | USB_RXCSRL2_ERROR 0x00000004 |
| #define | USB_RXCSRL2_OVER 0x00000004 |
| #define | USB_RXCSRL2_FULL 0x00000002 |
| #define | USB_RXCSRL2_RXRDY 0x00000001 |
| #define | USB_RXCSRH2_AUTOCL 0x00000080 |
| #define | USB_RXCSRH2_AUTORQ 0x00000040 |
| #define | USB_RXCSRH2_ISO 0x00000040 |
| #define | USB_RXCSRH2_DMAEN 0x00000020 |
| #define | USB_RXCSRH2_DISNYET 0x00000010 |
| #define | USB_RXCSRH2_PIDERR 0x00000010 |
| #define | USB_RXCSRH2_DMAMOD 0x00000008 |
| #define | USB_RXCSRH2_DTWE 0x00000004 |
| #define | USB_RXCSRH2_DT 0x00000002 |
| #define | USB_RXCOUNT2_COUNT_M 0x00001FFF |
| #define | USB_RXCOUNT2_COUNT_S 0 |
| #define | USB_TXTYPE2_SPEED_M 0x000000C0 |
| #define | USB_TXTYPE2_SPEED_DFLT 0x00000000 |
| #define | USB_TXTYPE2_SPEED_FULL 0x00000080 |
| #define | USB_TXTYPE2_SPEED_LOW 0x000000C0 |
| #define | USB_TXTYPE2_PROTO_M 0x00000030 |
| #define | USB_TXTYPE2_PROTO_CTRL 0x00000000 |
| #define | USB_TXTYPE2_PROTO_ISOC 0x00000010 |
| #define | USB_TXTYPE2_PROTO_BULK 0x00000020 |
| #define | USB_TXTYPE2_PROTO_INT 0x00000030 |
| #define | USB_TXTYPE2_TEP_M 0x0000000F |
| #define | USB_TXTYPE2_TEP_S 0 |
| #define | USB_TXINTERVAL2_TXPOLL_M 0x000000FF |
| #define | USB_TXINTERVAL2_NAKLMT_M 0x000000FF |
| #define | USB_TXINTERVAL2_NAKLMT_S 0 |
| #define | USB_TXINTERVAL2_TXPOLL_S 0 |
| #define | USB_RXTYPE2_SPEED_M 0x000000C0 |
| #define | USB_RXTYPE2_SPEED_DFLT 0x00000000 |
| #define | USB_RXTYPE2_SPEED_FULL 0x00000080 |
| #define | USB_RXTYPE2_SPEED_LOW 0x000000C0 |
| #define | USB_RXTYPE2_PROTO_M 0x00000030 |
| #define | USB_RXTYPE2_PROTO_CTRL 0x00000000 |
| #define | USB_RXTYPE2_PROTO_ISOC 0x00000010 |
| #define | USB_RXTYPE2_PROTO_BULK 0x00000020 |
| #define | USB_RXTYPE2_PROTO_INT 0x00000030 |
| #define | USB_RXTYPE2_TEP_M 0x0000000F |
| #define | USB_RXTYPE2_TEP_S 0 |
| #define | USB_RXINTERVAL2_TXPOLL_M 0x000000FF |
| #define | USB_RXINTERVAL2_NAKLMT_M 0x000000FF |
| #define | USB_RXINTERVAL2_TXPOLL_S 0 |
| #define | USB_RXINTERVAL2_NAKLMT_S 0 |
| #define | USB_TXMAXP3_MAXLOAD_M 0x000007FF |
| #define | USB_TXMAXP3_MAXLOAD_S 0 |
| #define | USB_TXCSRL3_NAKTO 0x00000080 |
| #define | USB_TXCSRL3_CLRDT 0x00000040 |
| #define | USB_TXCSRL3_STALLED 0x00000020 |
| #define | USB_TXCSRL3_SETUP 0x00000010 |
| #define | USB_TXCSRL3_STALL 0x00000010 |
| #define | USB_TXCSRL3_FLUSH 0x00000008 |
| #define | USB_TXCSRL3_ERROR 0x00000004 |
| #define | USB_TXCSRL3_UNDRN 0x00000004 |
| #define | USB_TXCSRL3_FIFONE 0x00000002 |
| #define | USB_TXCSRL3_TXRDY 0x00000001 |
| #define | USB_TXCSRH3_AUTOSET 0x00000080 |
| #define | USB_TXCSRH3_ISO 0x00000040 |
| #define | USB_TXCSRH3_MODE 0x00000020 |
| #define | USB_TXCSRH3_DMAEN 0x00000010 |
| #define | USB_TXCSRH3_FDT 0x00000008 |
| #define | USB_TXCSRH3_DMAMOD 0x00000004 |
| #define | USB_TXCSRH3_DTWE 0x00000002 |
| #define | USB_TXCSRH3_DT 0x00000001 |
| #define | USB_RXMAXP3_MAXLOAD_M 0x000007FF |
| #define | USB_RXMAXP3_MAXLOAD_S 0 |
| #define | USB_RXCSRL3_CLRDT 0x00000080 |
| #define | USB_RXCSRL3_STALLED 0x00000040 |
| #define | USB_RXCSRL3_STALL 0x00000020 |
| #define | USB_RXCSRL3_REQPKT 0x00000020 |
| #define | USB_RXCSRL3_FLUSH 0x00000010 |
| #define | USB_RXCSRL3_DATAERR 0x00000008 |
| #define | USB_RXCSRL3_NAKTO 0x00000008 |
| #define | USB_RXCSRL3_ERROR 0x00000004 |
| #define | USB_RXCSRL3_OVER 0x00000004 |
| #define | USB_RXCSRL3_FULL 0x00000002 |
| #define | USB_RXCSRL3_RXRDY 0x00000001 |
| #define | USB_RXCSRH3_AUTOCL 0x00000080 |
| #define | USB_RXCSRH3_AUTORQ 0x00000040 |
| #define | USB_RXCSRH3_ISO 0x00000040 |
| #define | USB_RXCSRH3_DMAEN 0x00000020 |
| #define | USB_RXCSRH3_DISNYET 0x00000010 |
| #define | USB_RXCSRH3_PIDERR 0x00000010 |
| #define | USB_RXCSRH3_DMAMOD 0x00000008 |
| #define | USB_RXCSRH3_DTWE 0x00000004 |
| #define | USB_RXCSRH3_DT 0x00000002 |
| #define | USB_RXCOUNT3_COUNT_M 0x00001FFF |
| #define | USB_RXCOUNT3_COUNT_S 0 |
| #define | USB_TXTYPE3_SPEED_M 0x000000C0 |
| #define | USB_TXTYPE3_SPEED_DFLT 0x00000000 |
| #define | USB_TXTYPE3_SPEED_FULL 0x00000080 |
| #define | USB_TXTYPE3_SPEED_LOW 0x000000C0 |
| #define | USB_TXTYPE3_PROTO_M 0x00000030 |
| #define | USB_TXTYPE3_PROTO_CTRL 0x00000000 |
| #define | USB_TXTYPE3_PROTO_ISOC 0x00000010 |
| #define | USB_TXTYPE3_PROTO_BULK 0x00000020 |
| #define | USB_TXTYPE3_PROTO_INT 0x00000030 |
| #define | USB_TXTYPE3_TEP_M 0x0000000F |
| #define | USB_TXTYPE3_TEP_S 0 |
| #define | USB_TXINTERVAL3_TXPOLL_M 0x000000FF |
| #define | USB_TXINTERVAL3_NAKLMT_M 0x000000FF |
| #define | USB_TXINTERVAL3_TXPOLL_S 0 |
| #define | USB_TXINTERVAL3_NAKLMT_S 0 |
| #define | USB_RXTYPE3_SPEED_M 0x000000C0 |
| #define | USB_RXTYPE3_SPEED_DFLT 0x00000000 |
| #define | USB_RXTYPE3_SPEED_FULL 0x00000080 |
| #define | USB_RXTYPE3_SPEED_LOW 0x000000C0 |
| #define | USB_RXTYPE3_PROTO_M 0x00000030 |
| #define | USB_RXTYPE3_PROTO_CTRL 0x00000000 |
| #define | USB_RXTYPE3_PROTO_ISOC 0x00000010 |
| #define | USB_RXTYPE3_PROTO_BULK 0x00000020 |
| #define | USB_RXTYPE3_PROTO_INT 0x00000030 |
| #define | USB_RXTYPE3_TEP_M 0x0000000F |
| #define | USB_RXTYPE3_TEP_S 0 |
| #define | USB_RXINTERVAL3_TXPOLL_M 0x000000FF |
| #define | USB_RXINTERVAL3_NAKLMT_M 0x000000FF |
| #define | USB_RXINTERVAL3_TXPOLL_S 0 |
| #define | USB_RXINTERVAL3_NAKLMT_S 0 |
| #define | USB_TXMAXP4_MAXLOAD_M 0x000007FF |
| #define | USB_TXMAXP4_MAXLOAD_S 0 |
| #define | USB_TXCSRL4_NAKTO 0x00000080 |
| #define | USB_TXCSRL4_CLRDT 0x00000040 |
| #define | USB_TXCSRL4_STALLED 0x00000020 |
| #define | USB_TXCSRL4_SETUP 0x00000010 |
| #define | USB_TXCSRL4_STALL 0x00000010 |
| #define | USB_TXCSRL4_FLUSH 0x00000008 |
| #define | USB_TXCSRL4_ERROR 0x00000004 |
| #define | USB_TXCSRL4_UNDRN 0x00000004 |
| #define | USB_TXCSRL4_FIFONE 0x00000002 |
| #define | USB_TXCSRL4_TXRDY 0x00000001 |
| #define | USB_TXCSRH4_AUTOSET 0x00000080 |
| #define | USB_TXCSRH4_ISO 0x00000040 |
| #define | USB_TXCSRH4_MODE 0x00000020 |
| #define | USB_TXCSRH4_DMAEN 0x00000010 |
| #define | USB_TXCSRH4_FDT 0x00000008 |
| #define | USB_TXCSRH4_DMAMOD 0x00000004 |
| #define | USB_TXCSRH4_DTWE 0x00000002 |
| #define | USB_TXCSRH4_DT 0x00000001 |
| #define | USB_RXMAXP4_MAXLOAD_M 0x000007FF |
| #define | USB_RXMAXP4_MAXLOAD_S 0 |
| #define | USB_RXCSRL4_CLRDT 0x00000080 |
| #define | USB_RXCSRL4_STALLED 0x00000040 |
| #define | USB_RXCSRL4_STALL 0x00000020 |
| #define | USB_RXCSRL4_REQPKT 0x00000020 |
| #define | USB_RXCSRL4_FLUSH 0x00000010 |
| #define | USB_RXCSRL4_NAKTO 0x00000008 |
| #define | USB_RXCSRL4_DATAERR 0x00000008 |
| #define | USB_RXCSRL4_OVER 0x00000004 |
| #define | USB_RXCSRL4_ERROR 0x00000004 |
| #define | USB_RXCSRL4_FULL 0x00000002 |
| #define | USB_RXCSRL4_RXRDY 0x00000001 |
| #define | USB_RXCSRH4_AUTOCL 0x00000080 |
| #define | USB_RXCSRH4_AUTORQ 0x00000040 |
| #define | USB_RXCSRH4_ISO 0x00000040 |
| #define | USB_RXCSRH4_DMAEN 0x00000020 |
| #define | USB_RXCSRH4_DISNYET 0x00000010 |
| #define | USB_RXCSRH4_PIDERR 0x00000010 |
| #define | USB_RXCSRH4_DMAMOD 0x00000008 |
| #define | USB_RXCSRH4_DTWE 0x00000004 |
| #define | USB_RXCSRH4_DT 0x00000002 |
| #define | USB_RXCOUNT4_COUNT_M 0x00001FFF |
| #define | USB_RXCOUNT4_COUNT_S 0 |
| #define | USB_TXTYPE4_SPEED_M 0x000000C0 |
| #define | USB_TXTYPE4_SPEED_DFLT 0x00000000 |
| #define | USB_TXTYPE4_SPEED_FULL 0x00000080 |
| #define | USB_TXTYPE4_SPEED_LOW 0x000000C0 |
| #define | USB_TXTYPE4_PROTO_M 0x00000030 |
| #define | USB_TXTYPE4_PROTO_CTRL 0x00000000 |
| #define | USB_TXTYPE4_PROTO_ISOC 0x00000010 |
| #define | USB_TXTYPE4_PROTO_BULK 0x00000020 |
| #define | USB_TXTYPE4_PROTO_INT 0x00000030 |
| #define | USB_TXTYPE4_TEP_M 0x0000000F |
| #define | USB_TXTYPE4_TEP_S 0 |
| #define | USB_TXINTERVAL4_TXPOLL_M 0x000000FF |
| #define | USB_TXINTERVAL4_NAKLMT_M 0x000000FF |
| #define | USB_TXINTERVAL4_NAKLMT_S 0 |
| #define | USB_TXINTERVAL4_TXPOLL_S 0 |
| #define | USB_RXTYPE4_SPEED_M 0x000000C0 |
| #define | USB_RXTYPE4_SPEED_DFLT 0x00000000 |
| #define | USB_RXTYPE4_SPEED_FULL 0x00000080 |
| #define | USB_RXTYPE4_SPEED_LOW 0x000000C0 |
| #define | USB_RXTYPE4_PROTO_M 0x00000030 |
| #define | USB_RXTYPE4_PROTO_CTRL 0x00000000 |
| #define | USB_RXTYPE4_PROTO_ISOC 0x00000010 |
| #define | USB_RXTYPE4_PROTO_BULK 0x00000020 |
| #define | USB_RXTYPE4_PROTO_INT 0x00000030 |
| #define | USB_RXTYPE4_TEP_M 0x0000000F |
| #define | USB_RXTYPE4_TEP_S 0 |
| #define | USB_RXINTERVAL4_TXPOLL_M 0x000000FF |
| #define | USB_RXINTERVAL4_NAKLMT_M 0x000000FF |
| #define | USB_RXINTERVAL4_NAKLMT_S 0 |
| #define | USB_RXINTERVAL4_TXPOLL_S 0 |
| #define | USB_TXMAXP5_MAXLOAD_M 0x000007FF |
| #define | USB_TXMAXP5_MAXLOAD_S 0 |
| #define | USB_TXCSRL5_NAKTO 0x00000080 |
| #define | USB_TXCSRL5_CLRDT 0x00000040 |
| #define | USB_TXCSRL5_STALLED 0x00000020 |
| #define | USB_TXCSRL5_SETUP 0x00000010 |
| #define | USB_TXCSRL5_STALL 0x00000010 |
| #define | USB_TXCSRL5_FLUSH 0x00000008 |
| #define | USB_TXCSRL5_ERROR 0x00000004 |
| #define | USB_TXCSRL5_UNDRN 0x00000004 |
| #define | USB_TXCSRL5_FIFONE 0x00000002 |
| #define | USB_TXCSRL5_TXRDY 0x00000001 |
| #define | USB_TXCSRH5_AUTOSET 0x00000080 |
| #define | USB_TXCSRH5_ISO 0x00000040 |
| #define | USB_TXCSRH5_MODE 0x00000020 |
| #define | USB_TXCSRH5_DMAEN 0x00000010 |
| #define | USB_TXCSRH5_FDT 0x00000008 |
| #define | USB_TXCSRH5_DMAMOD 0x00000004 |
| #define | USB_TXCSRH5_DTWE 0x00000002 |
| #define | USB_TXCSRH5_DT 0x00000001 |
| #define | USB_RXMAXP5_MAXLOAD_M 0x000007FF |
| #define | USB_RXMAXP5_MAXLOAD_S 0 |
| #define | USB_RXCSRL5_CLRDT 0x00000080 |
| #define | USB_RXCSRL5_STALLED 0x00000040 |
| #define | USB_RXCSRL5_STALL 0x00000020 |
| #define | USB_RXCSRL5_REQPKT 0x00000020 |
| #define | USB_RXCSRL5_FLUSH 0x00000010 |
| #define | USB_RXCSRL5_NAKTO 0x00000008 |
| #define | USB_RXCSRL5_DATAERR 0x00000008 |
| #define | USB_RXCSRL5_ERROR 0x00000004 |
| #define | USB_RXCSRL5_OVER 0x00000004 |
| #define | USB_RXCSRL5_FULL 0x00000002 |
| #define | USB_RXCSRL5_RXRDY 0x00000001 |
| #define | USB_RXCSRH5_AUTOCL 0x00000080 |
| #define | USB_RXCSRH5_AUTORQ 0x00000040 |
| #define | USB_RXCSRH5_ISO 0x00000040 |
| #define | USB_RXCSRH5_DMAEN 0x00000020 |
| #define | USB_RXCSRH5_DISNYET 0x00000010 |
| #define | USB_RXCSRH5_PIDERR 0x00000010 |
| #define | USB_RXCSRH5_DMAMOD 0x00000008 |
| #define | USB_RXCSRH5_DTWE 0x00000004 |
| #define | USB_RXCSRH5_DT 0x00000002 |
| #define | USB_RXCOUNT5_COUNT_M 0x00001FFF |
| #define | USB_RXCOUNT5_COUNT_S 0 |
| #define | USB_TXTYPE5_SPEED_M 0x000000C0 |
| #define | USB_TXTYPE5_SPEED_DFLT 0x00000000 |
| #define | USB_TXTYPE5_SPEED_FULL 0x00000080 |
| #define | USB_TXTYPE5_SPEED_LOW 0x000000C0 |
| #define | USB_TXTYPE5_PROTO_M 0x00000030 |
| #define | USB_TXTYPE5_PROTO_CTRL 0x00000000 |
| #define | USB_TXTYPE5_PROTO_ISOC 0x00000010 |
| #define | USB_TXTYPE5_PROTO_BULK 0x00000020 |
| #define | USB_TXTYPE5_PROTO_INT 0x00000030 |
| #define | USB_TXTYPE5_TEP_M 0x0000000F |
| #define | USB_TXTYPE5_TEP_S 0 |
| #define | USB_TXINTERVAL5_TXPOLL_M 0x000000FF |
| #define | USB_TXINTERVAL5_NAKLMT_M 0x000000FF |
| #define | USB_TXINTERVAL5_NAKLMT_S 0 |
| #define | USB_TXINTERVAL5_TXPOLL_S 0 |
| #define | USB_RXTYPE5_SPEED_M 0x000000C0 |
| #define | USB_RXTYPE5_SPEED_DFLT 0x00000000 |
| #define | USB_RXTYPE5_SPEED_FULL 0x00000080 |
| #define | USB_RXTYPE5_SPEED_LOW 0x000000C0 |
| #define | USB_RXTYPE5_PROTO_M 0x00000030 |
| #define | USB_RXTYPE5_PROTO_CTRL 0x00000000 |
| #define | USB_RXTYPE5_PROTO_ISOC 0x00000010 |
| #define | USB_RXTYPE5_PROTO_BULK 0x00000020 |
| #define | USB_RXTYPE5_PROTO_INT 0x00000030 |
| #define | USB_RXTYPE5_TEP_M 0x0000000F |
| #define | USB_RXTYPE5_TEP_S 0 |
| #define | USB_RXINTERVAL5_TXPOLL_M 0x000000FF |
| #define | USB_RXINTERVAL5_NAKLMT_M 0x000000FF |
| #define | USB_RXINTERVAL5_TXPOLL_S 0 |
| #define | USB_RXINTERVAL5_NAKLMT_S 0 |
| #define | USB_TXMAXP6_MAXLOAD_M 0x000007FF |
| #define | USB_TXMAXP6_MAXLOAD_S 0 |
| #define | USB_TXCSRL6_NAKTO 0x00000080 |
| #define | USB_TXCSRL6_CLRDT 0x00000040 |
| #define | USB_TXCSRL6_STALLED 0x00000020 |
| #define | USB_TXCSRL6_STALL 0x00000010 |
| #define | USB_TXCSRL6_SETUP 0x00000010 |
| #define | USB_TXCSRL6_FLUSH 0x00000008 |
| #define | USB_TXCSRL6_ERROR 0x00000004 |
| #define | USB_TXCSRL6_UNDRN 0x00000004 |
| #define | USB_TXCSRL6_FIFONE 0x00000002 |
| #define | USB_TXCSRL6_TXRDY 0x00000001 |
| #define | USB_TXCSRH6_AUTOSET 0x00000080 |
| #define | USB_TXCSRH6_ISO 0x00000040 |
| #define | USB_TXCSRH6_MODE 0x00000020 |
| #define | USB_TXCSRH6_DMAEN 0x00000010 |
| #define | USB_TXCSRH6_FDT 0x00000008 |
| #define | USB_TXCSRH6_DMAMOD 0x00000004 |
| #define | USB_TXCSRH6_DTWE 0x00000002 |
| #define | USB_TXCSRH6_DT 0x00000001 |
| #define | USB_RXMAXP6_MAXLOAD_M 0x000007FF |
| #define | USB_RXMAXP6_MAXLOAD_S 0 |
| #define | USB_RXCSRL6_CLRDT 0x00000080 |
| #define | USB_RXCSRL6_STALLED 0x00000040 |
| #define | USB_RXCSRL6_REQPKT 0x00000020 |
| #define | USB_RXCSRL6_STALL 0x00000020 |
| #define | USB_RXCSRL6_FLUSH 0x00000010 |
| #define | USB_RXCSRL6_NAKTO 0x00000008 |
| #define | USB_RXCSRL6_DATAERR 0x00000008 |
| #define | USB_RXCSRL6_ERROR 0x00000004 |
| #define | USB_RXCSRL6_OVER 0x00000004 |
| #define | USB_RXCSRL6_FULL 0x00000002 |
| #define | USB_RXCSRL6_RXRDY 0x00000001 |
| #define | USB_RXCSRH6_AUTOCL 0x00000080 |
| #define | USB_RXCSRH6_AUTORQ 0x00000040 |
| #define | USB_RXCSRH6_ISO 0x00000040 |
| #define | USB_RXCSRH6_DMAEN 0x00000020 |
| #define | USB_RXCSRH6_DISNYET 0x00000010 |
| #define | USB_RXCSRH6_PIDERR 0x00000010 |
| #define | USB_RXCSRH6_DMAMOD 0x00000008 |
| #define | USB_RXCSRH6_DTWE 0x00000004 |
| #define | USB_RXCSRH6_DT 0x00000002 |
| #define | USB_RXCOUNT6_COUNT_M 0x00001FFF |
| #define | USB_RXCOUNT6_COUNT_S 0 |
| #define | USB_TXTYPE6_SPEED_M 0x000000C0 |
| #define | USB_TXTYPE6_SPEED_DFLT 0x00000000 |
| #define | USB_TXTYPE6_SPEED_FULL 0x00000080 |
| #define | USB_TXTYPE6_SPEED_LOW 0x000000C0 |
| #define | USB_TXTYPE6_PROTO_M 0x00000030 |
| #define | USB_TXTYPE6_PROTO_CTRL 0x00000000 |
| #define | USB_TXTYPE6_PROTO_ISOC 0x00000010 |
| #define | USB_TXTYPE6_PROTO_BULK 0x00000020 |
| #define | USB_TXTYPE6_PROTO_INT 0x00000030 |
| #define | USB_TXTYPE6_TEP_M 0x0000000F |
| #define | USB_TXTYPE6_TEP_S 0 |
| #define | USB_TXINTERVAL6_TXPOLL_M 0x000000FF |
| #define | USB_TXINTERVAL6_NAKLMT_M 0x000000FF |
| #define | USB_TXINTERVAL6_TXPOLL_S 0 |
| #define | USB_TXINTERVAL6_NAKLMT_S 0 |
| #define | USB_RXTYPE6_SPEED_M 0x000000C0 |
| #define | USB_RXTYPE6_SPEED_DFLT 0x00000000 |
| #define | USB_RXTYPE6_SPEED_FULL 0x00000080 |
| #define | USB_RXTYPE6_SPEED_LOW 0x000000C0 |
| #define | USB_RXTYPE6_PROTO_M 0x00000030 |
| #define | USB_RXTYPE6_PROTO_CTRL 0x00000000 |
| #define | USB_RXTYPE6_PROTO_ISOC 0x00000010 |
| #define | USB_RXTYPE6_PROTO_BULK 0x00000020 |
| #define | USB_RXTYPE6_PROTO_INT 0x00000030 |
| #define | USB_RXTYPE6_TEP_M 0x0000000F |
| #define | USB_RXTYPE6_TEP_S 0 |
| #define | USB_RXINTERVAL6_TXPOLL_M 0x000000FF |
| #define | USB_RXINTERVAL6_NAKLMT_M 0x000000FF |
| #define | USB_RXINTERVAL6_NAKLMT_S 0 |
| #define | USB_RXINTERVAL6_TXPOLL_S 0 |
| #define | USB_TXMAXP7_MAXLOAD_M 0x000007FF |
| #define | USB_TXMAXP7_MAXLOAD_S 0 |
| #define | USB_TXCSRL7_NAKTO 0x00000080 |
| #define | USB_TXCSRL7_CLRDT 0x00000040 |
| #define | USB_TXCSRL7_STALLED 0x00000020 |
| #define | USB_TXCSRL7_STALL 0x00000010 |
| #define | USB_TXCSRL7_SETUP 0x00000010 |
| #define | USB_TXCSRL7_FLUSH 0x00000008 |
| #define | USB_TXCSRL7_ERROR 0x00000004 |
| #define | USB_TXCSRL7_UNDRN 0x00000004 |
| #define | USB_TXCSRL7_FIFONE 0x00000002 |
| #define | USB_TXCSRL7_TXRDY 0x00000001 |
| #define | USB_TXCSRH7_AUTOSET 0x00000080 |
| #define | USB_TXCSRH7_ISO 0x00000040 |
| #define | USB_TXCSRH7_MODE 0x00000020 |
| #define | USB_TXCSRH7_DMAEN 0x00000010 |
| #define | USB_TXCSRH7_FDT 0x00000008 |
| #define | USB_TXCSRH7_DMAMOD 0x00000004 |
| #define | USB_TXCSRH7_DTWE 0x00000002 |
| #define | USB_TXCSRH7_DT 0x00000001 |
| #define | USB_RXMAXP7_MAXLOAD_M 0x000007FF |
| #define | USB_RXMAXP7_MAXLOAD_S 0 |
| #define | USB_RXCSRL7_CLRDT 0x00000080 |
| #define | USB_RXCSRL7_STALLED 0x00000040 |
| #define | USB_RXCSRL7_REQPKT 0x00000020 |
| #define | USB_RXCSRL7_STALL 0x00000020 |
| #define | USB_RXCSRL7_FLUSH 0x00000010 |
| #define | USB_RXCSRL7_DATAERR 0x00000008 |
| #define | USB_RXCSRL7_NAKTO 0x00000008 |
| #define | USB_RXCSRL7_ERROR 0x00000004 |
| #define | USB_RXCSRL7_OVER 0x00000004 |
| #define | USB_RXCSRL7_FULL 0x00000002 |
| #define | USB_RXCSRL7_RXRDY 0x00000001 |
| #define | USB_RXCSRH7_AUTOCL 0x00000080 |
| #define | USB_RXCSRH7_ISO 0x00000040 |
| #define | USB_RXCSRH7_AUTORQ 0x00000040 |
| #define | USB_RXCSRH7_DMAEN 0x00000020 |
| #define | USB_RXCSRH7_PIDERR 0x00000010 |
| #define | USB_RXCSRH7_DISNYET 0x00000010 |
| #define | USB_RXCSRH7_DMAMOD 0x00000008 |
| #define | USB_RXCSRH7_DTWE 0x00000004 |
| #define | USB_RXCSRH7_DT 0x00000002 |
| #define | USB_RXCOUNT7_COUNT_M 0x00001FFF |
| #define | USB_RXCOUNT7_COUNT_S 0 |
| #define | USB_TXTYPE7_SPEED_M 0x000000C0 |
| #define | USB_TXTYPE7_SPEED_DFLT 0x00000000 |
| #define | USB_TXTYPE7_SPEED_FULL 0x00000080 |
| #define | USB_TXTYPE7_SPEED_LOW 0x000000C0 |
| #define | USB_TXTYPE7_PROTO_M 0x00000030 |
| #define | USB_TXTYPE7_PROTO_CTRL 0x00000000 |
| #define | USB_TXTYPE7_PROTO_ISOC 0x00000010 |
| #define | USB_TXTYPE7_PROTO_BULK 0x00000020 |
| #define | USB_TXTYPE7_PROTO_INT 0x00000030 |
| #define | USB_TXTYPE7_TEP_M 0x0000000F |
| #define | USB_TXTYPE7_TEP_S 0 |
| #define | USB_TXINTERVAL7_TXPOLL_M 0x000000FF |
| #define | USB_TXINTERVAL7_NAKLMT_M 0x000000FF |
| #define | USB_TXINTERVAL7_NAKLMT_S 0 |
| #define | USB_TXINTERVAL7_TXPOLL_S 0 |
| #define | USB_RXTYPE7_SPEED_M 0x000000C0 |
| #define | USB_RXTYPE7_SPEED_DFLT 0x00000000 |
| #define | USB_RXTYPE7_SPEED_FULL 0x00000080 |
| #define | USB_RXTYPE7_SPEED_LOW 0x000000C0 |
| #define | USB_RXTYPE7_PROTO_M 0x00000030 |
| #define | USB_RXTYPE7_PROTO_CTRL 0x00000000 |
| #define | USB_RXTYPE7_PROTO_ISOC 0x00000010 |
| #define | USB_RXTYPE7_PROTO_BULK 0x00000020 |
| #define | USB_RXTYPE7_PROTO_INT 0x00000030 |
| #define | USB_RXTYPE7_TEP_M 0x0000000F |
| #define | USB_RXTYPE7_TEP_S 0 |
| #define | USB_RXINTERVAL7_TXPOLL_M 0x000000FF |
| #define | USB_RXINTERVAL7_NAKLMT_M 0x000000FF |
| #define | USB_RXINTERVAL7_NAKLMT_S 0 |
| #define | USB_RXINTERVAL7_TXPOLL_S 0 |
| #define | USB_RQPKTCOUNT1_M 0x0000FFFF |
| #define | USB_RQPKTCOUNT1_S 0 |
| #define | USB_RQPKTCOUNT2_M 0x0000FFFF |
| #define | USB_RQPKTCOUNT2_S 0 |
| #define | USB_RQPKTCOUNT3_M 0x0000FFFF |
| #define | USB_RQPKTCOUNT3_S 0 |
| #define | USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF |
| #define | USB_RQPKTCOUNT4_COUNT_S 0 |
| #define | USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF |
| #define | USB_RQPKTCOUNT5_COUNT_S 0 |
| #define | USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF |
| #define | USB_RQPKTCOUNT6_COUNT_S 0 |
| #define | USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF |
| #define | USB_RQPKTCOUNT7_COUNT_S 0 |
| #define | USB_RXDPKTBUFDIS_EP7 0x00000080 |
| #define | USB_RXDPKTBUFDIS_EP6 0x00000040 |
| #define | USB_RXDPKTBUFDIS_EP5 0x00000020 |
| #define | USB_RXDPKTBUFDIS_EP4 0x00000010 |
| #define | USB_RXDPKTBUFDIS_EP3 0x00000008 |
| #define | USB_RXDPKTBUFDIS_EP2 0x00000004 |
| #define | USB_RXDPKTBUFDIS_EP1 0x00000002 |
| #define | USB_TXDPKTBUFDIS_EP7 0x00000080 |
| #define | USB_TXDPKTBUFDIS_EP6 0x00000040 |
| #define | USB_TXDPKTBUFDIS_EP5 0x00000020 |
| #define | USB_TXDPKTBUFDIS_EP4 0x00000010 |
| #define | USB_TXDPKTBUFDIS_EP3 0x00000008 |
| #define | USB_TXDPKTBUFDIS_EP2 0x00000004 |
| #define | USB_TXDPKTBUFDIS_EP1 0x00000002 |
| #define | USB_EPC_PFLTACT_M 0x00000300 |
| #define | USB_EPC_PFLTACT_UNCHG 0x00000000 |
| #define | USB_EPC_PFLTACT_TRIS 0x00000100 |
| #define | USB_EPC_PFLTACT_LOW 0x00000200 |
| #define | USB_EPC_PFLTACT_HIGH 0x00000300 |
| #define | USB_EPC_PFLTAEN 0x00000040 |
| #define | USB_EPC_PFLTSEN_HIGH 0x00000020 |
| #define | USB_EPC_PFLTEN 0x00000010 |
| #define | USB_EPC_EPENDE 0x00000004 |
| #define | USB_EPC_EPEN_M 0x00000003 |
| #define | USB_EPC_EPEN_LOW 0x00000000 |
| #define | USB_EPC_EPEN_HIGH 0x00000001 |
| #define | USB_EPC_EPEN_VBLOW 0x00000002 |
| #define | USB_EPC_EPEN_VBHIGH 0x00000003 |
| #define | USB_EPCRIS_PF 0x00000001 |
| #define | USB_EPCIM_PF 0x00000001 |
| #define | USB_EPCISC_PF 0x00000001 |
| #define | USB_DRRIS_RESUME 0x00000001 |
| #define | USB_DRIM_RESUME 0x00000001 |
| #define | USB_DRISC_RESUME 0x00000001 |
| #define | USB_GPCS_DEVMODOTG 0x00000002 |
| #define | USB_GPCS_DEVMOD 0x00000001 |
| #define | USB_VDC_VBDEN 0x00000001 |
| #define | USB_VDCRIS_VD 0x00000001 |
| #define | USB_VDCIM_VD 0x00000001 |
| #define | USB_VDCISC_VD 0x00000001 |
| #define | USB_IDVRIS_ID 0x00000001 |
| #define | USB_IDVIM_ID 0x00000001 |
| #define | USB_IDVISC_ID 0x00000001 |
| #define | USB_DMASEL_DMACTX_M 0x00F00000 |
| #define | USB_DMASEL_DMACRX_M 0x000F0000 |
| #define | USB_DMASEL_DMABTX_M 0x0000F000 |
| #define | USB_DMASEL_DMABRX_M 0x00000F00 |
| #define | USB_DMASEL_DMAATX_M 0x000000F0 |
| #define | USB_DMASEL_DMAARX_M 0x0000000F |
| #define | USB_DMASEL_DMACTX_S 20 |
| #define | USB_DMASEL_DMACRX_S 16 |
| #define | USB_DMASEL_DMABTX_S 12 |
| #define | USB_DMASEL_DMABRX_S 8 |
| #define | USB_DMASEL_DMAATX_S 4 |
| #define | USB_DMASEL_DMAARX_S 0 |
| #define | USB_PP_ECNT_M 0x0000FF00 |
| #define | USB_PP_USB_M 0x000000C0 |
| #define | USB_PP_USB_DEVICE 0x00000040 |
| #define | USB_PP_USB_HOSTDEVICE 0x00000080 |
| #define | USB_PP_USB_OTG 0x000000C0 |
| #define | USB_PP_PHY 0x00000010 |
| #define | USB_PP_TYPE_M 0x0000000F |
| #define | USB_PP_TYPE_0 0x00000000 |
| #define | USB_PP_ECNT_S 8 |
| #define | EEPROM_EESIZE_BLKCNT_M 0x07FF0000 |
| #define | EEPROM_EESIZE_WORDCNT_M 0x0000FFFF |
| #define | EEPROM_EESIZE_BLKCNT_S 16 |
| #define | EEPROM_EESIZE_WORDCNT_S 0 |
| #define | EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF |
| #define | EEPROM_EEBLOCK_BLOCK_S 0 |
| #define | EEPROM_EEOFFSET_OFFSET_M 0x0000000F |
| #define | EEPROM_EEOFFSET_OFFSET_S 0 |
| #define | EEPROM_EERDWR_VALUE_M 0xFFFFFFFF |
| #define | EEPROM_EERDWR_VALUE_S 0 |
| #define | EEPROM_EERDWRINC_VALUE_M 0xFFFFFFFF |
| #define | EEPROM_EERDWRINC_VALUE_S 0 |
| #define | EEPROM_EEDONE_WRBUSY 0x00000020 |
| #define | EEPROM_EEDONE_NOPERM 0x00000010 |
| #define | EEPROM_EEDONE_WKCOPY 0x00000008 |
| #define | EEPROM_EEDONE_WKERASE 0x00000004 |
| #define | EEPROM_EEDONE_WORKING 0x00000001 |
| #define | EEPROM_EESUPP_PRETRY 0x00000008 |
| #define | EEPROM_EESUPP_ERETRY 0x00000004 |
| #define | EEPROM_EEUNLOCK_UNLOCK_M 0xFFFFFFFF |
| #define | EEPROM_EEPROT_ACC 0x00000008 |
| #define | EEPROM_EEPROT_PROT_M 0x00000007 |
| #define | EEPROM_EEPROT_PROT_RWNPW 0x00000000 |
| #define | EEPROM_EEPROT_PROT_RWPW 0x00000001 |
| #define | EEPROM_EEPROT_PROT_RONPW 0x00000002 |
| #define | EEPROM_EEPASS0_PASS_M 0xFFFFFFFF |
| #define | EEPROM_EEPASS0_PASS_S 0 |
| #define | EEPROM_EEPASS1_PASS_M 0xFFFFFFFF |
| #define | EEPROM_EEPASS1_PASS_S 0 |
| #define | EEPROM_EEPASS2_PASS_M 0xFFFFFFFF |
| #define | EEPROM_EEPASS2_PASS_S 0 |
| #define | EEPROM_EEINT_INT 0x00000001 |
| #define | EEPROM_EEHIDE_HN_M 0xFFFFFFFE |
| #define | EEPROM_EEDBGME_KEY_M 0xFFFF0000 |
| #define | EEPROM_EEDBGME_ME 0x00000001 |
| #define | EEPROM_EEDBGME_KEY_S 16 |
| #define | EEPROM_PP_SIZE_M 0x0000001F |
| #define | EEPROM_PP_SIZE_S 0 |
| #define | SYSEXC_RIS_FPIXCRIS 0x00000020 |
| #define | SYSEXC_RIS_FPOFCRIS 0x00000010 |
| #define | SYSEXC_RIS_FPUFCRIS 0x00000008 |
| #define | SYSEXC_RIS_FPIOCRIS 0x00000004 |
| #define | SYSEXC_RIS_FPDZCRIS 0x00000002 |
| #define | SYSEXC_RIS_FPIDCRIS 0x00000001 |
| #define | SYSEXC_IM_FPIXCIM 0x00000020 |
| #define | SYSEXC_IM_FPOFCIM 0x00000010 |
| #define | SYSEXC_IM_FPUFCIM 0x00000008 |
| #define | SYSEXC_IM_FPIOCIM 0x00000004 |
| #define | SYSEXC_IM_FPDZCIM 0x00000002 |
| #define | SYSEXC_IM_FPIDCIM 0x00000001 |
| #define | SYSEXC_MIS_FPIXCMIS 0x00000020 |
| #define | SYSEXC_MIS_FPOFCMIS 0x00000010 |
| #define | SYSEXC_MIS_FPUFCMIS 0x00000008 |
| #define | SYSEXC_MIS_FPIOCMIS 0x00000004 |
| #define | SYSEXC_MIS_FPDZCMIS 0x00000002 |
| #define | SYSEXC_MIS_FPIDCMIS 0x00000001 |
| #define | SYSEXC_IC_FPIXCIC 0x00000020 |
| #define | SYSEXC_IC_FPOFCIC 0x00000010 |
| #define | SYSEXC_IC_FPUFCIC 0x00000008 |
| #define | SYSEXC_IC_FPIOCIC 0x00000004 |
| #define | SYSEXC_IC_FPDZCIC 0x00000002 |
| #define | SYSEXC_IC_FPIDCIC 0x00000001 |
| #define | HIB_RTCC_M 0xFFFFFFFF |
| #define | HIB_RTCC_S 0 |
| #define | HIB_RTCM0_M 0xFFFFFFFF |
| #define | HIB_RTCM0_S 0 |
| #define | HIB_RTCLD_M 0xFFFFFFFF |
| #define | HIB_RTCLD_S 0 |
| #define | HIB_CTL_WRC 0x80000000 |
| #define | HIB_CTL_OSCDRV 0x00020000 |
| #define | HIB_CTL_OSCBYP 0x00010000 |
| #define | HIB_CTL_VBATSEL_M 0x00006000 |
| #define | HIB_CTL_VBATSEL_1_9V 0x00000000 |
| #define | HIB_CTL_VBATSEL_2_1V 0x00002000 |
| #define | HIB_CTL_VBATSEL_2_3V 0x00004000 |
| #define | HIB_CTL_VBATSEL_2_5V 0x00006000 |
| #define | HIB_CTL_BATCHK 0x00000400 |
| #define | HIB_CTL_BATWKEN 0x00000200 |
| #define | HIB_CTL_VDD3ON 0x00000100 |
| #define | HIB_CTL_VABORT 0x00000080 |
| #define | HIB_CTL_CLK32EN 0x00000040 |
| #define | HIB_CTL_PINWEN 0x00000010 |
| #define | HIB_CTL_RTCWEN 0x00000008 |
| #define | HIB_CTL_HIBREQ 0x00000002 |
| #define | HIB_CTL_RTCEN 0x00000001 |
| #define | HIB_IM_WC 0x00000010 |
| #define | HIB_IM_EXTW 0x00000008 |
| #define | HIB_IM_LOWBAT 0x00000004 |
| #define | HIB_IM_RTCALT0 0x00000001 |
| #define | HIB_RIS_WC 0x00000010 |
| #define | HIB_RIS_EXTW 0x00000008 |
| #define | HIB_RIS_LOWBAT 0x00000004 |
| #define | HIB_RIS_RTCALT0 0x00000001 |
| #define | HIB_MIS_WC 0x00000010 |
| #define | HIB_MIS_EXTW 0x00000008 |
| #define | HIB_MIS_LOWBAT 0x00000004 |
| #define | HIB_MIS_RTCALT0 0x00000001 |
| #define | HIB_IC_WC 0x00000010 |
| #define | HIB_IC_EXTW 0x00000008 |
| #define | HIB_IC_LOWBAT 0x00000004 |
| #define | HIB_IC_RTCALT0 0x00000001 |
| #define | HIB_RTCT_TRIM_M 0x0000FFFF |
| #define | HIB_RTCT_TRIM_S 0 |
| #define | HIB_RTCSS_RTCSSM_M 0x7FFF0000 |
| #define | HIB_RTCSS_RTCSSC_M 0x00007FFF |
| #define | HIB_RTCSS_RTCSSM_S 16 |
| #define | HIB_RTCSS_RTCSSC_S 0 |
| #define | HIB_DATA_RTD_M 0xFFFFFFFF |
| #define | HIB_DATA_RTD_S 0 |
| #define | FLASH_FMA_OFFSET_M 0x0003FFFF |
| #define | FLASH_FMA_OFFSET_S 0 |
| #define | FLASH_FMD_DATA_M 0xFFFFFFFF |
| #define | FLASH_FMD_DATA_S 0 |
| #define | FLASH_FMC_WRKEY 0xA4420000 |
| #define | FLASH_FMC_COMT 0x00000008 |
| #define | FLASH_FMC_MERASE 0x00000004 |
| #define | FLASH_FMC_ERASE 0x00000002 |
| #define | FLASH_FMC_WRITE 0x00000001 |
| #define | FLASH_FCRIS_PROGRIS 0x00002000 |
| #define | FLASH_FCRIS_ERRIS 0x00000800 |
| #define | FLASH_FCRIS_INVDRIS 0x00000400 |
| #define | FLASH_FCRIS_VOLTRIS 0x00000200 |
| #define | FLASH_FCRIS_ERIS 0x00000004 |
| #define | FLASH_FCRIS_PRIS 0x00000002 |
| #define | FLASH_FCRIS_ARIS 0x00000001 |
| #define | FLASH_FCIM_PROGMASK 0x00002000 |
| #define | FLASH_FCIM_ERMASK 0x00000800 |
| #define | FLASH_FCIM_INVDMASK 0x00000400 |
| #define | FLASH_FCIM_VOLTMASK 0x00000200 |
| #define | FLASH_FCIM_EMASK 0x00000004 |
| #define | FLASH_FCIM_PMASK 0x00000002 |
| #define | FLASH_FCIM_AMASK 0x00000001 |
| #define | FLASH_FCMISC_PROGMISC 0x00002000 |
| #define | FLASH_FCMISC_ERMISC 0x00000800 |
| #define | FLASH_FCMISC_INVDMISC 0x00000400 |
| #define | FLASH_FCMISC_VOLTMISC 0x00000200 |
| #define | FLASH_FCMISC_EMISC 0x00000004 |
| #define | FLASH_FCMISC_PMISC 0x00000002 |
| #define | FLASH_FCMISC_AMISC 0x00000001 |
| #define | FLASH_FMC2_WRBUF 0x00000001 |
| #define | FLASH_FWBVAL_FWB_M 0xFFFFFFFF |
| #define | FLASH_FWBN_DATA_M 0xFFFFFFFF |
| #define | FLASH_FSIZE_SIZE_M 0x0000FFFF |
| #define | FLASH_FSIZE_SIZE_256KB 0x0000007F |
| #define | FLASH_SSIZE_SIZE_M 0x0000FFFF |
| #define | FLASH_SSIZE_SIZE_32KB 0x0000007F |
| #define | FLASH_ROMSWMAP_SAFERTOS 0x00000001 |
| #define | FLASH_RMCTL_BA 0x00000001 |
| #define | FLASH_BOOTCFG_NW 0x80000000 |
| #define | FLASH_BOOTCFG_PORT_M 0x0000E000 |
| #define | FLASH_BOOTCFG_PORT_A 0x00000000 |
| #define | FLASH_BOOTCFG_PORT_B 0x00002000 |
| #define | FLASH_BOOTCFG_PORT_C 0x00004000 |
| #define | FLASH_BOOTCFG_PORT_D 0x00006000 |
| #define | FLASH_BOOTCFG_PORT_E 0x00008000 |
| #define | FLASH_BOOTCFG_PORT_F 0x0000A000 |
| #define | FLASH_BOOTCFG_PORT_G 0x0000C000 |
| #define | FLASH_BOOTCFG_PORT_H 0x0000E000 |
| #define | FLASH_BOOTCFG_PIN_M 0x00001C00 |
| #define | FLASH_BOOTCFG_PIN_0 0x00000000 |
| #define | FLASH_BOOTCFG_PIN_1 0x00000400 |
| #define | FLASH_BOOTCFG_PIN_2 0x00000800 |
| #define | FLASH_BOOTCFG_PIN_3 0x00000C00 |
| #define | FLASH_BOOTCFG_PIN_4 0x00001000 |
| #define | FLASH_BOOTCFG_PIN_5 0x00001400 |
| #define | FLASH_BOOTCFG_PIN_6 0x00001800 |
| #define | FLASH_BOOTCFG_PIN_7 0x00001C00 |
| #define | FLASH_BOOTCFG_POL 0x00000200 |
| #define | FLASH_BOOTCFG_EN 0x00000100 |
| #define | FLASH_BOOTCFG_KEY 0x00000010 |
| #define | FLASH_BOOTCFG_DBG1 0x00000002 |
| #define | FLASH_BOOTCFG_DBG0 0x00000001 |
| #define | FLASH_USERREG0_DATA_M 0xFFFFFFFF |
| #define | FLASH_USERREG0_DATA_S 0 |
| #define | FLASH_USERREG1_DATA_M 0xFFFFFFFF |
| #define | FLASH_USERREG1_DATA_S 0 |
| #define | FLASH_USERREG2_DATA_M 0xFFFFFFFF |
| #define | FLASH_USERREG2_DATA_S 0 |
| #define | FLASH_USERREG3_DATA_M 0xFFFFFFFF |
| #define | FLASH_USERREG3_DATA_S 0 |
| #define | SYSCTL_DID0_VER_M 0x70000000 |
| #define | SYSCTL_DID0_VER_1 0x10000000 |
| #define | SYSCTL_DID0_CLASS_M 0x00FF0000 |
| #define | SYSCTL_DID0_CLASS_TM4C123 0x00050000 |
| #define | SYSCTL_DID0_MAJ_M 0x0000FF00 |
| #define | SYSCTL_DID0_MAJ_REVA 0x00000000 |
| #define | SYSCTL_DID0_MAJ_REVB 0x00000100 |
| #define | SYSCTL_DID0_MAJ_REVC 0x00000200 |
| #define | SYSCTL_DID0_MIN_M 0x000000FF |
| #define | SYSCTL_DID0_MIN_0 0x00000000 |
| #define | SYSCTL_DID0_MIN_1 0x00000001 |
| #define | SYSCTL_DID0_MIN_2 0x00000002 |
| #define | SYSCTL_DID1_VER_M 0xF0000000 |
| #define | SYSCTL_DID1_VER_1 0x10000000 |
| #define | SYSCTL_DID1_FAM_M 0x0F000000 |
| #define | SYSCTL_DID1_FAM_TIVA 0x00000000 |
| #define | SYSCTL_DID1_PRTNO_M 0x00FF0000 |
| #define | SYSCTL_DID1_PRTNO_TM4C123GH6PGE 0x00C50000 |
| #define | SYSCTL_DID1_PINCNT_M 0x0000E000 |
| #define | SYSCTL_DID1_PINCNT_100 0x00004000 |
| #define | SYSCTL_DID1_PINCNT_64 0x00006000 |
| #define | SYSCTL_DID1_PINCNT_144 0x00008000 |
| #define | SYSCTL_DID1_PINCNT_157 0x0000A000 |
| #define | SYSCTL_DID1_PINCNT_128 0x0000C000 |
| #define | SYSCTL_DID1_TEMP_M 0x000000E0 |
| #define | SYSCTL_DID1_TEMP_I 0x00000020 |
| #define | SYSCTL_DID1_TEMP_E 0x00000040 |
| #define | SYSCTL_DID1_TEMP_IE 0x00000060 |
| #define | SYSCTL_DID1_PKG_M 0x00000018 |
| #define | SYSCTL_DID1_PKG_QFP 0x00000008 |
| #define | SYSCTL_DID1_PKG_BGA 0x00000010 |
| #define | SYSCTL_DID1_ROHS 0x00000004 |
| #define | SYSCTL_DID1_QUAL_M 0x00000003 |
| #define | SYSCTL_DID1_QUAL_ES 0x00000000 |
| #define | SYSCTL_DID1_QUAL_PP 0x00000001 |
| #define | SYSCTL_DID1_QUAL_FQ 0x00000002 |
| #define | SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 |
| #define | SYSCTL_DC0_SRAMSZ_2KB 0x00070000 |
| #define | SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 |
| #define | SYSCTL_DC0_SRAMSZ_6KB 0x00170000 |
| #define | SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 |
| #define | SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 |
| #define | SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 |
| #define | SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 |
| #define | SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 |
| #define | SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 |
| #define | SYSCTL_DC0_FLASHSZ_M 0x0000FFFF |
| #define | SYSCTL_DC0_FLASHSZ_8KB 0x00000003 |
| #define | SYSCTL_DC0_FLASHSZ_16KB 0x00000007 |
| #define | SYSCTL_DC0_FLASHSZ_32KB 0x0000000F |
| #define | SYSCTL_DC0_FLASHSZ_64KB 0x0000001F |
| #define | SYSCTL_DC0_FLASHSZ_96KB 0x0000002F |
| #define | SYSCTL_DC0_FLASHSZ_128K 0x0000003F |
| #define | SYSCTL_DC0_FLASHSZ_192K 0x0000005F |
| #define | SYSCTL_DC0_FLASHSZ_256K 0x0000007F |
| #define | SYSCTL_DC1_WDT1 0x10000000 |
| #define | SYSCTL_DC1_CAN1 0x02000000 |
| #define | SYSCTL_DC1_CAN0 0x01000000 |
| #define | SYSCTL_DC1_PWM1 0x00200000 |
| #define | SYSCTL_DC1_PWM0 0x00100000 |
| #define | SYSCTL_DC1_ADC1 0x00020000 |
| #define | SYSCTL_DC1_ADC0 0x00010000 |
| #define | SYSCTL_DC1_MINSYSDIV_M 0x0000F000 |
| #define | SYSCTL_DC1_MINSYSDIV_80 0x00002000 |
| #define | SYSCTL_DC1_MINSYSDIV_50 0x00003000 |
| #define | SYSCTL_DC1_MINSYSDIV_40 0x00004000 |
| #define | SYSCTL_DC1_MINSYSDIV_25 0x00007000 |
| #define | SYSCTL_DC1_MINSYSDIV_20 0x00009000 |
| #define | SYSCTL_DC1_ADC1SPD_M 0x00000C00 |
| #define | SYSCTL_DC1_ADC1SPD_125K 0x00000000 |
| #define | SYSCTL_DC1_ADC1SPD_250K 0x00000400 |
| #define | SYSCTL_DC1_ADC1SPD_500K 0x00000800 |
| #define | SYSCTL_DC1_ADC1SPD_1M 0x00000C00 |
| #define | SYSCTL_DC1_ADC0SPD_M 0x00000300 |
| #define | SYSCTL_DC1_ADC0SPD_125K 0x00000000 |
| #define | SYSCTL_DC1_ADC0SPD_250K 0x00000100 |
| #define | SYSCTL_DC1_ADC0SPD_500K 0x00000200 |
| #define | SYSCTL_DC1_ADC0SPD_1M 0x00000300 |
| #define | SYSCTL_DC1_MPU 0x00000080 |
| #define | SYSCTL_DC1_HIB 0x00000040 |
| #define | SYSCTL_DC1_TEMP 0x00000020 |
| #define | SYSCTL_DC1_PLL 0x00000010 |
| #define | SYSCTL_DC1_WDT0 0x00000008 |
| #define | SYSCTL_DC1_SWO 0x00000004 |
| #define | SYSCTL_DC1_SWD 0x00000002 |
| #define | SYSCTL_DC1_JTAG 0x00000001 |
| #define | SYSCTL_DC2_EPI0 0x40000000 |
| #define | SYSCTL_DC2_I2S0 0x10000000 |
| #define | SYSCTL_DC2_COMP2 0x04000000 |
| #define | SYSCTL_DC2_COMP1 0x02000000 |
| #define | SYSCTL_DC2_COMP0 0x01000000 |
| #define | SYSCTL_DC2_TIMER3 0x00080000 |
| #define | SYSCTL_DC2_TIMER2 0x00040000 |
| #define | SYSCTL_DC2_TIMER1 0x00020000 |
| #define | SYSCTL_DC2_TIMER0 0x00010000 |
| #define | SYSCTL_DC2_I2C1HS 0x00008000 |
| #define | SYSCTL_DC2_I2C1 0x00004000 |
| #define | SYSCTL_DC2_I2C0HS 0x00002000 |
| #define | SYSCTL_DC2_I2C0 0x00001000 |
| #define | SYSCTL_DC2_QEI1 0x00000200 |
| #define | SYSCTL_DC2_QEI0 0x00000100 |
| #define | SYSCTL_DC2_SSI1 0x00000020 |
| #define | SYSCTL_DC2_SSI0 0x00000010 |
| #define | SYSCTL_DC2_UART2 0x00000004 |
| #define | SYSCTL_DC2_UART1 0x00000002 |
| #define | SYSCTL_DC2_UART0 0x00000001 |
| #define | SYSCTL_DC3_32KHZ 0x80000000 |
| #define | SYSCTL_DC3_CCP5 0x20000000 |
| #define | SYSCTL_DC3_CCP4 0x10000000 |
| #define | SYSCTL_DC3_CCP3 0x08000000 |
| #define | SYSCTL_DC3_CCP2 0x04000000 |
| #define | SYSCTL_DC3_CCP1 0x02000000 |
| #define | SYSCTL_DC3_CCP0 0x01000000 |
| #define | SYSCTL_DC3_ADC0AIN7 0x00800000 |
| #define | SYSCTL_DC3_ADC0AIN6 0x00400000 |
| #define | SYSCTL_DC3_ADC0AIN5 0x00200000 |
| #define | SYSCTL_DC3_ADC0AIN4 0x00100000 |
| #define | SYSCTL_DC3_ADC0AIN3 0x00080000 |
| #define | SYSCTL_DC3_ADC0AIN2 0x00040000 |
| #define | SYSCTL_DC3_ADC0AIN1 0x00020000 |
| #define | SYSCTL_DC3_ADC0AIN0 0x00010000 |
| #define | SYSCTL_DC3_PWMFAULT 0x00008000 |
| #define | SYSCTL_DC3_C2O 0x00004000 |
| #define | SYSCTL_DC3_C2PLUS 0x00002000 |
| #define | SYSCTL_DC3_C2MINUS 0x00001000 |
| #define | SYSCTL_DC3_C1O 0x00000800 |
| #define | SYSCTL_DC3_C1PLUS 0x00000400 |
| #define | SYSCTL_DC3_C1MINUS 0x00000200 |
| #define | SYSCTL_DC3_C0O 0x00000100 |
| #define | SYSCTL_DC3_C0PLUS 0x00000080 |
| #define | SYSCTL_DC3_C0MINUS 0x00000040 |
| #define | SYSCTL_DC3_PWM5 0x00000020 |
| #define | SYSCTL_DC3_PWM4 0x00000010 |
| #define | SYSCTL_DC3_PWM3 0x00000008 |
| #define | SYSCTL_DC3_PWM2 0x00000004 |
| #define | SYSCTL_DC3_PWM1 0x00000002 |
| #define | SYSCTL_DC3_PWM0 0x00000001 |
| #define | SYSCTL_DC4_EPHY0 0x40000000 |
| #define | SYSCTL_DC4_EMAC0 0x10000000 |
| #define | SYSCTL_DC4_E1588 0x01000000 |
| #define | SYSCTL_DC4_PICAL 0x00040000 |
| #define | SYSCTL_DC4_CCP7 0x00008000 |
| #define | SYSCTL_DC4_CCP6 0x00004000 |
| #define | SYSCTL_DC4_UDMA 0x00002000 |
| #define | SYSCTL_DC4_ROM 0x00001000 |
| #define | SYSCTL_DC4_GPIOJ 0x00000100 |
| #define | SYSCTL_DC4_GPIOH 0x00000080 |
| #define | SYSCTL_DC4_GPIOG 0x00000040 |
| #define | SYSCTL_DC4_GPIOF 0x00000020 |
| #define | SYSCTL_DC4_GPIOE 0x00000010 |
| #define | SYSCTL_DC4_GPIOD 0x00000008 |
| #define | SYSCTL_DC4_GPIOC 0x00000004 |
| #define | SYSCTL_DC4_GPIOB 0x00000002 |
| #define | SYSCTL_DC4_GPIOA 0x00000001 |
| #define | SYSCTL_DC5_PWMFAULT3 0x08000000 |
| #define | SYSCTL_DC5_PWMFAULT2 0x04000000 |
| #define | SYSCTL_DC5_PWMFAULT1 0x02000000 |
| #define | SYSCTL_DC5_PWMFAULT0 0x01000000 |
| #define | SYSCTL_DC5_PWMEFLT 0x00200000 |
| #define | SYSCTL_DC5_PWMESYNC 0x00100000 |
| #define | SYSCTL_DC5_PWM7 0x00000080 |
| #define | SYSCTL_DC5_PWM6 0x00000040 |
| #define | SYSCTL_DC5_PWM5 0x00000020 |
| #define | SYSCTL_DC5_PWM4 0x00000010 |
| #define | SYSCTL_DC5_PWM3 0x00000008 |
| #define | SYSCTL_DC5_PWM2 0x00000004 |
| #define | SYSCTL_DC5_PWM1 0x00000002 |
| #define | SYSCTL_DC5_PWM0 0x00000001 |
| #define | SYSCTL_DC6_USB0PHY 0x00000010 |
| #define | SYSCTL_DC6_USB0_M 0x00000003 |
| #define | SYSCTL_DC6_USB0_DEV 0x00000001 |
| #define | SYSCTL_DC6_USB0_HOSTDEV 0x00000002 |
| #define | SYSCTL_DC6_USB0_OTG 0x00000003 |
| #define | SYSCTL_DC7_DMACH30 0x40000000 |
| #define | SYSCTL_DC7_DMACH29 0x20000000 |
| #define | SYSCTL_DC7_DMACH28 0x10000000 |
| #define | SYSCTL_DC7_DMACH27 0x08000000 |
| #define | SYSCTL_DC7_DMACH26 0x04000000 |
| #define | SYSCTL_DC7_DMACH25 0x02000000 |
| #define | SYSCTL_DC7_DMACH24 0x01000000 |
| #define | SYSCTL_DC7_DMACH23 0x00800000 |
| #define | SYSCTL_DC7_DMACH22 0x00400000 |
| #define | SYSCTL_DC7_DMACH21 0x00200000 |
| #define | SYSCTL_DC7_DMACH20 0x00100000 |
| #define | SYSCTL_DC7_DMACH19 0x00080000 |
| #define | SYSCTL_DC7_DMACH18 0x00040000 |
| #define | SYSCTL_DC7_DMACH17 0x00020000 |
| #define | SYSCTL_DC7_DMACH16 0x00010000 |
| #define | SYSCTL_DC7_DMACH15 0x00008000 |
| #define | SYSCTL_DC7_DMACH14 0x00004000 |
| #define | SYSCTL_DC7_DMACH13 0x00002000 |
| #define | SYSCTL_DC7_DMACH12 0x00001000 |
| #define | SYSCTL_DC7_DMACH11 0x00000800 |
| #define | SYSCTL_DC7_DMACH10 0x00000400 |
| #define | SYSCTL_DC7_DMACH9 0x00000200 |
| #define | SYSCTL_DC7_DMACH8 0x00000100 |
| #define | SYSCTL_DC7_DMACH7 0x00000080 |
| #define | SYSCTL_DC7_DMACH6 0x00000040 |
| #define | SYSCTL_DC7_DMACH5 0x00000020 |
| #define | SYSCTL_DC7_DMACH4 0x00000010 |
| #define | SYSCTL_DC7_DMACH3 0x00000008 |
| #define | SYSCTL_DC7_DMACH2 0x00000004 |
| #define | SYSCTL_DC7_DMACH1 0x00000002 |
| #define | SYSCTL_DC7_DMACH0 0x00000001 |
| #define | SYSCTL_DC8_ADC1AIN15 0x80000000 |
| #define | SYSCTL_DC8_ADC1AIN14 0x40000000 |
| #define | SYSCTL_DC8_ADC1AIN13 0x20000000 |
| #define | SYSCTL_DC8_ADC1AIN12 0x10000000 |
| #define | SYSCTL_DC8_ADC1AIN11 0x08000000 |
| #define | SYSCTL_DC8_ADC1AIN10 0x04000000 |
| #define | SYSCTL_DC8_ADC1AIN9 0x02000000 |
| #define | SYSCTL_DC8_ADC1AIN8 0x01000000 |
| #define | SYSCTL_DC8_ADC1AIN7 0x00800000 |
| #define | SYSCTL_DC8_ADC1AIN6 0x00400000 |
| #define | SYSCTL_DC8_ADC1AIN5 0x00200000 |
| #define | SYSCTL_DC8_ADC1AIN4 0x00100000 |
| #define | SYSCTL_DC8_ADC1AIN3 0x00080000 |
| #define | SYSCTL_DC8_ADC1AIN2 0x00040000 |
| #define | SYSCTL_DC8_ADC1AIN1 0x00020000 |
| #define | SYSCTL_DC8_ADC1AIN0 0x00010000 |
| #define | SYSCTL_DC8_ADC0AIN15 0x00008000 |
| #define | SYSCTL_DC8_ADC0AIN14 0x00004000 |
| #define | SYSCTL_DC8_ADC0AIN13 0x00002000 |
| #define | SYSCTL_DC8_ADC0AIN12 0x00001000 |
| #define | SYSCTL_DC8_ADC0AIN11 0x00000800 |
| #define | SYSCTL_DC8_ADC0AIN10 0x00000400 |
| #define | SYSCTL_DC8_ADC0AIN9 0x00000200 |
| #define | SYSCTL_DC8_ADC0AIN8 0x00000100 |
| #define | SYSCTL_DC8_ADC0AIN7 0x00000080 |
| #define | SYSCTL_DC8_ADC0AIN6 0x00000040 |
| #define | SYSCTL_DC8_ADC0AIN5 0x00000020 |
| #define | SYSCTL_DC8_ADC0AIN4 0x00000010 |
| #define | SYSCTL_DC8_ADC0AIN3 0x00000008 |
| #define | SYSCTL_DC8_ADC0AIN2 0x00000004 |
| #define | SYSCTL_DC8_ADC0AIN1 0x00000002 |
| #define | SYSCTL_DC8_ADC0AIN0 0x00000001 |
| #define | SYSCTL_PBORCTL_BOR0 0x00000004 |
| #define | SYSCTL_PBORCTL_BOR1 0x00000002 |
| #define | SYSCTL_SRCR0_WDT1 0x10000000 |
| #define | SYSCTL_SRCR0_CAN1 0x02000000 |
| #define | SYSCTL_SRCR0_CAN0 0x01000000 |
| #define | SYSCTL_SRCR0_PWM0 0x00100000 |
| #define | SYSCTL_SRCR0_ADC1 0x00020000 |
| #define | SYSCTL_SRCR0_ADC0 0x00010000 |
| #define | SYSCTL_SRCR0_HIB 0x00000040 |
| #define | SYSCTL_SRCR0_WDT0 0x00000008 |
| #define | SYSCTL_SRCR1_COMP2 0x04000000 |
| #define | SYSCTL_SRCR1_COMP1 0x02000000 |
| #define | SYSCTL_SRCR1_COMP0 0x01000000 |
| #define | SYSCTL_SRCR1_TIMER3 0x00080000 |
| #define | SYSCTL_SRCR1_TIMER2 0x00040000 |
| #define | SYSCTL_SRCR1_TIMER1 0x00020000 |
| #define | SYSCTL_SRCR1_TIMER0 0x00010000 |
| #define | SYSCTL_SRCR1_I2C1 0x00004000 |
| #define | SYSCTL_SRCR1_I2C0 0x00001000 |
| #define | SYSCTL_SRCR1_QEI1 0x00000200 |
| #define | SYSCTL_SRCR1_QEI0 0x00000100 |
| #define | SYSCTL_SRCR1_SSI1 0x00000020 |
| #define | SYSCTL_SRCR1_SSI0 0x00000010 |
| #define | SYSCTL_SRCR1_UART2 0x00000004 |
| #define | SYSCTL_SRCR1_UART1 0x00000002 |
| #define | SYSCTL_SRCR1_UART0 0x00000001 |
| #define | SYSCTL_SRCR2_USB0 0x00010000 |
| #define | SYSCTL_SRCR2_UDMA 0x00002000 |
| #define | SYSCTL_SRCR2_GPIOJ 0x00000100 |
| #define | SYSCTL_SRCR2_GPIOH 0x00000080 |
| #define | SYSCTL_SRCR2_GPIOG 0x00000040 |
| #define | SYSCTL_SRCR2_GPIOF 0x00000020 |
| #define | SYSCTL_SRCR2_GPIOE 0x00000010 |
| #define | SYSCTL_SRCR2_GPIOD 0x00000008 |
| #define | SYSCTL_SRCR2_GPIOC 0x00000004 |
| #define | SYSCTL_SRCR2_GPIOB 0x00000002 |
| #define | SYSCTL_SRCR2_GPIOA 0x00000001 |
| #define | SYSCTL_RIS_BOR0RIS 0x00000800 |
| #define | SYSCTL_RIS_VDDARIS 0x00000400 |
| #define | SYSCTL_RIS_MOSCPUPRIS 0x00000100 |
| #define | SYSCTL_RIS_USBPLLLRIS 0x00000080 |
| #define | SYSCTL_RIS_PLLLRIS 0x00000040 |
| #define | SYSCTL_RIS_MOFRIS 0x00000008 |
| #define | SYSCTL_RIS_BOR1RIS 0x00000002 |
| #define | SYSCTL_IMC_BOR0IM 0x00000800 |
| #define | SYSCTL_IMC_VDDAIM 0x00000400 |
| #define | SYSCTL_IMC_MOSCPUPIM 0x00000100 |
| #define | SYSCTL_IMC_USBPLLLIM 0x00000080 |
| #define | SYSCTL_IMC_PLLLIM 0x00000040 |
| #define | SYSCTL_IMC_MOFIM 0x00000008 |
| #define | SYSCTL_IMC_BOR1IM 0x00000002 |
| #define | SYSCTL_MISC_BOR0MIS 0x00000800 |
| #define | SYSCTL_MISC_VDDAMIS 0x00000400 |
| #define | SYSCTL_MISC_MOSCPUPMIS 0x00000100 |
| #define | SYSCTL_MISC_USBPLLLMIS 0x00000080 |
| #define | SYSCTL_MISC_PLLLMIS 0x00000040 |
| #define | SYSCTL_MISC_MOFMIS 0x00000008 |
| #define | SYSCTL_MISC_BOR1MIS 0x00000002 |
| #define | SYSCTL_RESC_MOSCFAIL 0x00010000 |
| #define | SYSCTL_RESC_WDT1 0x00000020 |
| #define | SYSCTL_RESC_SW 0x00000010 |
| #define | SYSCTL_RESC_WDT0 0x00000008 |
| #define | SYSCTL_RESC_BOR 0x00000004 |
| #define | SYSCTL_RESC_POR 0x00000002 |
| #define | SYSCTL_RESC_EXT 0x00000001 |
| #define | SYSCTL_RCC_ACG 0x08000000 |
| #define | SYSCTL_RCC_SYSDIV_M 0x07800000 |
| #define | SYSCTL_RCC_USESYSDIV 0x00400000 |
| #define | SYSCTL_RCC_USEPWMDIV 0x00100000 |
| #define | SYSCTL_RCC_PWMDIV_M 0x000E0000 |
| #define | SYSCTL_RCC_PWMDIV_2 0x00000000 |
| #define | SYSCTL_RCC_PWMDIV_4 0x00020000 |
| #define | SYSCTL_RCC_PWMDIV_8 0x00040000 |
| #define | SYSCTL_RCC_PWMDIV_16 0x00060000 |
| #define | SYSCTL_RCC_PWMDIV_32 0x00080000 |
| #define | SYSCTL_RCC_PWMDIV_64 0x000A0000 |
| #define | SYSCTL_RCC_PWRDN 0x00002000 |
| #define | SYSCTL_RCC_BYPASS 0x00000800 |
| #define | SYSCTL_RCC_XTAL_M 0x000007C0 |
| #define | SYSCTL_RCC_XTAL_4MHZ 0x00000180 |
| #define | SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 |
| #define | SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 |
| #define | SYSCTL_RCC_XTAL_5MHZ 0x00000240 |
| #define | SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 |
| #define | SYSCTL_RCC_XTAL_6MHZ 0x000002C0 |
| #define | SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 |
| #define | SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 |
| #define | SYSCTL_RCC_XTAL_8MHZ 0x00000380 |
| #define | SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 |
| #define | SYSCTL_RCC_XTAL_10MHZ 0x00000400 |
| #define | SYSCTL_RCC_XTAL_12MHZ 0x00000440 |
| #define | SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 |
| #define | SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 |
| #define | SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 |
| #define | SYSCTL_RCC_XTAL_16MHZ 0x00000540 |
| #define | SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 |
| #define | SYSCTL_RCC_XTAL_18MHZ 0x000005C0 |
| #define | SYSCTL_RCC_XTAL_20MHZ 0x00000600 |
| #define | SYSCTL_RCC_XTAL_24MHZ 0x00000640 |
| #define | SYSCTL_RCC_XTAL_25MHZ 0x00000680 |
| #define | SYSCTL_RCC_OSCSRC_M 0x00000030 |
| #define | SYSCTL_RCC_OSCSRC_MAIN 0x00000000 |
| #define | SYSCTL_RCC_OSCSRC_INT 0x00000010 |
| #define | SYSCTL_RCC_OSCSRC_INT4 0x00000020 |
| #define | SYSCTL_RCC_OSCSRC_30 0x00000030 |
| #define | SYSCTL_RCC_MOSCDIS 0x00000001 |
| #define | SYSCTL_RCC_SYSDIV_S 23 |
| #define | SYSCTL_GPIOHBCTL_PORTJ 0x00000100 |
| #define | SYSCTL_GPIOHBCTL_PORTH 0x00000080 |
| #define | SYSCTL_GPIOHBCTL_PORTG 0x00000040 |
| #define | SYSCTL_GPIOHBCTL_PORTF 0x00000020 |
| #define | SYSCTL_GPIOHBCTL_PORTE 0x00000010 |
| #define | SYSCTL_GPIOHBCTL_PORTD 0x00000008 |
| #define | SYSCTL_GPIOHBCTL_PORTC 0x00000004 |
| #define | SYSCTL_GPIOHBCTL_PORTB 0x00000002 |
| #define | SYSCTL_GPIOHBCTL_PORTA 0x00000001 |
| #define | SYSCTL_RCC2_USERCC2 0x80000000 |
| #define | SYSCTL_RCC2_DIV400 0x40000000 |
| #define | SYSCTL_RCC2_SYSDIV2_M 0x1F800000 |
| #define | SYSCTL_RCC2_SYSDIV2LSB 0x00400000 |
| #define | SYSCTL_RCC2_USBPWRDN 0x00004000 |
| #define | SYSCTL_RCC2_PWRDN2 0x00002000 |
| #define | SYSCTL_RCC2_BYPASS2 0x00000800 |
| #define | SYSCTL_RCC2_OSCSRC2_M 0x00000070 |
| #define | SYSCTL_RCC2_OSCSRC2_MO 0x00000000 |
| #define | SYSCTL_RCC2_OSCSRC2_IO 0x00000010 |
| #define | SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 |
| #define | SYSCTL_RCC2_OSCSRC2_30 0x00000030 |
| #define | SYSCTL_RCC2_OSCSRC2_32 0x00000070 |
| #define | SYSCTL_RCC2_SYSDIV2_S 23 |
| #define | SYSCTL_MOSCCTL_NOXTAL 0x00000004 |
| #define | SYSCTL_MOSCCTL_MOSCIM 0x00000002 |
| #define | SYSCTL_MOSCCTL_CVAL 0x00000001 |
| #define | SYSCTL_RCGC0_WDT1 0x10000000 |
| #define | SYSCTL_RCGC0_CAN1 0x02000000 |
| #define | SYSCTL_RCGC0_CAN0 0x01000000 |
| #define | SYSCTL_RCGC0_PWM0 0x00100000 |
| #define | SYSCTL_RCGC0_ADC1 0x00020000 |
| #define | SYSCTL_RCGC0_ADC0 0x00010000 |
| #define | SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 |
| #define | SYSCTL_RCGC0_ADC1SPD_125K 0x00000000 |
| #define | SYSCTL_RCGC0_ADC1SPD_250K 0x00000400 |
| #define | SYSCTL_RCGC0_ADC1SPD_500K 0x00000800 |
| #define | SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 |
| #define | SYSCTL_RCGC0_ADC0SPD_M 0x00000300 |
| #define | SYSCTL_RCGC0_ADC0SPD_125K 0x00000000 |
| #define | SYSCTL_RCGC0_ADC0SPD_250K 0x00000100 |
| #define | SYSCTL_RCGC0_ADC0SPD_500K 0x00000200 |
| #define | SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 |
| #define | SYSCTL_RCGC0_HIB 0x00000040 |
| #define | SYSCTL_RCGC0_WDT0 0x00000008 |
| #define | SYSCTL_RCGC1_COMP2 0x04000000 |
| #define | SYSCTL_RCGC1_COMP1 0x02000000 |
| #define | SYSCTL_RCGC1_COMP0 0x01000000 |
| #define | SYSCTL_RCGC1_TIMER3 0x00080000 |
| #define | SYSCTL_RCGC1_TIMER2 0x00040000 |
| #define | SYSCTL_RCGC1_TIMER1 0x00020000 |
| #define | SYSCTL_RCGC1_TIMER0 0x00010000 |
| #define | SYSCTL_RCGC1_I2C1 0x00004000 |
| #define | SYSCTL_RCGC1_I2C0 0x00001000 |
| #define | SYSCTL_RCGC1_QEI1 0x00000200 |
| #define | SYSCTL_RCGC1_QEI0 0x00000100 |
| #define | SYSCTL_RCGC1_SSI1 0x00000020 |
| #define | SYSCTL_RCGC1_SSI0 0x00000010 |
| #define | SYSCTL_RCGC1_UART2 0x00000004 |
| #define | SYSCTL_RCGC1_UART1 0x00000002 |
| #define | SYSCTL_RCGC1_UART0 0x00000001 |
| #define | SYSCTL_RCGC2_USB0 0x00010000 |
| #define | SYSCTL_RCGC2_UDMA 0x00002000 |
| #define | SYSCTL_RCGC2_GPIOJ 0x00000100 |
| #define | SYSCTL_RCGC2_GPIOH 0x00000080 |
| #define | SYSCTL_RCGC2_GPIOG 0x00000040 |
| #define | SYSCTL_RCGC2_GPIOF 0x00000020 |
| #define | SYSCTL_RCGC2_GPIOE 0x00000010 |
| #define | SYSCTL_RCGC2_GPIOD 0x00000008 |
| #define | SYSCTL_RCGC2_GPIOC 0x00000004 |
| #define | SYSCTL_RCGC2_GPIOB 0x00000002 |
| #define | SYSCTL_RCGC2_GPIOA 0x00000001 |
| #define | SYSCTL_SCGC0_WDT1 0x10000000 |
| #define | SYSCTL_SCGC0_CAN1 0x02000000 |
| #define | SYSCTL_SCGC0_CAN0 0x01000000 |
| #define | SYSCTL_SCGC0_PWM0 0x00100000 |
| #define | SYSCTL_SCGC0_ADC1 0x00020000 |
| #define | SYSCTL_SCGC0_ADC0 0x00010000 |
| #define | SYSCTL_SCGC0_HIB 0x00000040 |
| #define | SYSCTL_SCGC0_WDT0 0x00000008 |
| #define | SYSCTL_SCGC1_COMP2 0x04000000 |
| #define | SYSCTL_SCGC1_COMP1 0x02000000 |
| #define | SYSCTL_SCGC1_COMP0 0x01000000 |
| #define | SYSCTL_SCGC1_TIMER3 0x00080000 |
| #define | SYSCTL_SCGC1_TIMER2 0x00040000 |
| #define | SYSCTL_SCGC1_TIMER1 0x00020000 |
| #define | SYSCTL_SCGC1_TIMER0 0x00010000 |
| #define | SYSCTL_SCGC1_I2C1 0x00004000 |
| #define | SYSCTL_SCGC1_I2C0 0x00001000 |
| #define | SYSCTL_SCGC1_QEI1 0x00000200 |
| #define | SYSCTL_SCGC1_QEI0 0x00000100 |
| #define | SYSCTL_SCGC1_SSI1 0x00000020 |
| #define | SYSCTL_SCGC1_SSI0 0x00000010 |
| #define | SYSCTL_SCGC1_UART2 0x00000004 |
| #define | SYSCTL_SCGC1_UART1 0x00000002 |
| #define | SYSCTL_SCGC1_UART0 0x00000001 |
| #define | SYSCTL_SCGC2_USB0 0x00010000 |
| #define | SYSCTL_SCGC2_UDMA 0x00002000 |
| #define | SYSCTL_SCGC2_GPIOJ 0x00000100 |
| #define | SYSCTL_SCGC2_GPIOH 0x00000080 |
| #define | SYSCTL_SCGC2_GPIOG 0x00000040 |
| #define | SYSCTL_SCGC2_GPIOF 0x00000020 |
| #define | SYSCTL_SCGC2_GPIOE 0x00000010 |
| #define | SYSCTL_SCGC2_GPIOD 0x00000008 |
| #define | SYSCTL_SCGC2_GPIOC 0x00000004 |
| #define | SYSCTL_SCGC2_GPIOB 0x00000002 |
| #define | SYSCTL_SCGC2_GPIOA 0x00000001 |
| #define | SYSCTL_DCGC0_WDT1 0x10000000 |
| #define | SYSCTL_DCGC0_CAN1 0x02000000 |
| #define | SYSCTL_DCGC0_CAN0 0x01000000 |
| #define | SYSCTL_DCGC0_PWM0 0x00100000 |
| #define | SYSCTL_DCGC0_ADC1 0x00020000 |
| #define | SYSCTL_DCGC0_ADC0 0x00010000 |
| #define | SYSCTL_DCGC0_HIB 0x00000040 |
| #define | SYSCTL_DCGC0_WDT0 0x00000008 |
| #define | SYSCTL_DCGC1_COMP2 0x04000000 |
| #define | SYSCTL_DCGC1_COMP1 0x02000000 |
| #define | SYSCTL_DCGC1_COMP0 0x01000000 |
| #define | SYSCTL_DCGC1_TIMER3 0x00080000 |
| #define | SYSCTL_DCGC1_TIMER2 0x00040000 |
| #define | SYSCTL_DCGC1_TIMER1 0x00020000 |
| #define | SYSCTL_DCGC1_TIMER0 0x00010000 |
| #define | SYSCTL_DCGC1_I2C1 0x00004000 |
| #define | SYSCTL_DCGC1_I2C0 0x00001000 |
| #define | SYSCTL_DCGC1_QEI1 0x00000200 |
| #define | SYSCTL_DCGC1_QEI0 0x00000100 |
| #define | SYSCTL_DCGC1_SSI1 0x00000020 |
| #define | SYSCTL_DCGC1_SSI0 0x00000010 |
| #define | SYSCTL_DCGC1_UART2 0x00000004 |
| #define | SYSCTL_DCGC1_UART1 0x00000002 |
| #define | SYSCTL_DCGC1_UART0 0x00000001 |
| #define | SYSCTL_DCGC2_USB0 0x00010000 |
| #define | SYSCTL_DCGC2_UDMA 0x00002000 |
| #define | SYSCTL_DCGC2_GPIOJ 0x00000100 |
| #define | SYSCTL_DCGC2_GPIOH 0x00000080 |
| #define | SYSCTL_DCGC2_GPIOG 0x00000040 |
| #define | SYSCTL_DCGC2_GPIOF 0x00000020 |
| #define | SYSCTL_DCGC2_GPIOE 0x00000010 |
| #define | SYSCTL_DCGC2_GPIOD 0x00000008 |
| #define | SYSCTL_DCGC2_GPIOC 0x00000004 |
| #define | SYSCTL_DCGC2_GPIOB 0x00000002 |
| #define | SYSCTL_DCGC2_GPIOA 0x00000001 |
| #define | SYSCTL_DSLPCLKCFG_D_M 0x1F800000 |
| #define | SYSCTL_DSLPCLKCFG_O_M 0x00000070 |
| #define | SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 |
| #define | SYSCTL_DSLPCLKCFG_O_IO 0x00000010 |
| #define | SYSCTL_DSLPCLKCFG_O_30 0x00000030 |
| #define | SYSCTL_DSLPCLKCFG_O_32 0x00000070 |
| #define | SYSCTL_DSLPCLKCFG_PIOSCPD 0x00000002 |
| #define | SYSCTL_DSLPCLKCFG_D_S 23 |
| #define | SYSCTL_SYSPROP_FPU 0x00000001 |
| #define | SYSCTL_PIOSCCAL_UTEN 0x80000000 |
| #define | SYSCTL_PIOSCCAL_CAL 0x00000200 |
| #define | SYSCTL_PIOSCCAL_UPDATE 0x00000100 |
| #define | SYSCTL_PIOSCCAL_UT_M 0x0000007F |
| #define | SYSCTL_PIOSCCAL_UT_S 0 |
| #define | SYSCTL_PIOSCSTAT_DT_M 0x007F0000 |
| #define | SYSCTL_PIOSCSTAT_CR_M 0x00000300 |
| #define | SYSCTL_PIOSCSTAT_CRNONE 0x00000000 |
| #define | SYSCTL_PIOSCSTAT_CRPASS 0x00000100 |
| #define | SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 |
| #define | SYSCTL_PIOSCSTAT_CT_M 0x0000007F |
| #define | SYSCTL_PIOSCSTAT_DT_S 16 |
| #define | SYSCTL_PIOSCSTAT_CT_S 0 |
| #define | SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 |
| #define | SYSCTL_PLLFREQ0_MINT_M 0x000003FF |
| #define | SYSCTL_PLLFREQ0_MFRAC_S 10 |
| #define | SYSCTL_PLLFREQ0_MINT_S 0 |
| #define | SYSCTL_PLLFREQ1_Q_M 0x00001F00 |
| #define | SYSCTL_PLLFREQ1_N_M 0x0000001F |
| #define | SYSCTL_PLLFREQ1_Q_S 8 |
| #define | SYSCTL_PLLFREQ1_N_S 0 |
| #define | SYSCTL_PLLSTAT_LOCK 0x00000001 |
| #define | SYSCTL_SLPPWRCFG_FLASHPM_M 0x00000030 |
| #define | SYSCTL_SLPPWRCFG_FLASHPM_NRM 0x00000000 |
| #define | SYSCTL_SLPPWRCFG_FLASHPM_SLP 0x00000020 |
| #define | SYSCTL_SLPPWRCFG_SRAMPM_M 0x00000003 |
| #define | SYSCTL_SLPPWRCFG_SRAMPM_NRM 0x00000000 |
| #define | SYSCTL_SLPPWRCFG_SRAMPM_SBY 0x00000001 |
| #define | SYSCTL_SLPPWRCFG_SRAMPM_LP 0x00000003 |
| #define | SYSCTL_DSLPPWRCFG_FLASHPM_M 0x00000030 |
| #define | SYSCTL_DSLPPWRCFG_FLASHPM_NRM 0x00000000 |
| #define | SYSCTL_DSLPPWRCFG_FLASHPM_SLP 0x00000020 |
| #define | SYSCTL_DSLPPWRCFG_SRAMPM_M 0x00000003 |
| #define | SYSCTL_DSLPPWRCFG_SRAMPM_NRM 0x00000000 |
| #define | SYSCTL_DSLPPWRCFG_SRAMPM_SBY 0x00000001 |
| #define | SYSCTL_DSLPPWRCFG_SRAMPM_LP 0x00000003 |
| #define | SYSCTL_DC9_ADC1DC7 0x00800000 |
| #define | SYSCTL_DC9_ADC1DC6 0x00400000 |
| #define | SYSCTL_DC9_ADC1DC5 0x00200000 |
| #define | SYSCTL_DC9_ADC1DC4 0x00100000 |
| #define | SYSCTL_DC9_ADC1DC3 0x00080000 |
| #define | SYSCTL_DC9_ADC1DC2 0x00040000 |
| #define | SYSCTL_DC9_ADC1DC1 0x00020000 |
| #define | SYSCTL_DC9_ADC1DC0 0x00010000 |
| #define | SYSCTL_DC9_ADC0DC7 0x00000080 |
| #define | SYSCTL_DC9_ADC0DC6 0x00000040 |
| #define | SYSCTL_DC9_ADC0DC5 0x00000020 |
| #define | SYSCTL_DC9_ADC0DC4 0x00000010 |
| #define | SYSCTL_DC9_ADC0DC3 0x00000008 |
| #define | SYSCTL_DC9_ADC0DC2 0x00000004 |
| #define | SYSCTL_DC9_ADC0DC1 0x00000002 |
| #define | SYSCTL_DC9_ADC0DC0 0x00000001 |
| #define | SYSCTL_NVMSTAT_FWB 0x00000001 |
| #define | SYSCTL_LDOSPCTL_VADJEN 0x80000000 |
| #define | SYSCTL_LDOSPCTL_VLDO_M 0x000000FF |
| #define | SYSCTL_LDOSPCTL_VLDO_0_90V 0x00000012 |
| #define | SYSCTL_LDOSPCTL_VLDO_0_95V 0x00000013 |
| #define | SYSCTL_LDOSPCTL_VLDO_1_00V 0x00000014 |
| #define | SYSCTL_LDOSPCTL_VLDO_1_05V 0x00000015 |
| #define | SYSCTL_LDOSPCTL_VLDO_1_10V 0x00000016 |
| #define | SYSCTL_LDOSPCTL_VLDO_1_15V 0x00000017 |
| #define | SYSCTL_LDOSPCTL_VLDO_1_20V 0x00000018 |
| #define | SYSCTL_LDODPCTL_VADJEN 0x80000000 |
| #define | SYSCTL_LDODPCTL_VLDO_M 0x000000FF |
| #define | SYSCTL_LDODPCTL_VLDO_0_90V 0x00000012 |
| #define | SYSCTL_LDODPCTL_VLDO_0_95V 0x00000013 |
| #define | SYSCTL_LDODPCTL_VLDO_1_00V 0x00000014 |
| #define | SYSCTL_LDODPCTL_VLDO_1_05V 0x00000015 |
| #define | SYSCTL_LDODPCTL_VLDO_1_10V 0x00000016 |
| #define | SYSCTL_LDODPCTL_VLDO_1_15V 0x00000017 |
| #define | SYSCTL_LDODPCTL_VLDO_1_20V 0x00000018 |
| #define | SYSCTL_PPWD_P1 0x00000002 |
| #define | SYSCTL_PPWD_P0 0x00000001 |
| #define | SYSCTL_PPTIMER_P5 0x00000020 |
| #define | SYSCTL_PPTIMER_P4 0x00000010 |
| #define | SYSCTL_PPTIMER_P3 0x00000008 |
| #define | SYSCTL_PPTIMER_P2 0x00000004 |
| #define | SYSCTL_PPTIMER_P1 0x00000002 |
| #define | SYSCTL_PPTIMER_P0 0x00000001 |
| #define | SYSCTL_PPGPIO_P14 0x00004000 |
| #define | SYSCTL_PPGPIO_P13 0x00002000 |
| #define | SYSCTL_PPGPIO_P12 0x00001000 |
| #define | SYSCTL_PPGPIO_P11 0x00000800 |
| #define | SYSCTL_PPGPIO_P10 0x00000400 |
| #define | SYSCTL_PPGPIO_P9 0x00000200 |
| #define | SYSCTL_PPGPIO_P8 0x00000100 |
| #define | SYSCTL_PPGPIO_P7 0x00000080 |
| #define | SYSCTL_PPGPIO_P6 0x00000040 |
| #define | SYSCTL_PPGPIO_P5 0x00000020 |
| #define | SYSCTL_PPGPIO_P4 0x00000010 |
| #define | SYSCTL_PPGPIO_P3 0x00000008 |
| #define | SYSCTL_PPGPIO_P2 0x00000004 |
| #define | SYSCTL_PPGPIO_P1 0x00000002 |
| #define | SYSCTL_PPGPIO_P0 0x00000001 |
| #define | SYSCTL_PPDMA_P0 0x00000001 |
| #define | SYSCTL_PPHIB_P0 0x00000001 |
| #define | SYSCTL_PPUART_P7 0x00000080 |
| #define | SYSCTL_PPUART_P6 0x00000040 |
| #define | SYSCTL_PPUART_P5 0x00000020 |
| #define | SYSCTL_PPUART_P4 0x00000010 |
| #define | SYSCTL_PPUART_P3 0x00000008 |
| #define | SYSCTL_PPUART_P2 0x00000004 |
| #define | SYSCTL_PPUART_P1 0x00000002 |
| #define | SYSCTL_PPUART_P0 0x00000001 |
| #define | SYSCTL_PPSSI_P3 0x00000008 |
| #define | SYSCTL_PPSSI_P2 0x00000004 |
| #define | SYSCTL_PPSSI_P1 0x00000002 |
| #define | SYSCTL_PPSSI_P0 0x00000001 |
| #define | SYSCTL_PPI2C_P5 0x00000020 |
| #define | SYSCTL_PPI2C_P4 0x00000010 |
| #define | SYSCTL_PPI2C_P3 0x00000008 |
| #define | SYSCTL_PPI2C_P2 0x00000004 |
| #define | SYSCTL_PPI2C_P1 0x00000002 |
| #define | SYSCTL_PPI2C_P0 0x00000001 |
| #define | SYSCTL_PPUSB_P0 0x00000001 |
| #define | SYSCTL_PPCAN_P1 0x00000002 |
| #define | SYSCTL_PPCAN_P0 0x00000001 |
| #define | SYSCTL_PPADC_P1 0x00000002 |
| #define | SYSCTL_PPADC_P0 0x00000001 |
| #define | SYSCTL_PPACMP_P0 0x00000001 |
| #define | SYSCTL_PPPWM_P1 0x00000002 |
| #define | SYSCTL_PPPWM_P0 0x00000001 |
| #define | SYSCTL_PPQEI_P1 0x00000002 |
| #define | SYSCTL_PPQEI_P0 0x00000001 |
| #define | SYSCTL_PPEEPROM_P0 0x00000001 |
| #define | SYSCTL_PPWTIMER_P5 0x00000020 |
| #define | SYSCTL_PPWTIMER_P4 0x00000010 |
| #define | SYSCTL_PPWTIMER_P3 0x00000008 |
| #define | SYSCTL_PPWTIMER_P2 0x00000004 |
| #define | SYSCTL_PPWTIMER_P1 0x00000002 |
| #define | SYSCTL_PPWTIMER_P0 0x00000001 |
| #define | SYSCTL_SRWD_R1 0x00000002 |
| #define | SYSCTL_SRWD_R0 0x00000001 |
| #define | SYSCTL_SRTIMER_R5 0x00000020 |
| #define | SYSCTL_SRTIMER_R4 0x00000010 |
| #define | SYSCTL_SRTIMER_R3 0x00000008 |
| #define | SYSCTL_SRTIMER_R2 0x00000004 |
| #define | SYSCTL_SRTIMER_R1 0x00000002 |
| #define | SYSCTL_SRTIMER_R0 0x00000001 |
| #define | SYSCTL_SRGPIO_R13 0x00002000 |
| #define | SYSCTL_SRGPIO_R12 0x00001000 |
| #define | SYSCTL_SRGPIO_R11 0x00000800 |
| #define | SYSCTL_SRGPIO_R10 0x00000400 |
| #define | SYSCTL_SRGPIO_R9 0x00000200 |
| #define | SYSCTL_SRGPIO_R8 0x00000100 |
| #define | SYSCTL_SRGPIO_R7 0x00000080 |
| #define | SYSCTL_SRGPIO_R6 0x00000040 |
| #define | SYSCTL_SRGPIO_R5 0x00000020 |
| #define | SYSCTL_SRGPIO_R4 0x00000010 |
| #define | SYSCTL_SRGPIO_R3 0x00000008 |
| #define | SYSCTL_SRGPIO_R2 0x00000004 |
| #define | SYSCTL_SRGPIO_R1 0x00000002 |
| #define | SYSCTL_SRGPIO_R0 0x00000001 |
| #define | SYSCTL_SRDMA_R0 0x00000001 |
| #define | SYSCTL_SRHIB_R0 0x00000001 |
| #define | SYSCTL_SRUART_R7 0x00000080 |
| #define | SYSCTL_SRUART_R6 0x00000040 |
| #define | SYSCTL_SRUART_R5 0x00000020 |
| #define | SYSCTL_SRUART_R4 0x00000010 |
| #define | SYSCTL_SRUART_R3 0x00000008 |
| #define | SYSCTL_SRUART_R2 0x00000004 |
| #define | SYSCTL_SRUART_R1 0x00000002 |
| #define | SYSCTL_SRUART_R0 0x00000001 |
| #define | SYSCTL_SRSSI_R3 0x00000008 |
| #define | SYSCTL_SRSSI_R2 0x00000004 |
| #define | SYSCTL_SRSSI_R1 0x00000002 |
| #define | SYSCTL_SRSSI_R0 0x00000001 |
| #define | SYSCTL_SRI2C_R5 0x00000020 |
| #define | SYSCTL_SRI2C_R4 0x00000010 |
| #define | SYSCTL_SRI2C_R3 0x00000008 |
| #define | SYSCTL_SRI2C_R2 0x00000004 |
| #define | SYSCTL_SRI2C_R1 0x00000002 |
| #define | SYSCTL_SRI2C_R0 0x00000001 |
| #define | SYSCTL_SRUSB_R0 0x00000001 |
| #define | SYSCTL_SRCAN_R1 0x00000002 |
| #define | SYSCTL_SRCAN_R0 0x00000001 |
| #define | SYSCTL_SRADC_R1 0x00000002 |
| #define | SYSCTL_SRADC_R0 0x00000001 |
| #define | SYSCTL_SRACMP_R0 0x00000001 |
| #define | SYSCTL_SRPWM_R1 0x00000002 |
| #define | SYSCTL_SRPWM_R0 0x00000001 |
| #define | SYSCTL_SRQEI_R1 0x00000002 |
| #define | SYSCTL_SRQEI_R0 0x00000001 |
| #define | SYSCTL_SREEPROM_R0 0x00000001 |
| #define | SYSCTL_SRWTIMER_R5 0x00000020 |
| #define | SYSCTL_SRWTIMER_R4 0x00000010 |
| #define | SYSCTL_SRWTIMER_R3 0x00000008 |
| #define | SYSCTL_SRWTIMER_R2 0x00000004 |
| #define | SYSCTL_SRWTIMER_R1 0x00000002 |
| #define | SYSCTL_SRWTIMER_R0 0x00000001 |
| #define | SYSCTL_RCGCWD_R1 0x00000002 |
| #define | SYSCTL_RCGCWD_R0 0x00000001 |
| #define | SYSCTL_RCGCTIMER_R5 0x00000020 |
| #define | SYSCTL_RCGCTIMER_R4 0x00000010 |
| #define | SYSCTL_RCGCTIMER_R3 0x00000008 |
| #define | SYSCTL_RCGCTIMER_R2 0x00000004 |
| #define | SYSCTL_RCGCTIMER_R1 0x00000002 |
| #define | SYSCTL_RCGCTIMER_R0 0x00000001 |
| #define | SYSCTL_RCGCGPIO_R13 0x00002000 |
| #define | SYSCTL_RCGCGPIO_R12 0x00001000 |
| #define | SYSCTL_RCGCGPIO_R11 0x00000800 |
| #define | SYSCTL_RCGCGPIO_R10 0x00000400 |
| #define | SYSCTL_RCGCGPIO_R9 0x00000200 |
| #define | SYSCTL_RCGCGPIO_R8 0x00000100 |
| #define | SYSCTL_RCGCGPIO_R7 0x00000080 |
| #define | SYSCTL_RCGCGPIO_R6 0x00000040 |
| #define | SYSCTL_RCGCGPIO_R5 0x00000020 |
| #define | SYSCTL_RCGCGPIO_R4 0x00000010 |
| #define | SYSCTL_RCGCGPIO_R3 0x00000008 |
| #define | SYSCTL_RCGCGPIO_R2 0x00000004 |
| #define | SYSCTL_RCGCGPIO_R1 0x00000002 |
| #define | SYSCTL_RCGCGPIO_R0 0x00000001 |
| #define | SYSCTL_RCGCDMA_R0 0x00000001 |
| #define | SYSCTL_RCGCHIB_R0 0x00000001 |
| #define | SYSCTL_RCGCUART_R7 0x00000080 |
| #define | SYSCTL_RCGCUART_R6 0x00000040 |
| #define | SYSCTL_RCGCUART_R5 0x00000020 |
| #define | SYSCTL_RCGCUART_R4 0x00000010 |
| #define | SYSCTL_RCGCUART_R3 0x00000008 |
| #define | SYSCTL_RCGCUART_R2 0x00000004 |
| #define | SYSCTL_RCGCUART_R1 0x00000002 |
| #define | SYSCTL_RCGCUART_R0 0x00000001 |
| #define | SYSCTL_RCGCSSI_R3 0x00000008 |
| #define | SYSCTL_RCGCSSI_R2 0x00000004 |
| #define | SYSCTL_RCGCSSI_R1 0x00000002 |
| #define | SYSCTL_RCGCSSI_R0 0x00000001 |
| #define | SYSCTL_RCGCI2C_R5 0x00000020 |
| #define | SYSCTL_RCGCI2C_R4 0x00000010 |
| #define | SYSCTL_RCGCI2C_R3 0x00000008 |
| #define | SYSCTL_RCGCI2C_R2 0x00000004 |
| #define | SYSCTL_RCGCI2C_R1 0x00000002 |
| #define | SYSCTL_RCGCI2C_R0 0x00000001 |
| #define | SYSCTL_RCGCUSB_R0 0x00000001 |
| #define | SYSCTL_RCGCCAN_R1 0x00000002 |
| #define | SYSCTL_RCGCCAN_R0 0x00000001 |
| #define | SYSCTL_RCGCADC_R1 0x00000002 |
| #define | SYSCTL_RCGCADC_R0 0x00000001 |
| #define | SYSCTL_RCGCACMP_R0 0x00000001 |
| #define | SYSCTL_RCGCPWM_R1 0x00000002 |
| #define | SYSCTL_RCGCPWM_R0 0x00000001 |
| #define | SYSCTL_RCGCQEI_R1 0x00000002 |
| #define | SYSCTL_RCGCQEI_R0 0x00000001 |
| #define | SYSCTL_RCGCEEPROM_R0 0x00000001 |
| #define | SYSCTL_RCGCWTIMER_R5 0x00000020 |
| #define | SYSCTL_RCGCWTIMER_R4 0x00000010 |
| #define | SYSCTL_RCGCWTIMER_R3 0x00000008 |
| #define | SYSCTL_RCGCWTIMER_R2 0x00000004 |
| #define | SYSCTL_RCGCWTIMER_R1 0x00000002 |
| #define | SYSCTL_RCGCWTIMER_R0 0x00000001 |
| #define | SYSCTL_SCGCWD_S1 0x00000002 |
| #define | SYSCTL_SCGCWD_S0 0x00000001 |
| #define | SYSCTL_SCGCTIMER_S5 0x00000020 |
| #define | SYSCTL_SCGCTIMER_S4 0x00000010 |
| #define | SYSCTL_SCGCTIMER_S3 0x00000008 |
| #define | SYSCTL_SCGCTIMER_S2 0x00000004 |
| #define | SYSCTL_SCGCTIMER_S1 0x00000002 |
| #define | SYSCTL_SCGCTIMER_S0 0x00000001 |
| #define | SYSCTL_SCGCGPIO_S13 0x00002000 |
| #define | SYSCTL_SCGCGPIO_S12 0x00001000 |
| #define | SYSCTL_SCGCGPIO_S11 0x00000800 |
| #define | SYSCTL_SCGCGPIO_S10 0x00000400 |
| #define | SYSCTL_SCGCGPIO_S9 0x00000200 |
| #define | SYSCTL_SCGCGPIO_S8 0x00000100 |
| #define | SYSCTL_SCGCGPIO_S7 0x00000080 |
| #define | SYSCTL_SCGCGPIO_S6 0x00000040 |
| #define | SYSCTL_SCGCGPIO_S5 0x00000020 |
| #define | SYSCTL_SCGCGPIO_S4 0x00000010 |
| #define | SYSCTL_SCGCGPIO_S3 0x00000008 |
| #define | SYSCTL_SCGCGPIO_S2 0x00000004 |
| #define | SYSCTL_SCGCGPIO_S1 0x00000002 |
| #define | SYSCTL_SCGCGPIO_S0 0x00000001 |
| #define | SYSCTL_SCGCDMA_S0 0x00000001 |
| #define | SYSCTL_SCGCHIB_S0 0x00000001 |
| #define | SYSCTL_SCGCUART_S7 0x00000080 |
| #define | SYSCTL_SCGCUART_S6 0x00000040 |
| #define | SYSCTL_SCGCUART_S5 0x00000020 |
| #define | SYSCTL_SCGCUART_S4 0x00000010 |
| #define | SYSCTL_SCGCUART_S3 0x00000008 |
| #define | SYSCTL_SCGCUART_S2 0x00000004 |
| #define | SYSCTL_SCGCUART_S1 0x00000002 |
| #define | SYSCTL_SCGCUART_S0 0x00000001 |
| #define | SYSCTL_SCGCSSI_S3 0x00000008 |
| #define | SYSCTL_SCGCSSI_S2 0x00000004 |
| #define | SYSCTL_SCGCSSI_S1 0x00000002 |
| #define | SYSCTL_SCGCSSI_S0 0x00000001 |
| #define | SYSCTL_SCGCI2C_S5 0x00000020 |
| #define | SYSCTL_SCGCI2C_S4 0x00000010 |
| #define | SYSCTL_SCGCI2C_S3 0x00000008 |
| #define | SYSCTL_SCGCI2C_S2 0x00000004 |
| #define | SYSCTL_SCGCI2C_S1 0x00000002 |
| #define | SYSCTL_SCGCI2C_S0 0x00000001 |
| #define | SYSCTL_SCGCUSB_S0 0x00000001 |
| #define | SYSCTL_SCGCCAN_S1 0x00000002 |
| #define | SYSCTL_SCGCCAN_S0 0x00000001 |
| #define | SYSCTL_SCGCADC_S1 0x00000002 |
| #define | SYSCTL_SCGCADC_S0 0x00000001 |
| #define | SYSCTL_SCGCACMP_S0 0x00000001 |
| #define | SYSCTL_SCGCPWM_S1 0x00000002 |
| #define | SYSCTL_SCGCPWM_S0 0x00000001 |
| #define | SYSCTL_SCGCQEI_S1 0x00000002 |
| #define | SYSCTL_SCGCQEI_S0 0x00000001 |
| #define | SYSCTL_SCGCEEPROM_S0 0x00000001 |
| #define | SYSCTL_SCGCWTIMER_S5 0x00000020 |
| #define | SYSCTL_SCGCWTIMER_S4 0x00000010 |
| #define | SYSCTL_SCGCWTIMER_S3 0x00000008 |
| #define | SYSCTL_SCGCWTIMER_S2 0x00000004 |
| #define | SYSCTL_SCGCWTIMER_S1 0x00000002 |
| #define | SYSCTL_SCGCWTIMER_S0 0x00000001 |
| #define | SYSCTL_DCGCWD_D1 0x00000002 |
| #define | SYSCTL_DCGCWD_D0 0x00000001 |
| #define | SYSCTL_DCGCTIMER_D5 0x00000020 |
| #define | SYSCTL_DCGCTIMER_D4 0x00000010 |
| #define | SYSCTL_DCGCTIMER_D3 0x00000008 |
| #define | SYSCTL_DCGCTIMER_D2 0x00000004 |
| #define | SYSCTL_DCGCTIMER_D1 0x00000002 |
| #define | SYSCTL_DCGCTIMER_D0 0x00000001 |
| #define | SYSCTL_DCGCGPIO_D13 0x00002000 |
| #define | SYSCTL_DCGCGPIO_D12 0x00001000 |
| #define | SYSCTL_DCGCGPIO_D11 0x00000800 |
| #define | SYSCTL_DCGCGPIO_D10 0x00000400 |
| #define | SYSCTL_DCGCGPIO_D9 0x00000200 |
| #define | SYSCTL_DCGCGPIO_D8 0x00000100 |
| #define | SYSCTL_DCGCGPIO_D7 0x00000080 |
| #define | SYSCTL_DCGCGPIO_D6 0x00000040 |
| #define | SYSCTL_DCGCGPIO_D5 0x00000020 |
| #define | SYSCTL_DCGCGPIO_D4 0x00000010 |
| #define | SYSCTL_DCGCGPIO_D3 0x00000008 |
| #define | SYSCTL_DCGCGPIO_D2 0x00000004 |
| #define | SYSCTL_DCGCGPIO_D1 0x00000002 |
| #define | SYSCTL_DCGCGPIO_D0 0x00000001 |
| #define | SYSCTL_DCGCDMA_D0 0x00000001 |
| #define | SYSCTL_DCGCHIB_D0 0x00000001 |
| #define | SYSCTL_DCGCUART_D7 0x00000080 |
| #define | SYSCTL_DCGCUART_D6 0x00000040 |
| #define | SYSCTL_DCGCUART_D5 0x00000020 |
| #define | SYSCTL_DCGCUART_D4 0x00000010 |
| #define | SYSCTL_DCGCUART_D3 0x00000008 |
| #define | SYSCTL_DCGCUART_D2 0x00000004 |
| #define | SYSCTL_DCGCUART_D1 0x00000002 |
| #define | SYSCTL_DCGCUART_D0 0x00000001 |
| #define | SYSCTL_DCGCSSI_D3 0x00000008 |
| #define | SYSCTL_DCGCSSI_D2 0x00000004 |
| #define | SYSCTL_DCGCSSI_D1 0x00000002 |
| #define | SYSCTL_DCGCSSI_D0 0x00000001 |
| #define | SYSCTL_DCGCI2C_D5 0x00000020 |
| #define | SYSCTL_DCGCI2C_D4 0x00000010 |
| #define | SYSCTL_DCGCI2C_D3 0x00000008 |
| #define | SYSCTL_DCGCI2C_D2 0x00000004 |
| #define | SYSCTL_DCGCI2C_D1 0x00000002 |
| #define | SYSCTL_DCGCI2C_D0 0x00000001 |
| #define | SYSCTL_DCGCUSB_D0 0x00000001 |
| #define | SYSCTL_DCGCCAN_D1 0x00000002 |
| #define | SYSCTL_DCGCCAN_D0 0x00000001 |
| #define | SYSCTL_DCGCADC_D1 0x00000002 |
| #define | SYSCTL_DCGCADC_D0 0x00000001 |
| #define | SYSCTL_DCGCACMP_D0 0x00000001 |
| #define | SYSCTL_DCGCPWM_D1 0x00000002 |
| #define | SYSCTL_DCGCPWM_D0 0x00000001 |
| #define | SYSCTL_DCGCQEI_D1 0x00000002 |
| #define | SYSCTL_DCGCQEI_D0 0x00000001 |
| #define | SYSCTL_DCGCEEPROM_D0 0x00000001 |
| #define | SYSCTL_DCGCWTIMER_D5 0x00000020 |
| #define | SYSCTL_DCGCWTIMER_D4 0x00000010 |
| #define | SYSCTL_DCGCWTIMER_D3 0x00000008 |
| #define | SYSCTL_DCGCWTIMER_D2 0x00000004 |
| #define | SYSCTL_DCGCWTIMER_D1 0x00000002 |
| #define | SYSCTL_DCGCWTIMER_D0 0x00000001 |
| #define | SYSCTL_PRWD_R1 0x00000002 |
| #define | SYSCTL_PRWD_R0 0x00000001 |
| #define | SYSCTL_PRTIMER_R5 0x00000020 |
| #define | SYSCTL_PRTIMER_R4 0x00000010 |
| #define | SYSCTL_PRTIMER_R3 0x00000008 |
| #define | SYSCTL_PRTIMER_R2 0x00000004 |
| #define | SYSCTL_PRTIMER_R1 0x00000002 |
| #define | SYSCTL_PRTIMER_R0 0x00000001 |
| #define | SYSCTL_PRGPIO_R13 0x00002000 |
| #define | SYSCTL_PRGPIO_R12 0x00001000 |
| #define | SYSCTL_PRGPIO_R11 0x00000800 |
| #define | SYSCTL_PRGPIO_R10 0x00000400 |
| #define | SYSCTL_PRGPIO_R9 0x00000200 |
| #define | SYSCTL_PRGPIO_R8 0x00000100 |
| #define | SYSCTL_PRGPIO_R7 0x00000080 |
| #define | SYSCTL_PRGPIO_R6 0x00000040 |
| #define | SYSCTL_PRGPIO_R5 0x00000020 |
| #define | SYSCTL_PRGPIO_R4 0x00000010 |
| #define | SYSCTL_PRGPIO_R3 0x00000008 |
| #define | SYSCTL_PRGPIO_R2 0x00000004 |
| #define | SYSCTL_PRGPIO_R1 0x00000002 |
| #define | SYSCTL_PRGPIO_R0 0x00000001 |
| #define | SYSCTL_PRDMA_R0 0x00000001 |
| #define | SYSCTL_PRHIB_R0 0x00000001 |
| #define | SYSCTL_PRUART_R7 0x00000080 |
| #define | SYSCTL_PRUART_R6 0x00000040 |
| #define | SYSCTL_PRUART_R5 0x00000020 |
| #define | SYSCTL_PRUART_R4 0x00000010 |
| #define | SYSCTL_PRUART_R3 0x00000008 |
| #define | SYSCTL_PRUART_R2 0x00000004 |
| #define | SYSCTL_PRUART_R1 0x00000002 |
| #define | SYSCTL_PRUART_R0 0x00000001 |
| #define | SYSCTL_PRSSI_R3 0x00000008 |
| #define | SYSCTL_PRSSI_R2 0x00000004 |
| #define | SYSCTL_PRSSI_R1 0x00000002 |
| #define | SYSCTL_PRSSI_R0 0x00000001 |
| #define | SYSCTL_PRI2C_R5 0x00000020 |
| #define | SYSCTL_PRI2C_R4 0x00000010 |
| #define | SYSCTL_PRI2C_R3 0x00000008 |
| #define | SYSCTL_PRI2C_R2 0x00000004 |
| #define | SYSCTL_PRI2C_R1 0x00000002 |
| #define | SYSCTL_PRI2C_R0 0x00000001 |
| #define | SYSCTL_PRUSB_R0 0x00000001 |
| #define | SYSCTL_PRCAN_R1 0x00000002 |
| #define | SYSCTL_PRCAN_R0 0x00000001 |
| #define | SYSCTL_PRADC_R1 0x00000002 |
| #define | SYSCTL_PRADC_R0 0x00000001 |
| #define | SYSCTL_PRACMP_R0 0x00000001 |
| #define | SYSCTL_PRPWM_R1 0x00000002 |
| #define | SYSCTL_PRPWM_R0 0x00000001 |
| #define | SYSCTL_PRQEI_R1 0x00000002 |
| #define | SYSCTL_PRQEI_R0 0x00000001 |
| #define | SYSCTL_PREEPROM_R0 0x00000001 |
| #define | SYSCTL_PRWTIMER_R5 0x00000020 |
| #define | SYSCTL_PRWTIMER_R4 0x00000010 |
| #define | SYSCTL_PRWTIMER_R3 0x00000008 |
| #define | SYSCTL_PRWTIMER_R2 0x00000004 |
| #define | SYSCTL_PRWTIMER_R1 0x00000002 |
| #define | SYSCTL_PRWTIMER_R0 0x00000001 |
| #define | UDMA_STAT_DMACHANS_M 0x001F0000 |
| #define | UDMA_STAT_STATE_M 0x000000F0 |
| #define | UDMA_STAT_STATE_IDLE 0x00000000 |
| #define | UDMA_STAT_STATE_RD_CTRL 0x00000010 |
| #define | UDMA_STAT_STATE_RD_SRCENDP 0x00000020 |
| #define | UDMA_STAT_STATE_RD_DSTENDP 0x00000030 |
| #define | UDMA_STAT_STATE_RD_SRCDAT 0x00000040 |
| #define | UDMA_STAT_STATE_WR_DSTDAT 0x00000050 |
| #define | UDMA_STAT_STATE_WAIT 0x00000060 |
| #define | UDMA_STAT_STATE_WR_CTRL 0x00000070 |
| #define | UDMA_STAT_STATE_STALL 0x00000080 |
| #define | UDMA_STAT_STATE_DONE 0x00000090 |
| #define | UDMA_STAT_STATE_UNDEF 0x000000A0 |
| #define | UDMA_STAT_MASTEN 0x00000001 |
| #define | UDMA_STAT_DMACHANS_S 16 |
| #define | UDMA_CFG_MASTEN 0x00000001 |
| #define | UDMA_CTLBASE_ADDR_M 0xFFFFFC00 |
| #define | UDMA_CTLBASE_ADDR_S 10 |
| #define | UDMA_ALTBASE_ADDR_M 0xFFFFFFFF |
| #define | UDMA_ALTBASE_ADDR_S 0 |
| #define | UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF |
| #define | UDMA_SWREQ_M 0xFFFFFFFF |
| #define | UDMA_USEBURSTSET_SET_M 0xFFFFFFFF |
| #define | UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF |
| #define | UDMA_REQMASKSET_SET_M 0xFFFFFFFF |
| #define | UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF |
| #define | UDMA_ENASET_SET_M 0xFFFFFFFF |
| #define | UDMA_ENACLR_CLR_M 0xFFFFFFFF |
| #define | UDMA_ALTSET_SET_M 0xFFFFFFFF |
| #define | UDMA_ALTCLR_CLR_M 0xFFFFFFFF |
| #define | UDMA_PRIOSET_SET_M 0xFFFFFFFF |
| #define | UDMA_PRIOCLR_CLR_M 0xFFFFFFFF |
| #define | UDMA_ERRCLR_ERRCLR 0x00000001 |
| #define | UDMA_CHASGN_M 0xFFFFFFFF |
| #define | UDMA_CHASGN_PRIMARY 0x00000000 |
| #define | UDMA_CHASGN_SECONDARY 0x00000001 |
| #define | UDMA_CHIS_M 0xFFFFFFFF |
| #define | UDMA_CHMAP0_CH7SEL_M 0xF0000000 |
| #define | UDMA_CHMAP0_CH6SEL_M 0x0F000000 |
| #define | UDMA_CHMAP0_CH5SEL_M 0x00F00000 |
| #define | UDMA_CHMAP0_CH4SEL_M 0x000F0000 |
| #define | UDMA_CHMAP0_CH3SEL_M 0x0000F000 |
| #define | UDMA_CHMAP0_CH2SEL_M 0x00000F00 |
| #define | UDMA_CHMAP0_CH1SEL_M 0x000000F0 |
| #define | UDMA_CHMAP0_CH0SEL_M 0x0000000F |
| #define | UDMA_CHMAP0_CH7SEL_S 28 |
| #define | UDMA_CHMAP0_CH6SEL_S 24 |
| #define | UDMA_CHMAP0_CH5SEL_S 20 |
| #define | UDMA_CHMAP0_CH4SEL_S 16 |
| #define | UDMA_CHMAP0_CH3SEL_S 12 |
| #define | UDMA_CHMAP0_CH2SEL_S 8 |
| #define | UDMA_CHMAP0_CH1SEL_S 4 |
| #define | UDMA_CHMAP0_CH0SEL_S 0 |
| #define | UDMA_CHMAP1_CH15SEL_M 0xF0000000 |
| #define | UDMA_CHMAP1_CH14SEL_M 0x0F000000 |
| #define | UDMA_CHMAP1_CH13SEL_M 0x00F00000 |
| #define | UDMA_CHMAP1_CH12SEL_M 0x000F0000 |
| #define | UDMA_CHMAP1_CH11SEL_M 0x0000F000 |
| #define | UDMA_CHMAP1_CH10SEL_M 0x00000F00 |
| #define | UDMA_CHMAP1_CH9SEL_M 0x000000F0 |
| #define | UDMA_CHMAP1_CH8SEL_M 0x0000000F |
| #define | UDMA_CHMAP1_CH15SEL_S 28 |
| #define | UDMA_CHMAP1_CH14SEL_S 24 |
| #define | UDMA_CHMAP1_CH13SEL_S 20 |
| #define | UDMA_CHMAP1_CH12SEL_S 16 |
| #define | UDMA_CHMAP1_CH11SEL_S 12 |
| #define | UDMA_CHMAP1_CH10SEL_S 8 |
| #define | UDMA_CHMAP1_CH9SEL_S 4 |
| #define | UDMA_CHMAP1_CH8SEL_S 0 |
| #define | UDMA_CHMAP2_CH23SEL_M 0xF0000000 |
| #define | UDMA_CHMAP2_CH22SEL_M 0x0F000000 |
| #define | UDMA_CHMAP2_CH21SEL_M 0x00F00000 |
| #define | UDMA_CHMAP2_CH20SEL_M 0x000F0000 |
| #define | UDMA_CHMAP2_CH19SEL_M 0x0000F000 |
| #define | UDMA_CHMAP2_CH18SEL_M 0x00000F00 |
| #define | UDMA_CHMAP2_CH17SEL_M 0x000000F0 |
| #define | UDMA_CHMAP2_CH16SEL_M 0x0000000F |
| #define | UDMA_CHMAP2_CH23SEL_S 28 |
| #define | UDMA_CHMAP2_CH22SEL_S 24 |
| #define | UDMA_CHMAP2_CH21SEL_S 20 |
| #define | UDMA_CHMAP2_CH20SEL_S 16 |
| #define | UDMA_CHMAP2_CH19SEL_S 12 |
| #define | UDMA_CHMAP2_CH18SEL_S 8 |
| #define | UDMA_CHMAP2_CH17SEL_S 4 |
| #define | UDMA_CHMAP2_CH16SEL_S 0 |
| #define | UDMA_CHMAP3_CH31SEL_M 0xF0000000 |
| #define | UDMA_CHMAP3_CH30SEL_M 0x0F000000 |
| #define | UDMA_CHMAP3_CH29SEL_M 0x00F00000 |
| #define | UDMA_CHMAP3_CH28SEL_M 0x000F0000 |
| #define | UDMA_CHMAP3_CH27SEL_M 0x0000F000 |
| #define | UDMA_CHMAP3_CH26SEL_M 0x00000F00 |
| #define | UDMA_CHMAP3_CH25SEL_M 0x000000F0 |
| #define | UDMA_CHMAP3_CH24SEL_M 0x0000000F |
| #define | UDMA_CHMAP3_CH31SEL_S 28 |
| #define | UDMA_CHMAP3_CH30SEL_S 24 |
| #define | UDMA_CHMAP3_CH29SEL_S 20 |
| #define | UDMA_CHMAP3_CH28SEL_S 16 |
| #define | UDMA_CHMAP3_CH27SEL_S 12 |
| #define | UDMA_CHMAP3_CH26SEL_S 8 |
| #define | UDMA_CHMAP3_CH25SEL_S 4 |
| #define | UDMA_CHMAP3_CH24SEL_S 0 |
| #define | UDMA_SRCENDP_ADDR_M 0xFFFFFFFF |
| #define | UDMA_SRCENDP_ADDR_S 0 |
| #define | UDMA_DSTENDP_ADDR_M 0xFFFFFFFF |
| #define | UDMA_DSTENDP_ADDR_S 0 |
| #define | UDMA_CHCTL_DSTINC_M 0xC0000000 |
| #define | UDMA_CHCTL_DSTINC_8 0x00000000 |
| #define | UDMA_CHCTL_DSTINC_16 0x40000000 |
| #define | UDMA_CHCTL_DSTINC_32 0x80000000 |
| #define | UDMA_CHCTL_DSTINC_NONE 0xC0000000 |
| #define | UDMA_CHCTL_DSTSIZE_M 0x30000000 |
| #define | UDMA_CHCTL_DSTSIZE_8 0x00000000 |
| #define | UDMA_CHCTL_DSTSIZE_16 0x10000000 |
| #define | UDMA_CHCTL_DSTSIZE_32 0x20000000 |
| #define | UDMA_CHCTL_SRCINC_M 0x0C000000 |
| #define | UDMA_CHCTL_SRCINC_8 0x00000000 |
| #define | UDMA_CHCTL_SRCINC_16 0x04000000 |
| #define | UDMA_CHCTL_SRCINC_32 0x08000000 |
| #define | UDMA_CHCTL_SRCINC_NONE 0x0C000000 |
| #define | UDMA_CHCTL_SRCSIZE_M 0x03000000 |
| #define | UDMA_CHCTL_SRCSIZE_8 0x00000000 |
| #define | UDMA_CHCTL_SRCSIZE_16 0x01000000 |
| #define | UDMA_CHCTL_SRCSIZE_32 0x02000000 |
| #define | UDMA_CHCTL_ARBSIZE_M 0x0003C000 |
| #define | UDMA_CHCTL_ARBSIZE_1 0x00000000 |
| #define | UDMA_CHCTL_ARBSIZE_2 0x00004000 |
| #define | UDMA_CHCTL_ARBSIZE_4 0x00008000 |
| #define | UDMA_CHCTL_ARBSIZE_8 0x0000C000 |
| #define | UDMA_CHCTL_ARBSIZE_16 0x00010000 |
| #define | UDMA_CHCTL_ARBSIZE_32 0x00014000 |
| #define | UDMA_CHCTL_ARBSIZE_64 0x00018000 |
| #define | UDMA_CHCTL_ARBSIZE_128 0x0001C000 |
| #define | UDMA_CHCTL_ARBSIZE_256 0x00020000 |
| #define | UDMA_CHCTL_ARBSIZE_512 0x00024000 |
| #define | UDMA_CHCTL_ARBSIZE_1024 0x00028000 |
| #define | UDMA_CHCTL_XFERSIZE_M 0x00003FF0 |
| #define | UDMA_CHCTL_NXTUSEBURST 0x00000008 |
| #define | UDMA_CHCTL_XFERMODE_M 0x00000007 |
| #define | UDMA_CHCTL_XFERMODE_STOP 0x00000000 |
| #define | UDMA_CHCTL_XFERMODE_BASIC 0x00000001 |
| #define | UDMA_CHCTL_XFERMODE_AUTO 0x00000002 |
| #define | UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 |
| #define | UDMA_CHCTL_XFERMODE_MEM_SG 0x00000004 |
| #define | UDMA_CHCTL_XFERMODE_MEM_SGA 0x00000005 |
| #define | UDMA_CHCTL_XFERMODE_PER_SG 0x00000006 |
| #define | UDMA_CHCTL_XFERMODE_PER_SGA 0x00000007 |
| #define | UDMA_CHCTL_XFERSIZE_S 4 |
| #define | NVIC_ACTLR_DISOOFP 0x00000200 |
| #define | NVIC_ACTLR_DISFPCA 0x00000100 |
| #define | NVIC_ACTLR_DISFOLD 0x00000004 |
| #define | NVIC_ACTLR_DISWBUF 0x00000002 |
| #define | NVIC_ACTLR_DISMCYC 0x00000001 |
| #define | NVIC_ST_CTRL_COUNT 0x00010000 |
| #define | NVIC_ST_CTRL_CLK_SRC 0x00000004 |
| #define | NVIC_ST_CTRL_INTEN 0x00000002 |
| #define | NVIC_ST_CTRL_ENABLE 0x00000001 |
| #define | NVIC_ST_RELOAD_M 0x00FFFFFF |
| #define | NVIC_ST_RELOAD_S 0 |
| #define | NVIC_ST_CURRENT_M 0x00FFFFFF |
| #define | NVIC_ST_CURRENT_S 0 |
| #define | NVIC_EN0_INT_M 0xFFFFFFFF |
| #define | NVIC_EN1_INT_M 0xFFFFFFFF |
| #define | NVIC_EN2_INT_M 0xFFFFFFFF |
| #define | NVIC_EN3_INT_M 0xFFFFFFFF |
| #define | NVIC_EN4_INT_M 0x000007FF |
| #define | NVIC_DIS0_INT_M 0xFFFFFFFF |
| #define | NVIC_DIS1_INT_M 0xFFFFFFFF |
| #define | NVIC_DIS2_INT_M 0xFFFFFFFF |
| #define | NVIC_DIS3_INT_M 0xFFFFFFFF |
| #define | NVIC_DIS4_INT_M 0x000007FF |
| #define | NVIC_PEND0_INT_M 0xFFFFFFFF |
| #define | NVIC_PEND1_INT_M 0xFFFFFFFF |
| #define | NVIC_PEND2_INT_M 0xFFFFFFFF |
| #define | NVIC_PEND3_INT_M 0xFFFFFFFF |
| #define | NVIC_PEND4_INT_M 0x000007FF |
| #define | NVIC_UNPEND0_INT_M 0xFFFFFFFF |
| #define | NVIC_UNPEND1_INT_M 0xFFFFFFFF |
| #define | NVIC_UNPEND2_INT_M 0xFFFFFFFF |
| #define | NVIC_UNPEND3_INT_M 0xFFFFFFFF |
| #define | NVIC_UNPEND4_INT_M 0x000007FF |
| #define | NVIC_ACTIVE0_INT_M 0xFFFFFFFF |
| #define | NVIC_ACTIVE1_INT_M 0xFFFFFFFF |
| #define | NVIC_ACTIVE2_INT_M 0xFFFFFFFF |
| #define | NVIC_ACTIVE3_INT_M 0xFFFFFFFF |
| #define | NVIC_ACTIVE4_INT_M 0x000007FF |
| #define | NVIC_PRI0_INT3_M 0xE0000000 |
| #define | NVIC_PRI0_INT2_M 0x00E00000 |
| #define | NVIC_PRI0_INT1_M 0x0000E000 |
| #define | NVIC_PRI0_INT0_M 0x000000E0 |
| #define | NVIC_PRI0_INT3_S 29 |
| #define | NVIC_PRI0_INT2_S 21 |
| #define | NVIC_PRI0_INT1_S 13 |
| #define | NVIC_PRI0_INT0_S 5 |
| #define | NVIC_PRI1_INT7_M 0xE0000000 |
| #define | NVIC_PRI1_INT6_M 0x00E00000 |
| #define | NVIC_PRI1_INT5_M 0x0000E000 |
| #define | NVIC_PRI1_INT4_M 0x000000E0 |
| #define | NVIC_PRI1_INT7_S 29 |
| #define | NVIC_PRI1_INT6_S 21 |
| #define | NVIC_PRI1_INT5_S 13 |
| #define | NVIC_PRI1_INT4_S 5 |
| #define | NVIC_PRI2_INT11_M 0xE0000000 |
| #define | NVIC_PRI2_INT10_M 0x00E00000 |
| #define | NVIC_PRI2_INT9_M 0x0000E000 |
| #define | NVIC_PRI2_INT8_M 0x000000E0 |
| #define | NVIC_PRI2_INT11_S 29 |
| #define | NVIC_PRI2_INT10_S 21 |
| #define | NVIC_PRI2_INT9_S 13 |
| #define | NVIC_PRI2_INT8_S 5 |
| #define | NVIC_PRI3_INT15_M 0xE0000000 |
| #define | NVIC_PRI3_INT14_M 0x00E00000 |
| #define | NVIC_PRI3_INT13_M 0x0000E000 |
| #define | NVIC_PRI3_INT12_M 0x000000E0 |
| #define | NVIC_PRI3_INT15_S 29 |
| #define | NVIC_PRI3_INT14_S 21 |
| #define | NVIC_PRI3_INT13_S 13 |
| #define | NVIC_PRI3_INT12_S 5 |
| #define | NVIC_PRI4_INT19_M 0xE0000000 |
| #define | NVIC_PRI4_INT18_M 0x00E00000 |
| #define | NVIC_PRI4_INT17_M 0x0000E000 |
| #define | NVIC_PRI4_INT16_M 0x000000E0 |
| #define | NVIC_PRI4_INT19_S 29 |
| #define | NVIC_PRI4_INT18_S 21 |
| #define | NVIC_PRI4_INT17_S 13 |
| #define | NVIC_PRI4_INT16_S 5 |
| #define | NVIC_PRI5_INT23_M 0xE0000000 |
| #define | NVIC_PRI5_INT22_M 0x00E00000 |
| #define | NVIC_PRI5_INT21_M 0x0000E000 |
| #define | NVIC_PRI5_INT20_M 0x000000E0 |
| #define | NVIC_PRI5_INT23_S 29 |
| #define | NVIC_PRI5_INT22_S 21 |
| #define | NVIC_PRI5_INT21_S 13 |
| #define | NVIC_PRI5_INT20_S 5 |
| #define | NVIC_PRI6_INT27_M 0xE0000000 |
| #define | NVIC_PRI6_INT26_M 0x00E00000 |
| #define | NVIC_PRI6_INT25_M 0x0000E000 |
| #define | NVIC_PRI6_INT24_M 0x000000E0 |
| #define | NVIC_PRI6_INT27_S 29 |
| #define | NVIC_PRI6_INT26_S 21 |
| #define | NVIC_PRI6_INT25_S 13 |
| #define | NVIC_PRI6_INT24_S 5 |
| #define | NVIC_PRI7_INT31_M 0xE0000000 |
| #define | NVIC_PRI7_INT30_M 0x00E00000 |
| #define | NVIC_PRI7_INT29_M 0x0000E000 |
| #define | NVIC_PRI7_INT28_M 0x000000E0 |
| #define | NVIC_PRI7_INT31_S 29 |
| #define | NVIC_PRI7_INT30_S 21 |
| #define | NVIC_PRI7_INT29_S 13 |
| #define | NVIC_PRI7_INT28_S 5 |
| #define | NVIC_PRI8_INT35_M 0xE0000000 |
| #define | NVIC_PRI8_INT34_M 0x00E00000 |
| #define | NVIC_PRI8_INT33_M 0x0000E000 |
| #define | NVIC_PRI8_INT32_M 0x000000E0 |
| #define | NVIC_PRI8_INT35_S 29 |
| #define | NVIC_PRI8_INT34_S 21 |
| #define | NVIC_PRI8_INT33_S 13 |
| #define | NVIC_PRI8_INT32_S 5 |
| #define | NVIC_PRI9_INT39_M 0xE0000000 |
| #define | NVIC_PRI9_INT38_M 0x00E00000 |
| #define | NVIC_PRI9_INT37_M 0x0000E000 |
| #define | NVIC_PRI9_INT36_M 0x000000E0 |
| #define | NVIC_PRI9_INT39_S 29 |
| #define | NVIC_PRI9_INT38_S 21 |
| #define | NVIC_PRI9_INT37_S 13 |
| #define | NVIC_PRI9_INT36_S 5 |
| #define | NVIC_PRI10_INT43_M 0xE0000000 |
| #define | NVIC_PRI10_INT42_M 0x00E00000 |
| #define | NVIC_PRI10_INT41_M 0x0000E000 |
| #define | NVIC_PRI10_INT40_M 0x000000E0 |
| #define | NVIC_PRI10_INT43_S 29 |
| #define | NVIC_PRI10_INT42_S 21 |
| #define | NVIC_PRI10_INT41_S 13 |
| #define | NVIC_PRI10_INT40_S 5 |
| #define | NVIC_PRI11_INT47_M 0xE0000000 |
| #define | NVIC_PRI11_INT46_M 0x00E00000 |
| #define | NVIC_PRI11_INT45_M 0x0000E000 |
| #define | NVIC_PRI11_INT44_M 0x000000E0 |
| #define | NVIC_PRI11_INT47_S 29 |
| #define | NVIC_PRI11_INT46_S 21 |
| #define | NVIC_PRI11_INT45_S 13 |
| #define | NVIC_PRI11_INT44_S 5 |
| #define | NVIC_PRI12_INT51_M 0xE0000000 |
| #define | NVIC_PRI12_INT50_M 0x00E00000 |
| #define | NVIC_PRI12_INT49_M 0x0000E000 |
| #define | NVIC_PRI12_INT48_M 0x000000E0 |
| #define | NVIC_PRI12_INT51_S 29 |
| #define | NVIC_PRI12_INT50_S 21 |
| #define | NVIC_PRI12_INT49_S 13 |
| #define | NVIC_PRI12_INT48_S 5 |
| #define | NVIC_PRI13_INT55_M 0xE0000000 |
| #define | NVIC_PRI13_INT54_M 0x00E00000 |
| #define | NVIC_PRI13_INT53_M 0x0000E000 |
| #define | NVIC_PRI13_INT52_M 0x000000E0 |
| #define | NVIC_PRI13_INT55_S 29 |
| #define | NVIC_PRI13_INT54_S 21 |
| #define | NVIC_PRI13_INT53_S 13 |
| #define | NVIC_PRI13_INT52_S 5 |
| #define | NVIC_PRI14_INTD_M 0xE0000000 |
| #define | NVIC_PRI14_INTC_M 0x00E00000 |
| #define | NVIC_PRI14_INTB_M 0x0000E000 |
| #define | NVIC_PRI14_INTA_M 0x000000E0 |
| #define | NVIC_PRI14_INTD_S 29 |
| #define | NVIC_PRI14_INTC_S 21 |
| #define | NVIC_PRI14_INTB_S 13 |
| #define | NVIC_PRI14_INTA_S 5 |
| #define | NVIC_PRI15_INTD_M 0xE0000000 |
| #define | NVIC_PRI15_INTC_M 0x00E00000 |
| #define | NVIC_PRI15_INTB_M 0x0000E000 |
| #define | NVIC_PRI15_INTA_M 0x000000E0 |
| #define | NVIC_PRI15_INTD_S 29 |
| #define | NVIC_PRI15_INTC_S 21 |
| #define | NVIC_PRI15_INTB_S 13 |
| #define | NVIC_PRI15_INTA_S 5 |
| #define | NVIC_PRI16_INTD_M 0xE0000000 |
| #define | NVIC_PRI16_INTC_M 0x00E00000 |
| #define | NVIC_PRI16_INTB_M 0x0000E000 |
| #define | NVIC_PRI16_INTA_M 0x000000E0 |
| #define | NVIC_PRI16_INTD_S 29 |
| #define | NVIC_PRI16_INTC_S 21 |
| #define | NVIC_PRI16_INTB_S 13 |
| #define | NVIC_PRI16_INTA_S 5 |
| #define | NVIC_PRI17_INTD_M 0xE0000000 |
| #define | NVIC_PRI17_INTC_M 0x00E00000 |
| #define | NVIC_PRI17_INTB_M 0x0000E000 |
| #define | NVIC_PRI17_INTA_M 0x000000E0 |
| #define | NVIC_PRI17_INTD_S 29 |
| #define | NVIC_PRI17_INTC_S 21 |
| #define | NVIC_PRI17_INTB_S 13 |
| #define | NVIC_PRI17_INTA_S 5 |
| #define | NVIC_PRI18_INTD_M 0xE0000000 |
| #define | NVIC_PRI18_INTC_M 0x00E00000 |
| #define | NVIC_PRI18_INTB_M 0x0000E000 |
| #define | NVIC_PRI18_INTA_M 0x000000E0 |
| #define | NVIC_PRI18_INTD_S 29 |
| #define | NVIC_PRI18_INTC_S 21 |
| #define | NVIC_PRI18_INTB_S 13 |
| #define | NVIC_PRI18_INTA_S 5 |
| #define | NVIC_PRI19_INTD_M 0xE0000000 |
| #define | NVIC_PRI19_INTC_M 0x00E00000 |
| #define | NVIC_PRI19_INTB_M 0x0000E000 |
| #define | NVIC_PRI19_INTA_M 0x000000E0 |
| #define | NVIC_PRI19_INTD_S 29 |
| #define | NVIC_PRI19_INTC_S 21 |
| #define | NVIC_PRI19_INTB_S 13 |
| #define | NVIC_PRI19_INTA_S 5 |
| #define | NVIC_PRI20_INTD_M 0xE0000000 |
| #define | NVIC_PRI20_INTC_M 0x00E00000 |
| #define | NVIC_PRI20_INTB_M 0x0000E000 |
| #define | NVIC_PRI20_INTA_M 0x000000E0 |
| #define | NVIC_PRI20_INTD_S 29 |
| #define | NVIC_PRI20_INTC_S 21 |
| #define | NVIC_PRI20_INTB_S 13 |
| #define | NVIC_PRI20_INTA_S 5 |
| #define | NVIC_PRI21_INTD_M 0xE0000000 |
| #define | NVIC_PRI21_INTC_M 0x00E00000 |
| #define | NVIC_PRI21_INTB_M 0x0000E000 |
| #define | NVIC_PRI21_INTA_M 0x000000E0 |
| #define | NVIC_PRI21_INTD_S 29 |
| #define | NVIC_PRI21_INTC_S 21 |
| #define | NVIC_PRI21_INTB_S 13 |
| #define | NVIC_PRI21_INTA_S 5 |
| #define | NVIC_PRI22_INTD_M 0xE0000000 |
| #define | NVIC_PRI22_INTC_M 0x00E00000 |
| #define | NVIC_PRI22_INTB_M 0x0000E000 |
| #define | NVIC_PRI22_INTA_M 0x000000E0 |
| #define | NVIC_PRI22_INTD_S 29 |
| #define | NVIC_PRI22_INTC_S 21 |
| #define | NVIC_PRI22_INTB_S 13 |
| #define | NVIC_PRI22_INTA_S 5 |
| #define | NVIC_PRI23_INTD_M 0xE0000000 |
| #define | NVIC_PRI23_INTC_M 0x00E00000 |
| #define | NVIC_PRI23_INTB_M 0x0000E000 |
| #define | NVIC_PRI23_INTA_M 0x000000E0 |
| #define | NVIC_PRI23_INTD_S 29 |
| #define | NVIC_PRI23_INTC_S 21 |
| #define | NVIC_PRI23_INTB_S 13 |
| #define | NVIC_PRI23_INTA_S 5 |
| #define | NVIC_PRI24_INTD_M 0xE0000000 |
| #define | NVIC_PRI24_INTC_M 0x00E00000 |
| #define | NVIC_PRI24_INTB_M 0x0000E000 |
| #define | NVIC_PRI24_INTA_M 0x000000E0 |
| #define | NVIC_PRI24_INTD_S 29 |
| #define | NVIC_PRI24_INTC_S 21 |
| #define | NVIC_PRI24_INTB_S 13 |
| #define | NVIC_PRI24_INTA_S 5 |
| #define | NVIC_PRI25_INTD_M 0xE0000000 |
| #define | NVIC_PRI25_INTC_M 0x00E00000 |
| #define | NVIC_PRI25_INTB_M 0x0000E000 |
| #define | NVIC_PRI25_INTA_M 0x000000E0 |
| #define | NVIC_PRI25_INTD_S 29 |
| #define | NVIC_PRI25_INTC_S 21 |
| #define | NVIC_PRI25_INTB_S 13 |
| #define | NVIC_PRI25_INTA_S 5 |
| #define | NVIC_PRI26_INTD_M 0xE0000000 |
| #define | NVIC_PRI26_INTC_M 0x00E00000 |
| #define | NVIC_PRI26_INTB_M 0x0000E000 |
| #define | NVIC_PRI26_INTA_M 0x000000E0 |
| #define | NVIC_PRI26_INTD_S 29 |
| #define | NVIC_PRI26_INTC_S 21 |
| #define | NVIC_PRI26_INTB_S 13 |
| #define | NVIC_PRI26_INTA_S 5 |
| #define | NVIC_PRI27_INTD_M 0xE0000000 |
| #define | NVIC_PRI27_INTC_M 0x00E00000 |
| #define | NVIC_PRI27_INTB_M 0x0000E000 |
| #define | NVIC_PRI27_INTA_M 0x000000E0 |
| #define | NVIC_PRI27_INTD_S 29 |
| #define | NVIC_PRI27_INTC_S 21 |
| #define | NVIC_PRI27_INTB_S 13 |
| #define | NVIC_PRI27_INTA_S 5 |
| #define | NVIC_PRI28_INTD_M 0xE0000000 |
| #define | NVIC_PRI28_INTC_M 0x00E00000 |
| #define | NVIC_PRI28_INTB_M 0x0000E000 |
| #define | NVIC_PRI28_INTA_M 0x000000E0 |
| #define | NVIC_PRI28_INTD_S 29 |
| #define | NVIC_PRI28_INTC_S 21 |
| #define | NVIC_PRI28_INTB_S 13 |
| #define | NVIC_PRI28_INTA_S 5 |
| #define | NVIC_PRI29_INTD_M 0xE0000000 |
| #define | NVIC_PRI29_INTC_M 0x00E00000 |
| #define | NVIC_PRI29_INTB_M 0x0000E000 |
| #define | NVIC_PRI29_INTA_M 0x000000E0 |
| #define | NVIC_PRI29_INTD_S 29 |
| #define | NVIC_PRI29_INTC_S 21 |
| #define | NVIC_PRI29_INTB_S 13 |
| #define | NVIC_PRI29_INTA_S 5 |
| #define | NVIC_PRI30_INTD_M 0xE0000000 |
| #define | NVIC_PRI30_INTC_M 0x00E00000 |
| #define | NVIC_PRI30_INTB_M 0x0000E000 |
| #define | NVIC_PRI30_INTA_M 0x000000E0 |
| #define | NVIC_PRI30_INTD_S 29 |
| #define | NVIC_PRI30_INTC_S 21 |
| #define | NVIC_PRI30_INTB_S 13 |
| #define | NVIC_PRI30_INTA_S 5 |
| #define | NVIC_PRI31_INTD_M 0xE0000000 |
| #define | NVIC_PRI31_INTC_M 0x00E00000 |
| #define | NVIC_PRI31_INTB_M 0x0000E000 |
| #define | NVIC_PRI31_INTA_M 0x000000E0 |
| #define | NVIC_PRI31_INTD_S 29 |
| #define | NVIC_PRI31_INTC_S 21 |
| #define | NVIC_PRI31_INTB_S 13 |
| #define | NVIC_PRI31_INTA_S 5 |
| #define | NVIC_PRI32_INTD_M 0xE0000000 |
| #define | NVIC_PRI32_INTC_M 0x00E00000 |
| #define | NVIC_PRI32_INTB_M 0x0000E000 |
| #define | NVIC_PRI32_INTA_M 0x000000E0 |
| #define | NVIC_PRI32_INTD_S 29 |
| #define | NVIC_PRI32_INTC_S 21 |
| #define | NVIC_PRI32_INTB_S 13 |
| #define | NVIC_PRI32_INTA_S 5 |
| #define | NVIC_PRI33_INTD_M 0xE0000000 |
| #define | NVIC_PRI33_INTC_M 0x00E00000 |
| #define | NVIC_PRI33_INTB_M 0x0000E000 |
| #define | NVIC_PRI33_INTA_M 0x000000E0 |
| #define | NVIC_PRI33_INTD_S 29 |
| #define | NVIC_PRI33_INTC_S 21 |
| #define | NVIC_PRI33_INTB_S 13 |
| #define | NVIC_PRI33_INTA_S 5 |
| #define | NVIC_PRI34_INTD_M 0xE0000000 |
| #define | NVIC_PRI34_INTC_M 0x00E00000 |
| #define | NVIC_PRI34_INTB_M 0x0000E000 |
| #define | NVIC_PRI34_INTA_M 0x000000E0 |
| #define | NVIC_PRI34_INTD_S 29 |
| #define | NVIC_PRI34_INTC_S 21 |
| #define | NVIC_PRI34_INTB_S 13 |
| #define | NVIC_PRI34_INTA_S 5 |
| #define | NVIC_CPUID_IMP_M 0xFF000000 |
| #define | NVIC_CPUID_IMP_ARM 0x41000000 |
| #define | NVIC_CPUID_VAR_M 0x00F00000 |
| #define | NVIC_CPUID_CON_M 0x000F0000 |
| #define | NVIC_CPUID_PARTNO_M 0x0000FFF0 |
| #define | NVIC_CPUID_PARTNO_CM4 0x0000C240 |
| #define | NVIC_CPUID_REV_M 0x0000000F |
| #define | NVIC_INT_CTRL_NMI_SET 0x80000000 |
| #define | NVIC_INT_CTRL_PEND_SV 0x10000000 |
| #define | NVIC_INT_CTRL_UNPEND_SV 0x08000000 |
| #define | NVIC_INT_CTRL_PENDSTSET 0x04000000 |
| #define | NVIC_INT_CTRL_PENDSTCLR 0x02000000 |
| #define | NVIC_INT_CTRL_ISR_PRE 0x00800000 |
| #define | NVIC_INT_CTRL_ISR_PEND 0x00400000 |
| #define | NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 |
| #define | NVIC_INT_CTRL_VEC_PEN_NMI 0x00002000 |
| #define | NVIC_INT_CTRL_VEC_PEN_HARD 0x00003000 |
| #define | NVIC_INT_CTRL_VEC_PEN_MEM 0x00004000 |
| #define | NVIC_INT_CTRL_VEC_PEN_BUS 0x00005000 |
| #define | NVIC_INT_CTRL_VEC_PEN_USG 0x00006000 |
| #define | NVIC_INT_CTRL_VEC_PEN_SVC 0x0000B000 |
| #define | NVIC_INT_CTRL_VEC_PEN_PNDSV 0x0000E000 |
| #define | NVIC_INT_CTRL_VEC_PEN_TICK 0x0000F000 |
| #define | NVIC_INT_CTRL_RET_BASE 0x00000800 |
| #define | NVIC_INT_CTRL_VEC_ACT_M 0x000000FF |
| #define | NVIC_INT_CTRL_VEC_ACT_S 0 |
| #define | NVIC_VTABLE_OFFSET_M 0xFFFFFC00 |
| #define | NVIC_VTABLE_OFFSET_S 10 |
| #define | NVIC_APINT_VECTKEY_M 0xFFFF0000 |
| #define | NVIC_APINT_VECTKEY 0x05FA0000 |
| #define | NVIC_APINT_ENDIANESS 0x00008000 |
| #define | NVIC_APINT_PRIGROUP_M 0x00000700 |
| #define | NVIC_APINT_PRIGROUP_7_1 0x00000000 |
| #define | NVIC_APINT_PRIGROUP_6_2 0x00000100 |
| #define | NVIC_APINT_PRIGROUP_5_3 0x00000200 |
| #define | NVIC_APINT_PRIGROUP_4_4 0x00000300 |
| #define | NVIC_APINT_PRIGROUP_3_5 0x00000400 |
| #define | NVIC_APINT_PRIGROUP_2_6 0x00000500 |
| #define | NVIC_APINT_PRIGROUP_1_7 0x00000600 |
| #define | NVIC_APINT_PRIGROUP_0_8 0x00000700 |
| #define | NVIC_APINT_SYSRESETREQ 0x00000004 |
| #define | NVIC_APINT_VECT_CLR_ACT 0x00000002 |
| #define | NVIC_APINT_VECT_RESET 0x00000001 |
| #define | NVIC_SYS_CTRL_SEVONPEND 0x00000010 |
| #define | NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 |
| #define | NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 |
| #define | NVIC_CFG_CTRL_STKALIGN 0x00000200 |
| #define | NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 |
| #define | NVIC_CFG_CTRL_DIV0 0x00000010 |
| #define | NVIC_CFG_CTRL_UNALIGNED 0x00000008 |
| #define | NVIC_CFG_CTRL_MAIN_PEND 0x00000002 |
| #define | NVIC_CFG_CTRL_BASE_THR 0x00000001 |
| #define | NVIC_SYS_PRI1_USAGE_M 0x00E00000 |
| #define | NVIC_SYS_PRI1_BUS_M 0x0000E000 |
| #define | NVIC_SYS_PRI1_MEM_M 0x000000E0 |
| #define | NVIC_SYS_PRI1_USAGE_S 21 |
| #define | NVIC_SYS_PRI1_BUS_S 13 |
| #define | NVIC_SYS_PRI1_MEM_S 5 |
| #define | NVIC_SYS_PRI2_SVC_M 0xE0000000 |
| #define | NVIC_SYS_PRI2_SVC_S 29 |
| #define | NVIC_SYS_PRI3_TICK_M 0xE0000000 |
| #define | NVIC_SYS_PRI3_PENDSV_M 0x00E00000 |
| #define | NVIC_SYS_PRI3_DEBUG_M 0x000000E0 |
| #define | NVIC_SYS_PRI3_TICK_S 29 |
| #define | NVIC_SYS_PRI3_PENDSV_S 21 |
| #define | NVIC_SYS_PRI3_DEBUG_S 5 |
| #define | NVIC_SYS_HND_CTRL_USAGE 0x00040000 |
| #define | NVIC_SYS_HND_CTRL_BUS 0x00020000 |
| #define | NVIC_SYS_HND_CTRL_MEM 0x00010000 |
| #define | NVIC_SYS_HND_CTRL_SVC 0x00008000 |
| #define | NVIC_SYS_HND_CTRL_BUSP 0x00004000 |
| #define | NVIC_SYS_HND_CTRL_MEMP 0x00002000 |
| #define | NVIC_SYS_HND_CTRL_USAGEP 0x00001000 |
| #define | NVIC_SYS_HND_CTRL_TICK 0x00000800 |
| #define | NVIC_SYS_HND_CTRL_PNDSV 0x00000400 |
| #define | NVIC_SYS_HND_CTRL_MON 0x00000100 |
| #define | NVIC_SYS_HND_CTRL_SVCA 0x00000080 |
| #define | NVIC_SYS_HND_CTRL_USGA 0x00000008 |
| #define | NVIC_SYS_HND_CTRL_BUSA 0x00000002 |
| #define | NVIC_SYS_HND_CTRL_MEMA 0x00000001 |
| #define | NVIC_FAULT_STAT_DIV0 0x02000000 |
| #define | NVIC_FAULT_STAT_UNALIGN 0x01000000 |
| #define | NVIC_FAULT_STAT_NOCP 0x00080000 |
| #define | NVIC_FAULT_STAT_INVPC 0x00040000 |
| #define | NVIC_FAULT_STAT_INVSTAT 0x00020000 |
| #define | NVIC_FAULT_STAT_UNDEF 0x00010000 |
| #define | NVIC_FAULT_STAT_BFARV 0x00008000 |
| #define | NVIC_FAULT_STAT_BLSPERR 0x00002000 |
| #define | NVIC_FAULT_STAT_BSTKE 0x00001000 |
| #define | NVIC_FAULT_STAT_BUSTKE 0x00000800 |
| #define | NVIC_FAULT_STAT_IMPRE 0x00000400 |
| #define | NVIC_FAULT_STAT_PRECISE 0x00000200 |
| #define | NVIC_FAULT_STAT_IBUS 0x00000100 |
| #define | NVIC_FAULT_STAT_MMARV 0x00000080 |
| #define | NVIC_FAULT_STAT_MLSPERR 0x00000020 |
| #define | NVIC_FAULT_STAT_MSTKE 0x00000010 |
| #define | NVIC_FAULT_STAT_MUSTKE 0x00000008 |
| #define | NVIC_FAULT_STAT_DERR 0x00000002 |
| #define | NVIC_FAULT_STAT_IERR 0x00000001 |
| #define | NVIC_HFAULT_STAT_DBG 0x80000000 |
| #define | NVIC_HFAULT_STAT_FORCED 0x40000000 |
| #define | NVIC_HFAULT_STAT_VECT 0x00000002 |
| #define | NVIC_DEBUG_STAT_EXTRNL 0x00000010 |
| #define | NVIC_DEBUG_STAT_VCATCH 0x00000008 |
| #define | NVIC_DEBUG_STAT_DWTTRAP 0x00000004 |
| #define | NVIC_DEBUG_STAT_BKPT 0x00000002 |
| #define | NVIC_DEBUG_STAT_HALTED 0x00000001 |
| #define | NVIC_MM_ADDR_M 0xFFFFFFFF |
| #define | NVIC_MM_ADDR_S 0 |
| #define | NVIC_FAULT_ADDR_M 0xFFFFFFFF |
| #define | NVIC_FAULT_ADDR_S 0 |
| #define | NVIC_CPAC_CP11_M 0x00C00000 |
| #define | NVIC_CPAC_CP11_DIS 0x00000000 |
| #define | NVIC_CPAC_CP11_PRIV 0x00400000 |
| #define | NVIC_CPAC_CP11_FULL 0x00C00000 |
| #define | NVIC_CPAC_CP10_M 0x00300000 |
| #define | NVIC_CPAC_CP10_DIS 0x00000000 |
| #define | NVIC_CPAC_CP10_PRIV 0x00100000 |
| #define | NVIC_CPAC_CP10_FULL 0x00300000 |
| #define | NVIC_MPU_TYPE_IREGION_M 0x00FF0000 |
| #define | NVIC_MPU_TYPE_DREGION_M 0x0000FF00 |
| #define | NVIC_MPU_TYPE_SEPARATE 0x00000001 |
| #define | NVIC_MPU_TYPE_IREGION_S 16 |
| #define | NVIC_MPU_TYPE_DREGION_S 8 |
| #define | NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 |
| #define | NVIC_MPU_CTRL_HFNMIENA 0x00000002 |
| #define | NVIC_MPU_CTRL_ENABLE 0x00000001 |
| #define | NVIC_MPU_NUMBER_M 0x00000007 |
| #define | NVIC_MPU_NUMBER_S 0 |
| #define | NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 |
| #define | NVIC_MPU_BASE_VALID 0x00000010 |
| #define | NVIC_MPU_BASE_REGION_M 0x00000007 |
| #define | NVIC_MPU_BASE_ADDR_S 5 |
| #define | NVIC_MPU_BASE_REGION_S 0 |
| #define | NVIC_MPU_ATTR_XN 0x10000000 |
| #define | NVIC_MPU_ATTR_AP_M 0x07000000 |
| #define | NVIC_MPU_ATTR_TEX_M 0x00380000 |
| #define | NVIC_MPU_ATTR_SHAREABLE 0x00040000 |
| #define | NVIC_MPU_ATTR_CACHEABLE 0x00020000 |
| #define | NVIC_MPU_ATTR_BUFFRABLE 0x00010000 |
| #define | NVIC_MPU_ATTR_SRD_M 0x0000FF00 |
| #define | NVIC_MPU_ATTR_SIZE_M 0x0000003E |
| #define | NVIC_MPU_ATTR_ENABLE 0x00000001 |
| #define | NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 |
| #define | NVIC_MPU_BASE1_VALID 0x00000010 |
| #define | NVIC_MPU_BASE1_REGION_M 0x00000007 |
| #define | NVIC_MPU_BASE1_ADDR_S 5 |
| #define | NVIC_MPU_BASE1_REGION_S 0 |
| #define | NVIC_MPU_ATTR1_XN 0x10000000 |
| #define | NVIC_MPU_ATTR1_AP_M 0x07000000 |
| #define | NVIC_MPU_ATTR1_TEX_M 0x00380000 |
| #define | NVIC_MPU_ATTR1_SHAREABLE 0x00040000 |
| #define | NVIC_MPU_ATTR1_CACHEABLE 0x00020000 |
| #define | NVIC_MPU_ATTR1_BUFFRABLE 0x00010000 |
| #define | NVIC_MPU_ATTR1_SRD_M 0x0000FF00 |
| #define | NVIC_MPU_ATTR1_SIZE_M 0x0000003E |
| #define | NVIC_MPU_ATTR1_ENABLE 0x00000001 |
| #define | NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 |
| #define | NVIC_MPU_BASE2_VALID 0x00000010 |
| #define | NVIC_MPU_BASE2_REGION_M 0x00000007 |
| #define | NVIC_MPU_BASE2_ADDR_S 5 |
| #define | NVIC_MPU_BASE2_REGION_S 0 |
| #define | NVIC_MPU_ATTR2_XN 0x10000000 |
| #define | NVIC_MPU_ATTR2_AP_M 0x07000000 |
| #define | NVIC_MPU_ATTR2_TEX_M 0x00380000 |
| #define | NVIC_MPU_ATTR2_SHAREABLE 0x00040000 |
| #define | NVIC_MPU_ATTR2_CACHEABLE 0x00020000 |
| #define | NVIC_MPU_ATTR2_BUFFRABLE 0x00010000 |
| #define | NVIC_MPU_ATTR2_SRD_M 0x0000FF00 |
| #define | NVIC_MPU_ATTR2_SIZE_M 0x0000003E |
| #define | NVIC_MPU_ATTR2_ENABLE 0x00000001 |
| #define | NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 |
| #define | NVIC_MPU_BASE3_VALID 0x00000010 |
| #define | NVIC_MPU_BASE3_REGION_M 0x00000007 |
| #define | NVIC_MPU_BASE3_ADDR_S 5 |
| #define | NVIC_MPU_BASE3_REGION_S 0 |
| #define | NVIC_MPU_ATTR3_XN 0x10000000 |
| #define | NVIC_MPU_ATTR3_AP_M 0x07000000 |
| #define | NVIC_MPU_ATTR3_TEX_M 0x00380000 |
| #define | NVIC_MPU_ATTR3_SHAREABLE 0x00040000 |
| #define | NVIC_MPU_ATTR3_CACHEABLE 0x00020000 |
| #define | NVIC_MPU_ATTR3_BUFFRABLE 0x00010000 |
| #define | NVIC_MPU_ATTR3_SRD_M 0x0000FF00 |
| #define | NVIC_MPU_ATTR3_SIZE_M 0x0000003E |
| #define | NVIC_MPU_ATTR3_ENABLE 0x00000001 |
| #define | NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 |
| #define | NVIC_DBG_CTRL_DBGKEY 0xA05F0000 |
| #define | NVIC_DBG_CTRL_S_RESET_ST 0x02000000 |
| #define | NVIC_DBG_CTRL_S_RETIRE_ST 0x01000000 |
| #define | NVIC_DBG_CTRL_S_LOCKUP 0x00080000 |
| #define | NVIC_DBG_CTRL_S_SLEEP 0x00040000 |
| #define | NVIC_DBG_CTRL_S_HALT 0x00020000 |
| #define | NVIC_DBG_CTRL_S_REGRDY 0x00010000 |
| #define | NVIC_DBG_CTRL_C_SNAPSTALL 0x00000020 |
| #define | NVIC_DBG_CTRL_C_MASKINT 0x00000008 |
| #define | NVIC_DBG_CTRL_C_STEP 0x00000004 |
| #define | NVIC_DBG_CTRL_C_HALT 0x00000002 |
| #define | NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 |
| #define | NVIC_DBG_XFER_REG_WNR 0x00010000 |
| #define | NVIC_DBG_XFER_REG_SEL_M 0x0000001F |
| #define | NVIC_DBG_XFER_REG_R0 0x00000000 |
| #define | NVIC_DBG_XFER_REG_R1 0x00000001 |
| #define | NVIC_DBG_XFER_REG_R2 0x00000002 |
| #define | NVIC_DBG_XFER_REG_R3 0x00000003 |
| #define | NVIC_DBG_XFER_REG_R4 0x00000004 |
| #define | NVIC_DBG_XFER_REG_R5 0x00000005 |
| #define | NVIC_DBG_XFER_REG_R6 0x00000006 |
| #define | NVIC_DBG_XFER_REG_R7 0x00000007 |
| #define | NVIC_DBG_XFER_REG_R8 0x00000008 |
| #define | NVIC_DBG_XFER_REG_R9 0x00000009 |
| #define | NVIC_DBG_XFER_REG_R10 0x0000000A |
| #define | NVIC_DBG_XFER_REG_R11 0x0000000B |
| #define | NVIC_DBG_XFER_REG_R12 0x0000000C |
| #define | NVIC_DBG_XFER_REG_R13 0x0000000D |
| #define | NVIC_DBG_XFER_REG_R14 0x0000000E |
| #define | NVIC_DBG_XFER_REG_R15 0x0000000F |
| #define | NVIC_DBG_XFER_REG_FLAGS 0x00000010 |
| #define | NVIC_DBG_XFER_REG_MSP 0x00000011 |
| #define | NVIC_DBG_XFER_REG_PSP 0x00000012 |
| #define | NVIC_DBG_XFER_REG_DSP 0x00000013 |
| #define | NVIC_DBG_XFER_REG_CFBP 0x00000014 |
| #define | NVIC_DBG_DATA_M 0xFFFFFFFF |
| #define | NVIC_DBG_DATA_S 0 |
| #define | NVIC_DBG_INT_HARDERR 0x00000400 |
| #define | NVIC_DBG_INT_INTERR 0x00000200 |
| #define | NVIC_DBG_INT_BUSERR 0x00000100 |
| #define | NVIC_DBG_INT_STATERR 0x00000080 |
| #define | NVIC_DBG_INT_CHKERR 0x00000040 |
| #define | NVIC_DBG_INT_NOCPERR 0x00000020 |
| #define | NVIC_DBG_INT_MMERR 0x00000010 |
| #define | NVIC_DBG_INT_RESET 0x00000008 |
| #define | NVIC_DBG_INT_RSTPENDCLR 0x00000004 |
| #define | NVIC_DBG_INT_RSTPENDING 0x00000002 |
| #define | NVIC_DBG_INT_RSTVCATCH 0x00000001 |
| #define | NVIC_SW_TRIG_INTID_M 0x000000FF |
| #define | NVIC_SW_TRIG_INTID_S 0 |
| #define | NVIC_FPCC_ASPEN 0x80000000 |
| #define | NVIC_FPCC_LSPEN 0x40000000 |
| #define | NVIC_FPCC_MONRDY 0x00000100 |
| #define | NVIC_FPCC_BFRDY 0x00000040 |
| #define | NVIC_FPCC_MMRDY 0x00000020 |
| #define | NVIC_FPCC_HFRDY 0x00000010 |
| #define | NVIC_FPCC_THREAD 0x00000008 |
| #define | NVIC_FPCC_USER 0x00000002 |
| #define | NVIC_FPCC_LSPACT 0x00000001 |
| #define | NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 |
| #define | NVIC_FPCA_ADDRESS_S 3 |
| #define | NVIC_FPDSC_AHP 0x04000000 |
| #define | NVIC_FPDSC_DN 0x02000000 |
| #define | NVIC_FPDSC_FZ 0x01000000 |
| #define | NVIC_FPDSC_RMODE_M 0x00C00000 |
| #define | NVIC_FPDSC_RMODE_RN 0x00000000 |
| #define | NVIC_FPDSC_RMODE_RP 0x00400000 |
| #define | NVIC_FPDSC_RMODE_RM 0x00800000 |
| #define | NVIC_FPDSC_RMODE_RZ 0x00C00000 |
| #define | SYSCTL_DID0_CLASS_BLIZZARD 0x00050000 |
| #define ADC0_ACTSS_R (*((volatile uint32_t *)0x40038000)) |
| #define ADC0_CC_R (*((volatile uint32_t *)0x40038FC8)) |
| #define ADC0_CTL_R (*((volatile uint32_t *)0x40038038)) |
| #define ADC0_DCCMP0_R (*((volatile uint32_t *)0x40038E40)) |
| #define ADC0_DCCMP1_R (*((volatile uint32_t *)0x40038E44)) |
| #define ADC0_DCCMP2_R (*((volatile uint32_t *)0x40038E48)) |
| #define ADC0_DCCMP3_R (*((volatile uint32_t *)0x40038E4C)) |
| #define ADC0_DCCMP4_R (*((volatile uint32_t *)0x40038E50)) |
| #define ADC0_DCCMP5_R (*((volatile uint32_t *)0x40038E54)) |
| #define ADC0_DCCMP6_R (*((volatile uint32_t *)0x40038E58)) |
| #define ADC0_DCCMP7_R (*((volatile uint32_t *)0x40038E5C)) |
| #define ADC0_DCCTL0_R (*((volatile uint32_t *)0x40038E00)) |
| #define ADC0_DCCTL1_R (*((volatile uint32_t *)0x40038E04)) |
| #define ADC0_DCCTL2_R (*((volatile uint32_t *)0x40038E08)) |
| #define ADC0_DCCTL3_R (*((volatile uint32_t *)0x40038E0C)) |
| #define ADC0_DCCTL4_R (*((volatile uint32_t *)0x40038E10)) |
| #define ADC0_DCCTL5_R (*((volatile uint32_t *)0x40038E14)) |
| #define ADC0_DCCTL6_R (*((volatile uint32_t *)0x40038E18)) |
| #define ADC0_DCCTL7_R (*((volatile uint32_t *)0x40038E1C)) |
| #define ADC0_DCISC_R (*((volatile uint32_t *)0x40038034)) |
| #define ADC0_DCRIC_R (*((volatile uint32_t *)0x40038D00)) |
| #define ADC0_EMUX_R (*((volatile uint32_t *)0x40038014)) |
| #define ADC0_IM_R (*((volatile uint32_t *)0x40038008)) |
| #define ADC0_ISC_R (*((volatile uint32_t *)0x4003800C)) |
| #define ADC0_OSTAT_R (*((volatile uint32_t *)0x40038010)) |
| #define ADC0_PC_R (*((volatile uint32_t *)0x40038FC4)) |
| #define ADC0_PP_R (*((volatile uint32_t *)0x40038FC0)) |
| #define ADC0_PSSI_R (*((volatile uint32_t *)0x40038028)) |
| #define ADC0_RIS_R (*((volatile uint32_t *)0x40038004)) |
| #define ADC0_SAC_R (*((volatile uint32_t *)0x40038030)) |
| #define ADC0_SPC_R (*((volatile uint32_t *)0x40038024)) |
| #define ADC0_SSCTL0_R (*((volatile uint32_t *)0x40038044)) |
| #define ADC0_SSCTL1_R (*((volatile uint32_t *)0x40038064)) |
| #define ADC0_SSCTL2_R (*((volatile uint32_t *)0x40038084)) |
| #define ADC0_SSCTL3_R (*((volatile uint32_t *)0x400380A4)) |
| #define ADC0_SSDC0_R (*((volatile uint32_t *)0x40038054)) |
| #define ADC0_SSDC1_R (*((volatile uint32_t *)0x40038074)) |
| #define ADC0_SSDC2_R (*((volatile uint32_t *)0x40038094)) |
| #define ADC0_SSDC3_R (*((volatile uint32_t *)0x400380B4)) |
| #define ADC0_SSEMUX0_R (*((volatile uint32_t *)0x40038058)) |
| #define ADC0_SSEMUX1_R (*((volatile uint32_t *)0x40038078)) |
| #define ADC0_SSEMUX2_R (*((volatile uint32_t *)0x40038098)) |
| #define ADC0_SSEMUX3_R (*((volatile uint32_t *)0x400380B8)) |
| #define ADC0_SSFIFO0_R (*((volatile uint32_t *)0x40038048)) |
| #define ADC0_SSFIFO1_R (*((volatile uint32_t *)0x40038068)) |
| #define ADC0_SSFIFO2_R (*((volatile uint32_t *)0x40038088)) |
| #define ADC0_SSFIFO3_R (*((volatile uint32_t *)0x400380A8)) |
| #define ADC0_SSFSTAT0_R (*((volatile uint32_t *)0x4003804C)) |
| #define ADC0_SSFSTAT1_R (*((volatile uint32_t *)0x4003806C)) |
| #define ADC0_SSFSTAT2_R (*((volatile uint32_t *)0x4003808C)) |
| #define ADC0_SSFSTAT3_R (*((volatile uint32_t *)0x400380AC)) |
| #define ADC0_SSMUX0_R (*((volatile uint32_t *)0x40038040)) |
| #define ADC0_SSMUX1_R (*((volatile uint32_t *)0x40038060)) |
| #define ADC0_SSMUX2_R (*((volatile uint32_t *)0x40038080)) |
| #define ADC0_SSMUX3_R (*((volatile uint32_t *)0x400380A0)) |
| #define ADC0_SSOP0_R (*((volatile uint32_t *)0x40038050)) |
| #define ADC0_SSOP1_R (*((volatile uint32_t *)0x40038070)) |
| #define ADC0_SSOP2_R (*((volatile uint32_t *)0x40038090)) |
| #define ADC0_SSOP3_R (*((volatile uint32_t *)0x400380B0)) |
| #define ADC0_SSPRI_R (*((volatile uint32_t *)0x40038020)) |
| #define ADC0_TSSEL_R (*((volatile uint32_t *)0x4003801C)) |
| #define ADC0_USTAT_R (*((volatile uint32_t *)0x40038018)) |
| #define ADC1_ACTSS_R (*((volatile uint32_t *)0x40039000)) |
| #define ADC1_CC_R (*((volatile uint32_t *)0x40039FC8)) |
| #define ADC1_CTL_R (*((volatile uint32_t *)0x40039038)) |
| #define ADC1_DCCMP0_R (*((volatile uint32_t *)0x40039E40)) |
| #define ADC1_DCCMP1_R (*((volatile uint32_t *)0x40039E44)) |
| #define ADC1_DCCMP2_R (*((volatile uint32_t *)0x40039E48)) |
| #define ADC1_DCCMP3_R (*((volatile uint32_t *)0x40039E4C)) |
| #define ADC1_DCCMP4_R (*((volatile uint32_t *)0x40039E50)) |
| #define ADC1_DCCMP5_R (*((volatile uint32_t *)0x40039E54)) |
| #define ADC1_DCCMP6_R (*((volatile uint32_t *)0x40039E58)) |
| #define ADC1_DCCMP7_R (*((volatile uint32_t *)0x40039E5C)) |
| #define ADC1_DCCTL0_R (*((volatile uint32_t *)0x40039E00)) |
| #define ADC1_DCCTL1_R (*((volatile uint32_t *)0x40039E04)) |
| #define ADC1_DCCTL2_R (*((volatile uint32_t *)0x40039E08)) |
| #define ADC1_DCCTL3_R (*((volatile uint32_t *)0x40039E0C)) |
| #define ADC1_DCCTL4_R (*((volatile uint32_t *)0x40039E10)) |
| #define ADC1_DCCTL5_R (*((volatile uint32_t *)0x40039E14)) |
| #define ADC1_DCCTL6_R (*((volatile uint32_t *)0x40039E18)) |
| #define ADC1_DCCTL7_R (*((volatile uint32_t *)0x40039E1C)) |
| #define ADC1_DCISC_R (*((volatile uint32_t *)0x40039034)) |
| #define ADC1_DCRIC_R (*((volatile uint32_t *)0x40039D00)) |
| #define ADC1_EMUX_R (*((volatile uint32_t *)0x40039014)) |
| #define ADC1_IM_R (*((volatile uint32_t *)0x40039008)) |
| #define ADC1_ISC_R (*((volatile uint32_t *)0x4003900C)) |
| #define ADC1_OSTAT_R (*((volatile uint32_t *)0x40039010)) |
| #define ADC1_PC_R (*((volatile uint32_t *)0x40039FC4)) |
| #define ADC1_PP_R (*((volatile uint32_t *)0x40039FC0)) |
| #define ADC1_PSSI_R (*((volatile uint32_t *)0x40039028)) |
| #define ADC1_RIS_R (*((volatile uint32_t *)0x40039004)) |
| #define ADC1_SAC_R (*((volatile uint32_t *)0x40039030)) |
| #define ADC1_SPC_R (*((volatile uint32_t *)0x40039024)) |
| #define ADC1_SSCTL0_R (*((volatile uint32_t *)0x40039044)) |
| #define ADC1_SSCTL1_R (*((volatile uint32_t *)0x40039064)) |
| #define ADC1_SSCTL2_R (*((volatile uint32_t *)0x40039084)) |
| #define ADC1_SSCTL3_R (*((volatile uint32_t *)0x400390A4)) |
| #define ADC1_SSDC0_R (*((volatile uint32_t *)0x40039054)) |
| #define ADC1_SSDC1_R (*((volatile uint32_t *)0x40039074)) |
| #define ADC1_SSDC2_R (*((volatile uint32_t *)0x40039094)) |
| #define ADC1_SSDC3_R (*((volatile uint32_t *)0x400390B4)) |
| #define ADC1_SSEMUX0_R (*((volatile uint32_t *)0x40039058)) |
| #define ADC1_SSEMUX1_R (*((volatile uint32_t *)0x40039078)) |
| #define ADC1_SSEMUX2_R (*((volatile uint32_t *)0x40039098)) |
| #define ADC1_SSEMUX3_R (*((volatile uint32_t *)0x400390B8)) |
| #define ADC1_SSFIFO0_R (*((volatile uint32_t *)0x40039048)) |
| #define ADC1_SSFIFO1_R (*((volatile uint32_t *)0x40039068)) |
| #define ADC1_SSFIFO2_R (*((volatile uint32_t *)0x40039088)) |
| #define ADC1_SSFIFO3_R (*((volatile uint32_t *)0x400390A8)) |
| #define ADC1_SSFSTAT0_R (*((volatile uint32_t *)0x4003904C)) |
| #define ADC1_SSFSTAT1_R (*((volatile uint32_t *)0x4003906C)) |
| #define ADC1_SSFSTAT2_R (*((volatile uint32_t *)0x4003908C)) |
| #define ADC1_SSFSTAT3_R (*((volatile uint32_t *)0x400390AC)) |
| #define ADC1_SSMUX0_R (*((volatile uint32_t *)0x40039040)) |
| #define ADC1_SSMUX1_R (*((volatile uint32_t *)0x40039060)) |
| #define ADC1_SSMUX2_R (*((volatile uint32_t *)0x40039080)) |
| #define ADC1_SSMUX3_R (*((volatile uint32_t *)0x400390A0)) |
| #define ADC1_SSOP0_R (*((volatile uint32_t *)0x40039050)) |
| #define ADC1_SSOP1_R (*((volatile uint32_t *)0x40039070)) |
| #define ADC1_SSOP2_R (*((volatile uint32_t *)0x40039090)) |
| #define ADC1_SSOP3_R (*((volatile uint32_t *)0x400390B0)) |
| #define ADC1_SSPRI_R (*((volatile uint32_t *)0x40039020)) |
| #define ADC1_TSSEL_R (*((volatile uint32_t *)0x4003901C)) |
| #define ADC1_USTAT_R (*((volatile uint32_t *)0x40039018)) |
| #define ADC_ACTSS_ASEN0 0x00000001 |
| #define ADC_ACTSS_ASEN1 0x00000002 |
| #define ADC_ACTSS_ASEN2 0x00000004 |
| #define ADC_ACTSS_ASEN3 0x00000008 |
| #define ADC_ACTSS_BUSY 0x00010000 |
| #define ADC_CC_CS_M 0x0000000F |
| #define ADC_CC_CS_PIOSC 0x00000001 |
| #define ADC_CC_CS_SYSPLL 0x00000000 |
| #define ADC_CTL_VREF_EXT_3V 0x00000001 |
| #define ADC_CTL_VREF_INTERNAL 0x00000000 |
| #define ADC_CTL_VREF_M 0x00000001 |
| #define ADC_DCCMP0_COMP0_M 0x00000FFF |
| #define ADC_DCCMP0_COMP0_S 0 |
| #define ADC_DCCMP0_COMP1_M 0x0FFF0000 |
| #define ADC_DCCMP0_COMP1_S 16 |
| #define ADC_DCCMP1_COMP0_M 0x00000FFF |
| #define ADC_DCCMP1_COMP0_S 0 |
| #define ADC_DCCMP1_COMP1_M 0x0FFF0000 |
| #define ADC_DCCMP1_COMP1_S 16 |
| #define ADC_DCCMP2_COMP0_M 0x00000FFF |
| #define ADC_DCCMP2_COMP0_S 0 |
| #define ADC_DCCMP2_COMP1_M 0x0FFF0000 |
| #define ADC_DCCMP2_COMP1_S 16 |
| #define ADC_DCCMP3_COMP0_M 0x00000FFF |
| #define ADC_DCCMP3_COMP0_S 0 |
| #define ADC_DCCMP3_COMP1_M 0x0FFF0000 |
| #define ADC_DCCMP3_COMP1_S 16 |
| #define ADC_DCCMP4_COMP0_M 0x00000FFF |
| #define ADC_DCCMP4_COMP0_S 0 |
| #define ADC_DCCMP4_COMP1_M 0x0FFF0000 |
| #define ADC_DCCMP4_COMP1_S 16 |
| #define ADC_DCCMP5_COMP0_M 0x00000FFF |
| #define ADC_DCCMP5_COMP0_S 0 |
| #define ADC_DCCMP5_COMP1_M 0x0FFF0000 |
| #define ADC_DCCMP5_COMP1_S 16 |
| #define ADC_DCCMP6_COMP0_M 0x00000FFF |
| #define ADC_DCCMP6_COMP0_S 0 |
| #define ADC_DCCMP6_COMP1_M 0x0FFF0000 |
| #define ADC_DCCMP6_COMP1_S 16 |
| #define ADC_DCCMP7_COMP0_M 0x00000FFF |
| #define ADC_DCCMP7_COMP0_S 0 |
| #define ADC_DCCMP7_COMP1_M 0x0FFF0000 |
| #define ADC_DCCMP7_COMP1_S 16 |
| #define ADC_DCCTL0_CIC_HIGH 0x0000000C |
| #define ADC_DCCTL0_CIC_LOW 0x00000000 |
| #define ADC_DCCTL0_CIC_M 0x0000000C |
| #define ADC_DCCTL0_CIC_MID 0x00000004 |
| #define ADC_DCCTL0_CIE 0x00000010 |
| #define ADC_DCCTL0_CIM_ALWAYS 0x00000000 |
| #define ADC_DCCTL0_CIM_HALWAYS 0x00000002 |
| #define ADC_DCCTL0_CIM_HONCE 0x00000003 |
| #define ADC_DCCTL0_CIM_M 0x00000003 |
| #define ADC_DCCTL0_CIM_ONCE 0x00000001 |
| #define ADC_DCCTL0_CTC_HIGH 0x00000C00 |
| #define ADC_DCCTL0_CTC_LOW 0x00000000 |
| #define ADC_DCCTL0_CTC_M 0x00000C00 |
| #define ADC_DCCTL0_CTC_MID 0x00000400 |
| #define ADC_DCCTL0_CTE 0x00001000 |
| #define ADC_DCCTL0_CTM_ALWAYS 0x00000000 |
| #define ADC_DCCTL0_CTM_HALWAYS 0x00000200 |
| #define ADC_DCCTL0_CTM_HONCE 0x00000300 |
| #define ADC_DCCTL0_CTM_M 0x00000300 |
| #define ADC_DCCTL0_CTM_ONCE 0x00000100 |
| #define ADC_DCCTL1_CIC_HIGH 0x0000000C |
| #define ADC_DCCTL1_CIC_LOW 0x00000000 |
| #define ADC_DCCTL1_CIC_M 0x0000000C |
| #define ADC_DCCTL1_CIC_MID 0x00000004 |
| #define ADC_DCCTL1_CIE 0x00000010 |
| #define ADC_DCCTL1_CIM_ALWAYS 0x00000000 |
| #define ADC_DCCTL1_CIM_HALWAYS 0x00000002 |
| #define ADC_DCCTL1_CIM_HONCE 0x00000003 |
| #define ADC_DCCTL1_CIM_M 0x00000003 |
| #define ADC_DCCTL1_CIM_ONCE 0x00000001 |
| #define ADC_DCCTL1_CTC_HIGH 0x00000C00 |
| #define ADC_DCCTL1_CTC_LOW 0x00000000 |
| #define ADC_DCCTL1_CTC_M 0x00000C00 |
| #define ADC_DCCTL1_CTC_MID 0x00000400 |
| #define ADC_DCCTL1_CTE 0x00001000 |
| #define ADC_DCCTL1_CTM_ALWAYS 0x00000000 |
| #define ADC_DCCTL1_CTM_HALWAYS 0x00000200 |
| #define ADC_DCCTL1_CTM_HONCE 0x00000300 |
| #define ADC_DCCTL1_CTM_M 0x00000300 |
| #define ADC_DCCTL1_CTM_ONCE 0x00000100 |
| #define ADC_DCCTL2_CIC_HIGH 0x0000000C |
| #define ADC_DCCTL2_CIC_LOW 0x00000000 |
| #define ADC_DCCTL2_CIC_M 0x0000000C |
| #define ADC_DCCTL2_CIC_MID 0x00000004 |
| #define ADC_DCCTL2_CIE 0x00000010 |
| #define ADC_DCCTL2_CIM_ALWAYS 0x00000000 |
| #define ADC_DCCTL2_CIM_HALWAYS 0x00000002 |
| #define ADC_DCCTL2_CIM_HONCE 0x00000003 |
| #define ADC_DCCTL2_CIM_M 0x00000003 |
| #define ADC_DCCTL2_CIM_ONCE 0x00000001 |
| #define ADC_DCCTL2_CTC_HIGH 0x00000C00 |
| #define ADC_DCCTL2_CTC_LOW 0x00000000 |
| #define ADC_DCCTL2_CTC_M 0x00000C00 |
| #define ADC_DCCTL2_CTC_MID 0x00000400 |
| #define ADC_DCCTL2_CTE 0x00001000 |
| #define ADC_DCCTL2_CTM_ALWAYS 0x00000000 |
| #define ADC_DCCTL2_CTM_HALWAYS 0x00000200 |
| #define ADC_DCCTL2_CTM_HONCE 0x00000300 |
| #define ADC_DCCTL2_CTM_M 0x00000300 |
| #define ADC_DCCTL2_CTM_ONCE 0x00000100 |
| #define ADC_DCCTL3_CIC_HIGH 0x0000000C |
| #define ADC_DCCTL3_CIC_LOW 0x00000000 |
| #define ADC_DCCTL3_CIC_M 0x0000000C |
| #define ADC_DCCTL3_CIC_MID 0x00000004 |
| #define ADC_DCCTL3_CIE 0x00000010 |
| #define ADC_DCCTL3_CIM_ALWAYS 0x00000000 |
| #define ADC_DCCTL3_CIM_HALWAYS 0x00000002 |
| #define ADC_DCCTL3_CIM_HONCE 0x00000003 |
| #define ADC_DCCTL3_CIM_M 0x00000003 |
| #define ADC_DCCTL3_CIM_ONCE 0x00000001 |
| #define ADC_DCCTL3_CTC_HIGH 0x00000C00 |
| #define ADC_DCCTL3_CTC_LOW 0x00000000 |
| #define ADC_DCCTL3_CTC_M 0x00000C00 |
| #define ADC_DCCTL3_CTC_MID 0x00000400 |
| #define ADC_DCCTL3_CTE 0x00001000 |
| #define ADC_DCCTL3_CTM_ALWAYS 0x00000000 |
| #define ADC_DCCTL3_CTM_HALWAYS 0x00000200 |
| #define ADC_DCCTL3_CTM_HONCE 0x00000300 |
| #define ADC_DCCTL3_CTM_M 0x00000300 |
| #define ADC_DCCTL3_CTM_ONCE 0x00000100 |
| #define ADC_DCCTL4_CIC_HIGH 0x0000000C |
| #define ADC_DCCTL4_CIC_LOW 0x00000000 |
| #define ADC_DCCTL4_CIC_M 0x0000000C |
| #define ADC_DCCTL4_CIC_MID 0x00000004 |
| #define ADC_DCCTL4_CIE 0x00000010 |
| #define ADC_DCCTL4_CIM_ALWAYS 0x00000000 |
| #define ADC_DCCTL4_CIM_HALWAYS 0x00000002 |
| #define ADC_DCCTL4_CIM_HONCE 0x00000003 |
| #define ADC_DCCTL4_CIM_M 0x00000003 |
| #define ADC_DCCTL4_CIM_ONCE 0x00000001 |
| #define ADC_DCCTL4_CTC_HIGH 0x00000C00 |
| #define ADC_DCCTL4_CTC_LOW 0x00000000 |
| #define ADC_DCCTL4_CTC_M 0x00000C00 |
| #define ADC_DCCTL4_CTC_MID 0x00000400 |
| #define ADC_DCCTL4_CTE 0x00001000 |
| #define ADC_DCCTL4_CTM_ALWAYS 0x00000000 |
| #define ADC_DCCTL4_CTM_HALWAYS 0x00000200 |
| #define ADC_DCCTL4_CTM_HONCE 0x00000300 |
| #define ADC_DCCTL4_CTM_M 0x00000300 |
| #define ADC_DCCTL4_CTM_ONCE 0x00000100 |
| #define ADC_DCCTL5_CIC_HIGH 0x0000000C |
| #define ADC_DCCTL5_CIC_LOW 0x00000000 |
| #define ADC_DCCTL5_CIC_M 0x0000000C |
| #define ADC_DCCTL5_CIC_MID 0x00000004 |
| #define ADC_DCCTL5_CIE 0x00000010 |
| #define ADC_DCCTL5_CIM_ALWAYS 0x00000000 |
| #define ADC_DCCTL5_CIM_HALWAYS 0x00000002 |
| #define ADC_DCCTL5_CIM_HONCE 0x00000003 |
| #define ADC_DCCTL5_CIM_M 0x00000003 |
| #define ADC_DCCTL5_CIM_ONCE 0x00000001 |
| #define ADC_DCCTL5_CTC_HIGH 0x00000C00 |
| #define ADC_DCCTL5_CTC_LOW 0x00000000 |
| #define ADC_DCCTL5_CTC_M 0x00000C00 |
| #define ADC_DCCTL5_CTC_MID 0x00000400 |
| #define ADC_DCCTL5_CTE 0x00001000 |
| #define ADC_DCCTL5_CTM_ALWAYS 0x00000000 |
| #define ADC_DCCTL5_CTM_HALWAYS 0x00000200 |
| #define ADC_DCCTL5_CTM_HONCE 0x00000300 |
| #define ADC_DCCTL5_CTM_M 0x00000300 |
| #define ADC_DCCTL5_CTM_ONCE 0x00000100 |
| #define ADC_DCCTL6_CIC_HIGH 0x0000000C |
| #define ADC_DCCTL6_CIC_LOW 0x00000000 |
| #define ADC_DCCTL6_CIC_M 0x0000000C |
| #define ADC_DCCTL6_CIC_MID 0x00000004 |
| #define ADC_DCCTL6_CIE 0x00000010 |
| #define ADC_DCCTL6_CIM_ALWAYS 0x00000000 |
| #define ADC_DCCTL6_CIM_HALWAYS 0x00000002 |
| #define ADC_DCCTL6_CIM_HONCE 0x00000003 |
| #define ADC_DCCTL6_CIM_M 0x00000003 |
| #define ADC_DCCTL6_CIM_ONCE 0x00000001 |
| #define ADC_DCCTL6_CTC_HIGH 0x00000C00 |
| #define ADC_DCCTL6_CTC_LOW 0x00000000 |
| #define ADC_DCCTL6_CTC_M 0x00000C00 |
| #define ADC_DCCTL6_CTC_MID 0x00000400 |
| #define ADC_DCCTL6_CTE 0x00001000 |
| #define ADC_DCCTL6_CTM_ALWAYS 0x00000000 |
| #define ADC_DCCTL6_CTM_HALWAYS 0x00000200 |
| #define ADC_DCCTL6_CTM_HONCE 0x00000300 |
| #define ADC_DCCTL6_CTM_M 0x00000300 |
| #define ADC_DCCTL6_CTM_ONCE 0x00000100 |
| #define ADC_DCCTL7_CIC_HIGH 0x0000000C |
| #define ADC_DCCTL7_CIC_LOW 0x00000000 |
| #define ADC_DCCTL7_CIC_M 0x0000000C |
| #define ADC_DCCTL7_CIC_MID 0x00000004 |
| #define ADC_DCCTL7_CIE 0x00000010 |
| #define ADC_DCCTL7_CIM_ALWAYS 0x00000000 |
| #define ADC_DCCTL7_CIM_HALWAYS 0x00000002 |
| #define ADC_DCCTL7_CIM_HONCE 0x00000003 |
| #define ADC_DCCTL7_CIM_M 0x00000003 |
| #define ADC_DCCTL7_CIM_ONCE 0x00000001 |
| #define ADC_DCCTL7_CTC_HIGH 0x00000C00 |
| #define ADC_DCCTL7_CTC_LOW 0x00000000 |
| #define ADC_DCCTL7_CTC_M 0x00000C00 |
| #define ADC_DCCTL7_CTC_MID 0x00000400 |
| #define ADC_DCCTL7_CTE 0x00001000 |
| #define ADC_DCCTL7_CTM_ALWAYS 0x00000000 |
| #define ADC_DCCTL7_CTM_HALWAYS 0x00000200 |
| #define ADC_DCCTL7_CTM_HONCE 0x00000300 |
| #define ADC_DCCTL7_CTM_M 0x00000300 |
| #define ADC_DCCTL7_CTM_ONCE 0x00000100 |
| #define ADC_DCISC_DCINT0 0x00000001 |
| #define ADC_DCISC_DCINT1 0x00000002 |
| #define ADC_DCISC_DCINT2 0x00000004 |
| #define ADC_DCISC_DCINT3 0x00000008 |
| #define ADC_DCISC_DCINT4 0x00000010 |
| #define ADC_DCISC_DCINT5 0x00000020 |
| #define ADC_DCISC_DCINT6 0x00000040 |
| #define ADC_DCISC_DCINT7 0x00000080 |
| #define ADC_DCRIC_DCINT0 0x00000001 |
| #define ADC_DCRIC_DCINT1 0x00000002 |
| #define ADC_DCRIC_DCINT2 0x00000004 |
| #define ADC_DCRIC_DCINT3 0x00000008 |
| #define ADC_DCRIC_DCINT4 0x00000010 |
| #define ADC_DCRIC_DCINT5 0x00000020 |
| #define ADC_DCRIC_DCINT6 0x00000040 |
| #define ADC_DCRIC_DCINT7 0x00000080 |
| #define ADC_DCRIC_DCTRIG0 0x00010000 |
| #define ADC_DCRIC_DCTRIG1 0x00020000 |
| #define ADC_DCRIC_DCTRIG2 0x00040000 |
| #define ADC_DCRIC_DCTRIG3 0x00080000 |
| #define ADC_DCRIC_DCTRIG4 0x00100000 |
| #define ADC_DCRIC_DCTRIG5 0x00200000 |
| #define ADC_DCRIC_DCTRIG6 0x00400000 |
| #define ADC_DCRIC_DCTRIG7 0x00800000 |
| #define ADC_EMUX_EM0_ALWAYS 0x0000000F |
| #define ADC_EMUX_EM0_COMP0 0x00000001 |
| #define ADC_EMUX_EM0_COMP1 0x00000002 |
| #define ADC_EMUX_EM0_COMP2 0x00000003 |
| #define ADC_EMUX_EM0_EXTERNAL 0x00000004 |
| #define ADC_EMUX_EM0_M 0x0000000F |
| #define ADC_EMUX_EM0_PROCESSOR 0x00000000 |
| #define ADC_EMUX_EM0_PWM0 0x00000006 |
| #define ADC_EMUX_EM0_PWM1 0x00000007 |
| #define ADC_EMUX_EM0_PWM2 0x00000008 |
| #define ADC_EMUX_EM0_PWM3 0x00000009 |
| #define ADC_EMUX_EM0_TIMER 0x00000005 |
| #define ADC_EMUX_EM1_ALWAYS 0x000000F0 |
| #define ADC_EMUX_EM1_COMP0 0x00000010 |
| #define ADC_EMUX_EM1_COMP1 0x00000020 |
| #define ADC_EMUX_EM1_COMP2 0x00000030 |
| #define ADC_EMUX_EM1_EXTERNAL 0x00000040 |
| #define ADC_EMUX_EM1_M 0x000000F0 |
| #define ADC_EMUX_EM1_PROCESSOR 0x00000000 |
| #define ADC_EMUX_EM1_PWM0 0x00000060 |
| #define ADC_EMUX_EM1_PWM1 0x00000070 |
| #define ADC_EMUX_EM1_PWM2 0x00000080 |
| #define ADC_EMUX_EM1_PWM3 0x00000090 |
| #define ADC_EMUX_EM1_TIMER 0x00000050 |
| #define ADC_EMUX_EM2_ALWAYS 0x00000F00 |
| #define ADC_EMUX_EM2_COMP0 0x00000100 |
| #define ADC_EMUX_EM2_COMP1 0x00000200 |
| #define ADC_EMUX_EM2_COMP2 0x00000300 |
| #define ADC_EMUX_EM2_EXTERNAL 0x00000400 |
| #define ADC_EMUX_EM2_M 0x00000F00 |
| #define ADC_EMUX_EM2_PROCESSOR 0x00000000 |
| #define ADC_EMUX_EM2_PWM0 0x00000600 |
| #define ADC_EMUX_EM2_PWM1 0x00000700 |
| #define ADC_EMUX_EM2_PWM2 0x00000800 |
| #define ADC_EMUX_EM2_PWM3 0x00000900 |
| #define ADC_EMUX_EM2_TIMER 0x00000500 |
| #define ADC_EMUX_EM3_ALWAYS 0x0000F000 |
| #define ADC_EMUX_EM3_COMP0 0x00001000 |
| #define ADC_EMUX_EM3_COMP1 0x00002000 |
| #define ADC_EMUX_EM3_COMP2 0x00003000 |
| #define ADC_EMUX_EM3_EXTERNAL 0x00004000 |
| #define ADC_EMUX_EM3_M 0x0000F000 |
| #define ADC_EMUX_EM3_PROCESSOR 0x00000000 |
| #define ADC_EMUX_EM3_PWM0 0x00006000 |
| #define ADC_EMUX_EM3_PWM1 0x00007000 |
| #define ADC_EMUX_EM3_PWM2 0x00008000 |
| #define ADC_EMUX_EM3_PWM3 0x00009000 |
| #define ADC_EMUX_EM3_TIMER 0x00005000 |
| #define ADC_IM_DCONSS0 0x00010000 |
| #define ADC_IM_DCONSS1 0x00020000 |
| #define ADC_IM_DCONSS2 0x00040000 |
| #define ADC_IM_DCONSS3 0x00080000 |
| #define ADC_IM_MASK0 0x00000001 |
| #define ADC_IM_MASK1 0x00000002 |
| #define ADC_IM_MASK2 0x00000004 |
| #define ADC_IM_MASK3 0x00000008 |
| #define ADC_ISC_DCINSS0 0x00010000 |
| #define ADC_ISC_DCINSS1 0x00020000 |
| #define ADC_ISC_DCINSS2 0x00040000 |
| #define ADC_ISC_DCINSS3 0x00080000 |
| #define ADC_ISC_IN0 0x00000001 |
| #define ADC_ISC_IN1 0x00000002 |
| #define ADC_ISC_IN2 0x00000004 |
| #define ADC_ISC_IN3 0x00000008 |
| #define ADC_OSTAT_OV0 0x00000001 |
| #define ADC_OSTAT_OV1 0x00000002 |
| #define ADC_OSTAT_OV2 0x00000004 |
| #define ADC_OSTAT_OV3 0x00000008 |
| #define ADC_PC_SR_125K 0x00000001 |
| #define ADC_PC_SR_1M 0x00000007 |
| #define ADC_PC_SR_250K 0x00000003 |
| #define ADC_PC_SR_500K 0x00000005 |
| #define ADC_PC_SR_M 0x0000000F |
| #define ADC_PP_CH_M 0x000003F0 |
| #define ADC_PP_CH_S 4 |
| #define ADC_PP_DC_M 0x0000FC00 |
| #define ADC_PP_DC_S 10 |
| #define ADC_PP_MSR_125K 0x00000001 |
| #define ADC_PP_MSR_1M 0x00000007 |
| #define ADC_PP_MSR_250K 0x00000003 |
| #define ADC_PP_MSR_500K 0x00000005 |
| #define ADC_PP_MSR_M 0x0000000F |
| #define ADC_PP_RSL_M 0x007C0000 |
| #define ADC_PP_RSL_S 18 |
| #define ADC_PP_TS 0x00800000 |
| #define ADC_PP_TYPE_M 0x00030000 |
| #define ADC_PP_TYPE_SAR 0x00000000 |
| #define ADC_PSSI_GSYNC 0x80000000 |
| #define ADC_PSSI_SS0 0x00000001 |
| #define ADC_PSSI_SS1 0x00000002 |
| #define ADC_PSSI_SS2 0x00000004 |
| #define ADC_PSSI_SS3 0x00000008 |
| #define ADC_PSSI_SYNCWAIT 0x08000000 |
| #define ADC_RIS_INR0 0x00000001 |
| #define ADC_RIS_INR1 0x00000002 |
| #define ADC_RIS_INR2 0x00000004 |
| #define ADC_RIS_INR3 0x00000008 |
| #define ADC_RIS_INRDC 0x00010000 |
| #define ADC_SAC_AVG_16X 0x00000004 |
| #define ADC_SAC_AVG_2X 0x00000001 |
| #define ADC_SAC_AVG_32X 0x00000005 |
| #define ADC_SAC_AVG_4X 0x00000002 |
| #define ADC_SAC_AVG_64X 0x00000006 |
| #define ADC_SAC_AVG_8X 0x00000003 |
| #define ADC_SAC_AVG_M 0x00000007 |
| #define ADC_SAC_AVG_OFF 0x00000000 |
| #define ADC_SPC_PHASE_0 0x00000000 |
| #define ADC_SPC_PHASE_112_5 0x00000005 |
| #define ADC_SPC_PHASE_135 0x00000006 |
| #define ADC_SPC_PHASE_157_5 0x00000007 |
| #define ADC_SPC_PHASE_180 0x00000008 |
| #define ADC_SPC_PHASE_202_5 0x00000009 |
| #define ADC_SPC_PHASE_225 0x0000000A |
| #define ADC_SPC_PHASE_22_5 0x00000001 |
| #define ADC_SPC_PHASE_247_5 0x0000000B |
| #define ADC_SPC_PHASE_270 0x0000000C |
| #define ADC_SPC_PHASE_292_5 0x0000000D |
| #define ADC_SPC_PHASE_315 0x0000000E |
| #define ADC_SPC_PHASE_337_5 0x0000000F |
| #define ADC_SPC_PHASE_45 0x00000002 |
| #define ADC_SPC_PHASE_67_5 0x00000003 |
| #define ADC_SPC_PHASE_90 0x00000004 |
| #define ADC_SPC_PHASE_M 0x0000000F |
| #define ADC_SSCTL0_D0 0x00000001 |
| #define ADC_SSCTL0_D1 0x00000010 |
| #define ADC_SSCTL0_D2 0x00000100 |
| #define ADC_SSCTL0_D3 0x00001000 |
| #define ADC_SSCTL0_D4 0x00010000 |
| #define ADC_SSCTL0_D5 0x00100000 |
| #define ADC_SSCTL0_D6 0x01000000 |
| #define ADC_SSCTL0_D7 0x10000000 |
| #define ADC_SSCTL0_END0 0x00000002 |
| #define ADC_SSCTL0_END1 0x00000020 |
| #define ADC_SSCTL0_END2 0x00000200 |
| #define ADC_SSCTL0_END3 0x00002000 |
| #define ADC_SSCTL0_END4 0x00020000 |
| #define ADC_SSCTL0_END5 0x00200000 |
| #define ADC_SSCTL0_END6 0x02000000 |
| #define ADC_SSCTL0_END7 0x20000000 |
| #define ADC_SSCTL0_IE0 0x00000004 |
| #define ADC_SSCTL0_IE1 0x00000040 |
| #define ADC_SSCTL0_IE2 0x00000400 |
| #define ADC_SSCTL0_IE3 0x00004000 |
| #define ADC_SSCTL0_IE4 0x00040000 |
| #define ADC_SSCTL0_IE5 0x00400000 |
| #define ADC_SSCTL0_IE6 0x04000000 |
| #define ADC_SSCTL0_IE7 0x40000000 |
| #define ADC_SSCTL0_TS0 0x00000008 |
| #define ADC_SSCTL0_TS1 0x00000080 |
| #define ADC_SSCTL0_TS2 0x00000800 |
| #define ADC_SSCTL0_TS3 0x00008000 |
| #define ADC_SSCTL0_TS4 0x00080000 |
| #define ADC_SSCTL0_TS5 0x00800000 |
| #define ADC_SSCTL0_TS6 0x08000000 |
| #define ADC_SSCTL0_TS7 0x80000000 |
| #define ADC_SSCTL1_D0 0x00000001 |
| #define ADC_SSCTL1_D1 0x00000010 |
| #define ADC_SSCTL1_D2 0x00000100 |
| #define ADC_SSCTL1_D3 0x00001000 |
| #define ADC_SSCTL1_END0 0x00000002 |
| #define ADC_SSCTL1_END1 0x00000020 |
| #define ADC_SSCTL1_END2 0x00000200 |
| #define ADC_SSCTL1_END3 0x00002000 |
| #define ADC_SSCTL1_IE0 0x00000004 |
| #define ADC_SSCTL1_IE1 0x00000040 |
| #define ADC_SSCTL1_IE2 0x00000400 |
| #define ADC_SSCTL1_IE3 0x00004000 |
| #define ADC_SSCTL1_TS0 0x00000008 |
| #define ADC_SSCTL1_TS1 0x00000080 |
| #define ADC_SSCTL1_TS2 0x00000800 |
| #define ADC_SSCTL1_TS3 0x00008000 |
| #define ADC_SSCTL2_D0 0x00000001 |
| #define ADC_SSCTL2_D1 0x00000010 |
| #define ADC_SSCTL2_D2 0x00000100 |
| #define ADC_SSCTL2_D3 0x00001000 |
| #define ADC_SSCTL2_END0 0x00000002 |
| #define ADC_SSCTL2_END1 0x00000020 |
| #define ADC_SSCTL2_END2 0x00000200 |
| #define ADC_SSCTL2_END3 0x00002000 |
| #define ADC_SSCTL2_IE0 0x00000004 |
| #define ADC_SSCTL2_IE1 0x00000040 |
| #define ADC_SSCTL2_IE2 0x00000400 |
| #define ADC_SSCTL2_IE3 0x00004000 |
| #define ADC_SSCTL2_TS0 0x00000008 |
| #define ADC_SSCTL2_TS1 0x00000080 |
| #define ADC_SSCTL2_TS2 0x00000800 |
| #define ADC_SSCTL2_TS3 0x00008000 |
| #define ADC_SSCTL3_D0 0x00000001 |
| #define ADC_SSCTL3_END0 0x00000002 |
| #define ADC_SSCTL3_IE0 0x00000004 |
| #define ADC_SSCTL3_TS0 0x00000008 |
| #define ADC_SSDC0_S0DCSEL_M 0x0000000F |
| #define ADC_SSDC0_S0DCSEL_S 0 |
| #define ADC_SSDC0_S1DCSEL_M 0x000000F0 |
| #define ADC_SSDC0_S1DCSEL_S 4 |
| #define ADC_SSDC0_S2DCSEL_M 0x00000F00 |
| #define ADC_SSDC0_S2DCSEL_S 8 |
| #define ADC_SSDC0_S3DCSEL_M 0x0000F000 |
| #define ADC_SSDC0_S3DCSEL_S 12 |
| #define ADC_SSDC0_S4DCSEL_M 0x000F0000 |
| #define ADC_SSDC0_S4DCSEL_S 16 |
| #define ADC_SSDC0_S5DCSEL_M 0x00F00000 |
| #define ADC_SSDC0_S5DCSEL_S 20 |
| #define ADC_SSDC0_S6DCSEL_M 0x0F000000 |
| #define ADC_SSDC0_S6DCSEL_S 24 |
| #define ADC_SSDC0_S7DCSEL_M 0xF0000000 |
| #define ADC_SSDC1_S0DCSEL_M 0x0000000F |
| #define ADC_SSDC1_S0DCSEL_S 0 |
| #define ADC_SSDC1_S1DCSEL_M 0x000000F0 |
| #define ADC_SSDC1_S1DCSEL_S 4 |
| #define ADC_SSDC1_S2DCSEL_M 0x00000F00 |
| #define ADC_SSDC1_S2DCSEL_S 8 |
| #define ADC_SSDC1_S3DCSEL_M 0x0000F000 |
| #define ADC_SSDC2_S0DCSEL_M 0x0000000F |
| #define ADC_SSDC2_S0DCSEL_S 0 |
| #define ADC_SSDC2_S1DCSEL_M 0x000000F0 |
| #define ADC_SSDC2_S1DCSEL_S 4 |
| #define ADC_SSDC2_S2DCSEL_M 0x00000F00 |
| #define ADC_SSDC2_S2DCSEL_S 8 |
| #define ADC_SSDC2_S3DCSEL_M 0x0000F000 |
| #define ADC_SSDC3_S0DCSEL_M 0x0000000F |
| #define ADC_SSEMUX0_EMUX0 0x00000001 |
| #define ADC_SSEMUX0_EMUX1 0x00000010 |
| #define ADC_SSEMUX0_EMUX2 0x00000100 |
| #define ADC_SSEMUX0_EMUX3 0x00001000 |
| #define ADC_SSEMUX0_EMUX4 0x00010000 |
| #define ADC_SSEMUX0_EMUX5 0x00100000 |
| #define ADC_SSEMUX0_EMUX6 0x01000000 |
| #define ADC_SSEMUX0_EMUX7 0x10000000 |
| #define ADC_SSEMUX1_EMUX0 0x00000001 |
| #define ADC_SSEMUX1_EMUX1 0x00000010 |
| #define ADC_SSEMUX1_EMUX2 0x00000100 |
| #define ADC_SSEMUX1_EMUX3 0x00001000 |
| #define ADC_SSEMUX2_EMUX0 0x00000001 |
| #define ADC_SSEMUX2_EMUX1 0x00000010 |
| #define ADC_SSEMUX2_EMUX2 0x00000100 |
| #define ADC_SSEMUX2_EMUX3 0x00001000 |
| #define ADC_SSEMUX3_EMUX0 0x00000001 |
| #define ADC_SSFIFO0_DATA_M 0x00000FFF |
| #define ADC_SSFIFO0_DATA_S 0 |
| #define ADC_SSFIFO1_DATA_M 0x00000FFF |
| #define ADC_SSFIFO1_DATA_S 0 |
| #define ADC_SSFIFO2_DATA_M 0x00000FFF |
| #define ADC_SSFIFO2_DATA_S 0 |
| #define ADC_SSFIFO3_DATA_M 0x00000FFF |
| #define ADC_SSFIFO3_DATA_S 0 |
| #define ADC_SSFSTAT0_EMPTY 0x00000100 |
| #define ADC_SSFSTAT0_FULL 0x00001000 |
| #define ADC_SSFSTAT0_HPTR_M 0x000000F0 |
| #define ADC_SSFSTAT0_HPTR_S 4 |
| #define ADC_SSFSTAT0_TPTR_M 0x0000000F |
| #define ADC_SSFSTAT0_TPTR_S 0 |
| #define ADC_SSFSTAT1_EMPTY 0x00000100 |
| #define ADC_SSFSTAT1_FULL 0x00001000 |
| #define ADC_SSFSTAT1_HPTR_M 0x000000F0 |
| #define ADC_SSFSTAT1_HPTR_S 4 |
| #define ADC_SSFSTAT1_TPTR_M 0x0000000F |
| #define ADC_SSFSTAT1_TPTR_S 0 |
| #define ADC_SSFSTAT2_EMPTY 0x00000100 |
| #define ADC_SSFSTAT2_FULL 0x00001000 |
| #define ADC_SSFSTAT2_HPTR_M 0x000000F0 |
| #define ADC_SSFSTAT2_HPTR_S 4 |
| #define ADC_SSFSTAT2_TPTR_M 0x0000000F |
| #define ADC_SSFSTAT2_TPTR_S 0 |
| #define ADC_SSFSTAT3_EMPTY 0x00000100 |
| #define ADC_SSFSTAT3_FULL 0x00001000 |
| #define ADC_SSFSTAT3_HPTR_M 0x000000F0 |
| #define ADC_SSFSTAT3_HPTR_S 4 |
| #define ADC_SSFSTAT3_TPTR_M 0x0000000F |
| #define ADC_SSFSTAT3_TPTR_S 0 |
| #define ADC_SSMUX0_MUX0_M 0x0000000F |
| #define ADC_SSMUX0_MUX0_S 0 |
| #define ADC_SSMUX0_MUX1_M 0x000000F0 |
| #define ADC_SSMUX0_MUX1_S 4 |
| #define ADC_SSMUX0_MUX2_M 0x00000F00 |
| #define ADC_SSMUX0_MUX2_S 8 |
| #define ADC_SSMUX0_MUX3_M 0x0000F000 |
| #define ADC_SSMUX0_MUX3_S 12 |
| #define ADC_SSMUX0_MUX4_M 0x000F0000 |
| #define ADC_SSMUX0_MUX4_S 16 |
| #define ADC_SSMUX0_MUX5_M 0x00F00000 |
| #define ADC_SSMUX0_MUX5_S 20 |
| #define ADC_SSMUX0_MUX6_M 0x0F000000 |
| #define ADC_SSMUX0_MUX6_S 24 |
| #define ADC_SSMUX0_MUX7_M 0xF0000000 |
| #define ADC_SSMUX0_MUX7_S 28 |
| #define ADC_SSMUX1_MUX0_M 0x0000000F |
| #define ADC_SSMUX1_MUX0_S 0 |
| #define ADC_SSMUX1_MUX1_M 0x000000F0 |
| #define ADC_SSMUX1_MUX1_S 4 |
| #define ADC_SSMUX1_MUX2_M 0x00000F00 |
| #define ADC_SSMUX1_MUX2_S 8 |
| #define ADC_SSMUX1_MUX3_M 0x0000F000 |
| #define ADC_SSMUX1_MUX3_S 12 |
| #define ADC_SSMUX2_MUX0_M 0x0000000F |
| #define ADC_SSMUX2_MUX0_S 0 |
| #define ADC_SSMUX2_MUX1_M 0x000000F0 |
| #define ADC_SSMUX2_MUX1_S 4 |
| #define ADC_SSMUX2_MUX2_M 0x00000F00 |
| #define ADC_SSMUX2_MUX2_S 8 |
| #define ADC_SSMUX2_MUX3_M 0x0000F000 |
| #define ADC_SSMUX2_MUX3_S 12 |
| #define ADC_SSMUX3_MUX0_M 0x0000000F |
| #define ADC_SSMUX3_MUX0_S 0 |
| #define ADC_SSOP0_S0DCOP 0x00000001 |
| #define ADC_SSOP0_S1DCOP 0x00000010 |
| #define ADC_SSOP0_S2DCOP 0x00000100 |
| #define ADC_SSOP0_S3DCOP 0x00001000 |
| #define ADC_SSOP0_S4DCOP 0x00010000 |
| #define ADC_SSOP0_S5DCOP 0x00100000 |
| #define ADC_SSOP0_S6DCOP 0x01000000 |
| #define ADC_SSOP0_S7DCOP 0x10000000 |
| #define ADC_SSOP1_S0DCOP 0x00000001 |
| #define ADC_SSOP1_S1DCOP 0x00000010 |
| #define ADC_SSOP1_S2DCOP 0x00000100 |
| #define ADC_SSOP1_S3DCOP 0x00001000 |
| #define ADC_SSOP2_S0DCOP 0x00000001 |
| #define ADC_SSOP2_S1DCOP 0x00000010 |
| #define ADC_SSOP2_S2DCOP 0x00000100 |
| #define ADC_SSOP2_S3DCOP 0x00001000 |
| #define ADC_SSOP3_S0DCOP 0x00000001 |
| #define ADC_SSPRI_SS0_M 0x00000003 |
| #define ADC_SSPRI_SS1_M 0x00000030 |
| #define ADC_SSPRI_SS2_M 0x00000300 |
| #define ADC_SSPRI_SS3_M 0x00003000 |
| #define ADC_TSSEL_PS0_0 0x00000000 |
| #define ADC_TSSEL_PS0_1 0x00000010 |
| #define ADC_TSSEL_PS0_M 0x00000030 |
| #define ADC_TSSEL_PS1_0 0x00000000 |
| #define ADC_TSSEL_PS1_1 0x00001000 |
| #define ADC_TSSEL_PS1_M 0x00003000 |
| #define ADC_TSSEL_PS2_0 0x00000000 |
| #define ADC_TSSEL_PS2_1 0x00100000 |
| #define ADC_TSSEL_PS2_M 0x00300000 |
| #define ADC_TSSEL_PS3_0 0x00000000 |
| #define ADC_TSSEL_PS3_1 0x10000000 |
| #define ADC_TSSEL_PS3_M 0x30000000 |
| #define ADC_USTAT_UV0 0x00000001 |
| #define ADC_USTAT_UV1 0x00000002 |
| #define ADC_USTAT_UV2 0x00000004 |
| #define ADC_USTAT_UV3 0x00000008 |
| #define CAN0_BIT_R (*((volatile uint32_t *)0x4004000C)) |
| #define CAN0_BRPE_R (*((volatile uint32_t *)0x40040018)) |
| #define CAN0_CTL_R (*((volatile uint32_t *)0x40040000)) |
| #define CAN0_ERR_R (*((volatile uint32_t *)0x40040008)) |
| #define CAN0_IF1ARB1_R (*((volatile uint32_t *)0x40040030)) |
| #define CAN0_IF1ARB2_R (*((volatile uint32_t *)0x40040034)) |
| #define CAN0_IF1CMSK_R (*((volatile uint32_t *)0x40040024)) |
| #define CAN0_IF1CRQ_R (*((volatile uint32_t *)0x40040020)) |
| #define CAN0_IF1DA1_R (*((volatile uint32_t *)0x4004003C)) |
| #define CAN0_IF1DA2_R (*((volatile uint32_t *)0x40040040)) |
| #define CAN0_IF1DB1_R (*((volatile uint32_t *)0x40040044)) |
| #define CAN0_IF1DB2_R (*((volatile uint32_t *)0x40040048)) |
| #define CAN0_IF1MCTL_R (*((volatile uint32_t *)0x40040038)) |
| #define CAN0_IF1MSK1_R (*((volatile uint32_t *)0x40040028)) |
| #define CAN0_IF1MSK2_R (*((volatile uint32_t *)0x4004002C)) |
| #define CAN0_IF2ARB1_R (*((volatile uint32_t *)0x40040090)) |
| #define CAN0_IF2ARB2_R (*((volatile uint32_t *)0x40040094)) |
| #define CAN0_IF2CMSK_R (*((volatile uint32_t *)0x40040084)) |
| #define CAN0_IF2CRQ_R (*((volatile uint32_t *)0x40040080)) |
| #define CAN0_IF2DA1_R (*((volatile uint32_t *)0x4004009C)) |
| #define CAN0_IF2DA2_R (*((volatile uint32_t *)0x400400A0)) |
| #define CAN0_IF2DB1_R (*((volatile uint32_t *)0x400400A4)) |
| #define CAN0_IF2DB2_R (*((volatile uint32_t *)0x400400A8)) |
| #define CAN0_IF2MCTL_R (*((volatile uint32_t *)0x40040098)) |
| #define CAN0_IF2MSK1_R (*((volatile uint32_t *)0x40040088)) |
| #define CAN0_IF2MSK2_R (*((volatile uint32_t *)0x4004008C)) |
| #define CAN0_INT_R (*((volatile uint32_t *)0x40040010)) |
| #define CAN0_MSG1INT_R (*((volatile uint32_t *)0x40040140)) |
| #define CAN0_MSG1VAL_R (*((volatile uint32_t *)0x40040160)) |
| #define CAN0_MSG2INT_R (*((volatile uint32_t *)0x40040144)) |
| #define CAN0_MSG2VAL_R (*((volatile uint32_t *)0x40040164)) |
| #define CAN0_NWDA1_R (*((volatile uint32_t *)0x40040120)) |
| #define CAN0_NWDA2_R (*((volatile uint32_t *)0x40040124)) |
| #define CAN0_STS_R (*((volatile uint32_t *)0x40040004)) |
| #define CAN0_TST_R (*((volatile uint32_t *)0x40040014)) |
| #define CAN0_TXRQ1_R (*((volatile uint32_t *)0x40040100)) |
| #define CAN0_TXRQ2_R (*((volatile uint32_t *)0x40040104)) |
| #define CAN1_BIT_R (*((volatile uint32_t *)0x4004100C)) |
| #define CAN1_BRPE_R (*((volatile uint32_t *)0x40041018)) |
| #define CAN1_CTL_R (*((volatile uint32_t *)0x40041000)) |
| #define CAN1_ERR_R (*((volatile uint32_t *)0x40041008)) |
| #define CAN1_IF1ARB1_R (*((volatile uint32_t *)0x40041030)) |
| #define CAN1_IF1ARB2_R (*((volatile uint32_t *)0x40041034)) |
| #define CAN1_IF1CMSK_R (*((volatile uint32_t *)0x40041024)) |
| #define CAN1_IF1CRQ_R (*((volatile uint32_t *)0x40041020)) |
| #define CAN1_IF1DA1_R (*((volatile uint32_t *)0x4004103C)) |
| #define CAN1_IF1DA2_R (*((volatile uint32_t *)0x40041040)) |
| #define CAN1_IF1DB1_R (*((volatile uint32_t *)0x40041044)) |
| #define CAN1_IF1DB2_R (*((volatile uint32_t *)0x40041048)) |
| #define CAN1_IF1MCTL_R (*((volatile uint32_t *)0x40041038)) |
| #define CAN1_IF1MSK1_R (*((volatile uint32_t *)0x40041028)) |
| #define CAN1_IF1MSK2_R (*((volatile uint32_t *)0x4004102C)) |
| #define CAN1_IF2ARB1_R (*((volatile uint32_t *)0x40041090)) |
| #define CAN1_IF2ARB2_R (*((volatile uint32_t *)0x40041094)) |
| #define CAN1_IF2CMSK_R (*((volatile uint32_t *)0x40041084)) |
| #define CAN1_IF2CRQ_R (*((volatile uint32_t *)0x40041080)) |
| #define CAN1_IF2DA1_R (*((volatile uint32_t *)0x4004109C)) |
| #define CAN1_IF2DA2_R (*((volatile uint32_t *)0x400410A0)) |
| #define CAN1_IF2DB1_R (*((volatile uint32_t *)0x400410A4)) |
| #define CAN1_IF2DB2_R (*((volatile uint32_t *)0x400410A8)) |
| #define CAN1_IF2MCTL_R (*((volatile uint32_t *)0x40041098)) |
| #define CAN1_IF2MSK1_R (*((volatile uint32_t *)0x40041088)) |
| #define CAN1_IF2MSK2_R (*((volatile uint32_t *)0x4004108C)) |
| #define CAN1_INT_R (*((volatile uint32_t *)0x40041010)) |
| #define CAN1_MSG1INT_R (*((volatile uint32_t *)0x40041140)) |
| #define CAN1_MSG1VAL_R (*((volatile uint32_t *)0x40041160)) |
| #define CAN1_MSG2INT_R (*((volatile uint32_t *)0x40041144)) |
| #define CAN1_MSG2VAL_R (*((volatile uint32_t *)0x40041164)) |
| #define CAN1_NWDA1_R (*((volatile uint32_t *)0x40041120)) |
| #define CAN1_NWDA2_R (*((volatile uint32_t *)0x40041124)) |
| #define CAN1_STS_R (*((volatile uint32_t *)0x40041004)) |
| #define CAN1_TST_R (*((volatile uint32_t *)0x40041014)) |
| #define CAN1_TXRQ1_R (*((volatile uint32_t *)0x40041100)) |
| #define CAN1_TXRQ2_R (*((volatile uint32_t *)0x40041104)) |
| #define CAN_BIT_BRP_M 0x0000003F |
| #define CAN_BIT_BRP_S 0 |
| #define CAN_BIT_SJW_M 0x000000C0 |
| #define CAN_BIT_SJW_S 6 |
| #define CAN_BIT_TSEG1_M 0x00000F00 |
| #define CAN_BIT_TSEG1_S 8 |
| #define CAN_BIT_TSEG2_M 0x00007000 |
| #define CAN_BIT_TSEG2_S 12 |
| #define CAN_BRPE_BRPE_M 0x0000000F |
| #define CAN_BRPE_BRPE_S 0 |
| #define CAN_CTL_CCE 0x00000040 |
| #define CAN_CTL_DAR 0x00000020 |
| #define CAN_CTL_EIE 0x00000008 |
| #define CAN_CTL_IE 0x00000002 |
| #define CAN_CTL_INIT 0x00000001 |
| #define CAN_CTL_SIE 0x00000004 |
| #define CAN_CTL_TEST 0x00000080 |
| #define CAN_ERR_REC_M 0x00007F00 |
| #define CAN_ERR_REC_S 8 |
| #define CAN_ERR_RP 0x00008000 |
| #define CAN_ERR_TEC_M 0x000000FF |
| #define CAN_ERR_TEC_S 0 |
| #define CAN_IF1ARB1_ID_M 0x0000FFFF |
| #define CAN_IF1ARB1_ID_S 0 |
| #define CAN_IF1ARB2_DIR 0x00002000 |
| #define CAN_IF1ARB2_ID_M 0x00001FFF |
| #define CAN_IF1ARB2_ID_S 0 |
| #define CAN_IF1ARB2_MSGVAL 0x00008000 |
| #define CAN_IF1ARB2_XTD 0x00004000 |
| #define CAN_IF1CMSK_ARB 0x00000020 |
| #define CAN_IF1CMSK_CLRINTPND 0x00000008 |
| #define CAN_IF1CMSK_CONTROL 0x00000010 |
| #define CAN_IF1CMSK_DATAA 0x00000002 |
| #define CAN_IF1CMSK_DATAB 0x00000001 |
| #define CAN_IF1CMSK_MASK 0x00000040 |
| #define CAN_IF1CMSK_NEWDAT 0x00000004 |
| #define CAN_IF1CMSK_TXRQST 0x00000004 |
| #define CAN_IF1CMSK_WRNRD 0x00000080 |
| #define CAN_IF1CRQ_BUSY 0x00008000 |
| #define CAN_IF1CRQ_MNUM_M 0x0000003F |
| #define CAN_IF1CRQ_MNUM_S 0 |
| #define CAN_IF1DA1_DATA_M 0x0000FFFF |
| #define CAN_IF1DA1_DATA_S 0 |
| #define CAN_IF1DA2_DATA_M 0x0000FFFF |
| #define CAN_IF1DA2_DATA_S 0 |
| #define CAN_IF1DB1_DATA_M 0x0000FFFF |
| #define CAN_IF1DB1_DATA_S 0 |
| #define CAN_IF1DB2_DATA_M 0x0000FFFF |
| #define CAN_IF1DB2_DATA_S 0 |
| #define CAN_IF1MCTL_DLC_M 0x0000000F |
| #define CAN_IF1MCTL_DLC_S 0 |
| #define CAN_IF1MCTL_EOB 0x00000080 |
| #define CAN_IF1MCTL_INTPND 0x00002000 |
| #define CAN_IF1MCTL_MSGLST 0x00004000 |
| #define CAN_IF1MCTL_NEWDAT 0x00008000 |
| #define CAN_IF1MCTL_RMTEN 0x00000200 |
| #define CAN_IF1MCTL_RXIE 0x00000400 |
| #define CAN_IF1MCTL_TXIE 0x00000800 |
| #define CAN_IF1MCTL_TXRQST 0x00000100 |
| #define CAN_IF1MCTL_UMASK 0x00001000 |
| #define CAN_IF1MSK1_IDMSK_M 0x0000FFFF |
| #define CAN_IF1MSK1_IDMSK_S 0 |
| #define CAN_IF1MSK2_IDMSK_M 0x00001FFF |
| #define CAN_IF1MSK2_IDMSK_S 0 |
| #define CAN_IF1MSK2_MDIR 0x00004000 |
| #define CAN_IF1MSK2_MXTD 0x00008000 |
| #define CAN_IF2ARB1_ID_M 0x0000FFFF |
| #define CAN_IF2ARB1_ID_S 0 |
| #define CAN_IF2ARB2_DIR 0x00002000 |
| #define CAN_IF2ARB2_ID_M 0x00001FFF |
| #define CAN_IF2ARB2_ID_S 0 |
| #define CAN_IF2ARB2_MSGVAL 0x00008000 |
| #define CAN_IF2ARB2_XTD 0x00004000 |
| #define CAN_IF2CMSK_ARB 0x00000020 |
| #define CAN_IF2CMSK_CLRINTPND 0x00000008 |
| #define CAN_IF2CMSK_CONTROL 0x00000010 |
| #define CAN_IF2CMSK_DATAA 0x00000002 |
| #define CAN_IF2CMSK_DATAB 0x00000001 |
| #define CAN_IF2CMSK_MASK 0x00000040 |
| #define CAN_IF2CMSK_NEWDAT 0x00000004 |
| #define CAN_IF2CMSK_TXRQST 0x00000004 |
| #define CAN_IF2CMSK_WRNRD 0x00000080 |
| #define CAN_IF2CRQ_BUSY 0x00008000 |
| #define CAN_IF2CRQ_MNUM_M 0x0000003F |
| #define CAN_IF2CRQ_MNUM_S 0 |
| #define CAN_IF2DA1_DATA_M 0x0000FFFF |
| #define CAN_IF2DA1_DATA_S 0 |
| #define CAN_IF2DA2_DATA_M 0x0000FFFF |
| #define CAN_IF2DA2_DATA_S 0 |
| #define CAN_IF2DB1_DATA_M 0x0000FFFF |
| #define CAN_IF2DB1_DATA_S 0 |
| #define CAN_IF2DB2_DATA_M 0x0000FFFF |
| #define CAN_IF2DB2_DATA_S 0 |
| #define CAN_IF2MCTL_DLC_M 0x0000000F |
| #define CAN_IF2MCTL_DLC_S 0 |
| #define CAN_IF2MCTL_EOB 0x00000080 |
| #define CAN_IF2MCTL_INTPND 0x00002000 |
| #define CAN_IF2MCTL_MSGLST 0x00004000 |
| #define CAN_IF2MCTL_NEWDAT 0x00008000 |
| #define CAN_IF2MCTL_RMTEN 0x00000200 |
| #define CAN_IF2MCTL_RXIE 0x00000400 |
| #define CAN_IF2MCTL_TXIE 0x00000800 |
| #define CAN_IF2MCTL_TXRQST 0x00000100 |
| #define CAN_IF2MCTL_UMASK 0x00001000 |
| #define CAN_IF2MSK1_IDMSK_M 0x0000FFFF |
| #define CAN_IF2MSK1_IDMSK_S 0 |
| #define CAN_IF2MSK2_IDMSK_M 0x00001FFF |
| #define CAN_IF2MSK2_IDMSK_S 0 |
| #define CAN_IF2MSK2_MDIR 0x00004000 |
| #define CAN_IF2MSK2_MXTD 0x00008000 |
| #define CAN_INT_INTID_M 0x0000FFFF |
| #define CAN_INT_INTID_NONE 0x00000000 |
| #define CAN_INT_INTID_STATUS 0x00008000 |
| #define CAN_MSG1INT_INTPND_M 0x0000FFFF |
| #define CAN_MSG1INT_INTPND_S 0 |
| #define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF |
| #define CAN_MSG1VAL_MSGVAL_S 0 |
| #define CAN_MSG2INT_INTPND_M 0x0000FFFF |
| #define CAN_MSG2INT_INTPND_S 0 |
| #define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF |
| #define CAN_MSG2VAL_MSGVAL_S 0 |
| #define CAN_NWDA1_NEWDAT_M 0x0000FFFF |
| #define CAN_NWDA1_NEWDAT_S 0 |
| #define CAN_NWDA2_NEWDAT_M 0x0000FFFF |
| #define CAN_NWDA2_NEWDAT_S 0 |
| #define CAN_STS_BOFF 0x00000080 |
| #define CAN_STS_EPASS 0x00000020 |
| #define CAN_STS_EWARN 0x00000040 |
| #define CAN_STS_LEC_ACK 0x00000003 |
| #define CAN_STS_LEC_BIT0 0x00000005 |
| #define CAN_STS_LEC_BIT1 0x00000004 |
| #define CAN_STS_LEC_CRC 0x00000006 |
| #define CAN_STS_LEC_FORM 0x00000002 |
| #define CAN_STS_LEC_M 0x00000007 |
| #define CAN_STS_LEC_NOEVENT 0x00000007 |
| #define CAN_STS_LEC_NONE 0x00000000 |
| #define CAN_STS_LEC_STUFF 0x00000001 |
| #define CAN_STS_RXOK 0x00000010 |
| #define CAN_STS_TXOK 0x00000008 |
| #define CAN_TST_BASIC 0x00000004 |
| #define CAN_TST_LBACK 0x00000010 |
| #define CAN_TST_RX 0x00000080 |
| #define CAN_TST_SILENT 0x00000008 |
| #define CAN_TST_TX_CANCTL 0x00000000 |
| #define CAN_TST_TX_DOMINANT 0x00000040 |
| #define CAN_TST_TX_M 0x00000060 |
| #define CAN_TST_TX_RECESSIVE 0x00000060 |
| #define CAN_TST_TX_SAMPLE 0x00000020 |
| #define CAN_TXRQ1_TXRQST_M 0x0000FFFF |
| #define CAN_TXRQ1_TXRQST_S 0 |
| #define CAN_TXRQ2_TXRQST_M 0x0000FFFF |
| #define CAN_TXRQ2_TXRQST_S 0 |
| #define COMP_ACCTL0_ASRCP_M 0x00000600 |
| #define COMP_ACCTL0_ASRCP_PIN 0x00000000 |
| #define COMP_ACCTL0_ASRCP_PIN0 0x00000200 |
| #define COMP_ACCTL0_ASRCP_REF 0x00000400 |
| #define COMP_ACCTL0_CINV 0x00000002 |
| #define COMP_ACCTL0_ISEN_BOTH 0x0000000C |
| #define COMP_ACCTL0_ISEN_FALL 0x00000004 |
| #define COMP_ACCTL0_ISEN_LEVEL 0x00000000 |
| #define COMP_ACCTL0_ISEN_M 0x0000000C |
| #define COMP_ACCTL0_ISEN_RISE 0x00000008 |
| #define COMP_ACCTL0_ISLVAL 0x00000010 |
| #define COMP_ACCTL0_R (*((volatile uint32_t *)0x4003C024)) |
| #define COMP_ACCTL0_TOEN 0x00000800 |
| #define COMP_ACCTL0_TSEN_BOTH 0x00000060 |
| #define COMP_ACCTL0_TSEN_FALL 0x00000020 |
| #define COMP_ACCTL0_TSEN_LEVEL 0x00000000 |
| #define COMP_ACCTL0_TSEN_M 0x00000060 |
| #define COMP_ACCTL0_TSEN_RISE 0x00000040 |
| #define COMP_ACCTL0_TSLVAL 0x00000080 |
| #define COMP_ACCTL1_ASRCP_M 0x00000600 |
| #define COMP_ACCTL1_ASRCP_PIN 0x00000000 |
| #define COMP_ACCTL1_ASRCP_PIN0 0x00000200 |
| #define COMP_ACCTL1_ASRCP_REF 0x00000400 |
| #define COMP_ACCTL1_CINV 0x00000002 |
| #define COMP_ACCTL1_ISEN_BOTH 0x0000000C |
| #define COMP_ACCTL1_ISEN_FALL 0x00000004 |
| #define COMP_ACCTL1_ISEN_LEVEL 0x00000000 |
| #define COMP_ACCTL1_ISEN_M 0x0000000C |
| #define COMP_ACCTL1_ISEN_RISE 0x00000008 |
| #define COMP_ACCTL1_ISLVAL 0x00000010 |
| #define COMP_ACCTL1_R (*((volatile uint32_t *)0x4003C044)) |
| #define COMP_ACCTL1_TOEN 0x00000800 |
| #define COMP_ACCTL1_TSEN_BOTH 0x00000060 |
| #define COMP_ACCTL1_TSEN_FALL 0x00000020 |
| #define COMP_ACCTL1_TSEN_LEVEL 0x00000000 |
| #define COMP_ACCTL1_TSEN_M 0x00000060 |
| #define COMP_ACCTL1_TSEN_RISE 0x00000040 |
| #define COMP_ACCTL1_TSLVAL 0x00000080 |
| #define COMP_ACCTL2_ASRCP_M 0x00000600 |
| #define COMP_ACCTL2_ASRCP_PIN 0x00000000 |
| #define COMP_ACCTL2_ASRCP_PIN0 0x00000200 |
| #define COMP_ACCTL2_ASRCP_REF 0x00000400 |
| #define COMP_ACCTL2_CINV 0x00000002 |
| #define COMP_ACCTL2_ISEN_BOTH 0x0000000C |
| #define COMP_ACCTL2_ISEN_FALL 0x00000004 |
| #define COMP_ACCTL2_ISEN_LEVEL 0x00000000 |
| #define COMP_ACCTL2_ISEN_M 0x0000000C |
| #define COMP_ACCTL2_ISEN_RISE 0x00000008 |
| #define COMP_ACCTL2_ISLVAL 0x00000010 |
| #define COMP_ACCTL2_R (*((volatile uint32_t *)0x4003C064)) |
| #define COMP_ACCTL2_TOEN 0x00000800 |
| #define COMP_ACCTL2_TSEN_BOTH 0x00000060 |
| #define COMP_ACCTL2_TSEN_FALL 0x00000020 |
| #define COMP_ACCTL2_TSEN_LEVEL 0x00000000 |
| #define COMP_ACCTL2_TSEN_M 0x00000060 |
| #define COMP_ACCTL2_TSEN_RISE 0x00000040 |
| #define COMP_ACCTL2_TSLVAL 0x00000080 |
| #define COMP_ACINTEN_IN0 0x00000001 |
| #define COMP_ACINTEN_IN1 0x00000002 |
| #define COMP_ACINTEN_IN2 0x00000004 |
| #define COMP_ACINTEN_R (*((volatile uint32_t *)0x4003C008)) |
| #define COMP_ACMIS_IN0 0x00000001 |
| #define COMP_ACMIS_IN1 0x00000002 |
| #define COMP_ACMIS_IN2 0x00000004 |
| #define COMP_ACMIS_R (*((volatile uint32_t *)0x4003C000)) |
| #define COMP_ACREFCTL_EN 0x00000200 |
| #define COMP_ACREFCTL_R (*((volatile uint32_t *)0x4003C010)) |
| #define COMP_ACREFCTL_RNG 0x00000100 |
| #define COMP_ACREFCTL_VREF_M 0x0000000F |
| #define COMP_ACREFCTL_VREF_S 0 |
| #define COMP_ACRIS_IN0 0x00000001 |
| #define COMP_ACRIS_IN1 0x00000002 |
| #define COMP_ACRIS_IN2 0x00000004 |
| #define COMP_ACRIS_R (*((volatile uint32_t *)0x4003C004)) |
| #define COMP_ACSTAT0_OVAL 0x00000002 |
| #define COMP_ACSTAT0_R (*((volatile uint32_t *)0x4003C020)) |
| #define COMP_ACSTAT1_OVAL 0x00000002 |
| #define COMP_ACSTAT1_R (*((volatile uint32_t *)0x4003C040)) |
| #define COMP_ACSTAT2_OVAL 0x00000002 |
| #define COMP_ACSTAT2_R (*((volatile uint32_t *)0x4003C060)) |
| #define COMP_PP_C0O 0x00010000 |
| #define COMP_PP_C1O 0x00020000 |
| #define COMP_PP_C2O 0x00040000 |
| #define COMP_PP_CMP0 0x00000001 |
| #define COMP_PP_CMP1 0x00000002 |
| #define COMP_PP_CMP2 0x00000004 |
| #define COMP_PP_R (*((volatile uint32_t *)0x4003CFC0)) |
| #define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF |
| #define EEPROM_EEBLOCK_BLOCK_S 0 |
| #define EEPROM_EEBLOCK_R (*((volatile uint32_t *)0x400AF004)) |
| #define EEPROM_EEDBGME_KEY_M 0xFFFF0000 |
| #define EEPROM_EEDBGME_KEY_S 16 |
| #define EEPROM_EEDBGME_ME 0x00000001 |
| #define EEPROM_EEDBGME_R (*((volatile uint32_t *)0x400AF080)) |
| #define EEPROM_EEDONE_NOPERM 0x00000010 |
| #define EEPROM_EEDONE_R (*((volatile uint32_t *)0x400AF018)) |
| #define EEPROM_EEDONE_WKCOPY 0x00000008 |
| #define EEPROM_EEDONE_WKERASE 0x00000004 |
| #define EEPROM_EEDONE_WORKING 0x00000001 |
| #define EEPROM_EEDONE_WRBUSY 0x00000020 |
| #define EEPROM_EEHIDE_HN_M 0xFFFFFFFE |
| #define EEPROM_EEHIDE_R (*((volatile uint32_t *)0x400AF050)) |
| #define EEPROM_EEINT_INT 0x00000001 |
| #define EEPROM_EEINT_R (*((volatile uint32_t *)0x400AF040)) |
| #define EEPROM_EEOFFSET_OFFSET_M 0x0000000F |
| #define EEPROM_EEOFFSET_OFFSET_S 0 |
| #define EEPROM_EEOFFSET_R (*((volatile uint32_t *)0x400AF008)) |
| #define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF |
| #define EEPROM_EEPASS0_PASS_S 0 |
| #define EEPROM_EEPASS0_R (*((volatile uint32_t *)0x400AF034)) |
| #define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF |
| #define EEPROM_EEPASS1_PASS_S 0 |
| #define EEPROM_EEPASS1_R (*((volatile uint32_t *)0x400AF038)) |
| #define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF |
| #define EEPROM_EEPASS2_PASS_S 0 |
| #define EEPROM_EEPASS2_R (*((volatile uint32_t *)0x400AF03C)) |
| #define EEPROM_EEPROT_ACC 0x00000008 |
| #define EEPROM_EEPROT_PROT_M 0x00000007 |
| #define EEPROM_EEPROT_PROT_RONPW 0x00000002 |
| #define EEPROM_EEPROT_PROT_RWNPW 0x00000000 |
| #define EEPROM_EEPROT_PROT_RWPW 0x00000001 |
| #define EEPROM_EEPROT_R (*((volatile uint32_t *)0x400AF030)) |
| #define EEPROM_EERDWR_R (*((volatile uint32_t *)0x400AF010)) |
| #define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF |
| #define EEPROM_EERDWR_VALUE_S 0 |
| #define EEPROM_EERDWRINC_R (*((volatile uint32_t *)0x400AF014)) |
| #define EEPROM_EERDWRINC_VALUE_M 0xFFFFFFFF |
| #define EEPROM_EERDWRINC_VALUE_S 0 |
| #define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 |
| #define EEPROM_EESIZE_BLKCNT_S 16 |
| #define EEPROM_EESIZE_R (*((volatile uint32_t *)0x400AF000)) |
| #define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF |
| #define EEPROM_EESIZE_WORDCNT_S 0 |
| #define EEPROM_EESUPP_ERETRY 0x00000004 |
| #define EEPROM_EESUPP_PRETRY 0x00000008 |
| #define EEPROM_EESUPP_R (*((volatile uint32_t *)0x400AF01C)) |
| #define EEPROM_EEUNLOCK_R (*((volatile uint32_t *)0x400AF020)) |
| #define EEPROM_EEUNLOCK_UNLOCK_M 0xFFFFFFFF |
| #define EEPROM_PP_R (*((volatile uint32_t *)0x400AFFC0)) |
| #define EEPROM_PP_SIZE_M 0x0000001F |
| #define EEPROM_PP_SIZE_S 0 |
| #define FLASH_BOOTCFG_DBG0 0x00000001 |
| #define FLASH_BOOTCFG_DBG1 0x00000002 |
| #define FLASH_BOOTCFG_EN 0x00000100 |
| #define FLASH_BOOTCFG_KEY 0x00000010 |
| #define FLASH_BOOTCFG_NW 0x80000000 |
| #define FLASH_BOOTCFG_PIN_0 0x00000000 |
| #define FLASH_BOOTCFG_PIN_1 0x00000400 |
| #define FLASH_BOOTCFG_PIN_2 0x00000800 |
| #define FLASH_BOOTCFG_PIN_3 0x00000C00 |
| #define FLASH_BOOTCFG_PIN_4 0x00001000 |
| #define FLASH_BOOTCFG_PIN_5 0x00001400 |
| #define FLASH_BOOTCFG_PIN_6 0x00001800 |
| #define FLASH_BOOTCFG_PIN_7 0x00001C00 |
| #define FLASH_BOOTCFG_PIN_M 0x00001C00 |
| #define FLASH_BOOTCFG_POL 0x00000200 |
| #define FLASH_BOOTCFG_PORT_A 0x00000000 |
| #define FLASH_BOOTCFG_PORT_B 0x00002000 |
| #define FLASH_BOOTCFG_PORT_C 0x00004000 |
| #define FLASH_BOOTCFG_PORT_D 0x00006000 |
| #define FLASH_BOOTCFG_PORT_E 0x00008000 |
| #define FLASH_BOOTCFG_PORT_F 0x0000A000 |
| #define FLASH_BOOTCFG_PORT_G 0x0000C000 |
| #define FLASH_BOOTCFG_PORT_H 0x0000E000 |
| #define FLASH_BOOTCFG_PORT_M 0x0000E000 |
| #define FLASH_BOOTCFG_R (*((volatile uint32_t *)0x400FE1D0)) |
| #define FLASH_FCIM_AMASK 0x00000001 |
| #define FLASH_FCIM_EMASK 0x00000004 |
| #define FLASH_FCIM_ERMASK 0x00000800 |
| #define FLASH_FCIM_INVDMASK 0x00000400 |
| #define FLASH_FCIM_PMASK 0x00000002 |
| #define FLASH_FCIM_PROGMASK 0x00002000 |
| #define FLASH_FCIM_R (*((volatile uint32_t *)0x400FD010)) |
| #define FLASH_FCIM_VOLTMASK 0x00000200 |
| #define FLASH_FCMISC_AMISC 0x00000001 |
| #define FLASH_FCMISC_EMISC 0x00000004 |
| #define FLASH_FCMISC_ERMISC 0x00000800 |
| #define FLASH_FCMISC_INVDMISC 0x00000400 |
| #define FLASH_FCMISC_PMISC 0x00000002 |
| #define FLASH_FCMISC_PROGMISC 0x00002000 |
| #define FLASH_FCMISC_R (*((volatile uint32_t *)0x400FD014)) |
| #define FLASH_FCMISC_VOLTMISC 0x00000200 |
| #define FLASH_FCRIS_ARIS 0x00000001 |
| #define FLASH_FCRIS_ERIS 0x00000004 |
| #define FLASH_FCRIS_ERRIS 0x00000800 |
| #define FLASH_FCRIS_INVDRIS 0x00000400 |
| #define FLASH_FCRIS_PRIS 0x00000002 |
| #define FLASH_FCRIS_PROGRIS 0x00002000 |
| #define FLASH_FCRIS_R (*((volatile uint32_t *)0x400FD00C)) |
| #define FLASH_FCRIS_VOLTRIS 0x00000200 |
| #define FLASH_FMA_OFFSET_M 0x0003FFFF |
| #define FLASH_FMA_OFFSET_S 0 |
| #define FLASH_FMA_R (*((volatile uint32_t *)0x400FD000)) |
| #define FLASH_FMC2_R (*((volatile uint32_t *)0x400FD020)) |
| #define FLASH_FMC2_WRBUF 0x00000001 |
| #define FLASH_FMC_COMT 0x00000008 |
| #define FLASH_FMC_ERASE 0x00000002 |
| #define FLASH_FMC_MERASE 0x00000004 |
| #define FLASH_FMC_R (*((volatile uint32_t *)0x400FD008)) |
| #define FLASH_FMC_WRITE 0x00000001 |
| #define FLASH_FMC_WRKEY 0xA4420000 |
| #define FLASH_FMD_DATA_M 0xFFFFFFFF |
| #define FLASH_FMD_DATA_S 0 |
| #define FLASH_FMD_R (*((volatile uint32_t *)0x400FD004)) |
| #define FLASH_FMPPE0_R (*((volatile uint32_t *)0x400FE400)) |
| #define FLASH_FMPPE1_R (*((volatile uint32_t *)0x400FE404)) |
| #define FLASH_FMPPE2_R (*((volatile uint32_t *)0x400FE408)) |
| #define FLASH_FMPPE3_R (*((volatile uint32_t *)0x400FE40C)) |
| #define FLASH_FMPRE0_R (*((volatile uint32_t *)0x400FE200)) |
| #define FLASH_FMPRE1_R (*((volatile uint32_t *)0x400FE204)) |
| #define FLASH_FMPRE2_R (*((volatile uint32_t *)0x400FE208)) |
| #define FLASH_FMPRE3_R (*((volatile uint32_t *)0x400FE20C)) |
| #define FLASH_FSIZE_R (*((volatile uint32_t *)0x400FDFC0)) |
| #define FLASH_FSIZE_SIZE_256KB 0x0000007F |
| #define FLASH_FSIZE_SIZE_M 0x0000FFFF |
| #define FLASH_FWBN_DATA_M 0xFFFFFFFF |
| #define FLASH_FWBN_R (*((volatile uint32_t *)0x400FD100)) |
| #define FLASH_FWBVAL_FWB_M 0xFFFFFFFF |
| #define FLASH_FWBVAL_R (*((volatile uint32_t *)0x400FD030)) |
| #define FLASH_RMCTL_BA 0x00000001 |
| #define FLASH_RMCTL_R (*((volatile uint32_t *)0x400FE0F0)) |
| #define FLASH_ROMSWMAP_R (*((volatile uint32_t *)0x400FDFCC)) |
| #define FLASH_ROMSWMAP_SAFERTOS 0x00000001 |
| #define FLASH_SSIZE_R (*((volatile uint32_t *)0x400FDFC4)) |
| #define FLASH_SSIZE_SIZE_32KB 0x0000007F |
| #define FLASH_SSIZE_SIZE_M 0x0000FFFF |
| #define FLASH_USERREG0_DATA_M 0xFFFFFFFF |
| #define FLASH_USERREG0_DATA_S 0 |
| #define FLASH_USERREG0_R (*((volatile uint32_t *)0x400FE1E0)) |
| #define FLASH_USERREG1_DATA_M 0xFFFFFFFF |
| #define FLASH_USERREG1_DATA_S 0 |
| #define FLASH_USERREG1_R (*((volatile uint32_t *)0x400FE1E4)) |
| #define FLASH_USERREG2_DATA_M 0xFFFFFFFF |
| #define FLASH_USERREG2_DATA_S 0 |
| #define FLASH_USERREG2_R (*((volatile uint32_t *)0x400FE1E8)) |
| #define FLASH_USERREG3_DATA_M 0xFFFFFFFF |
| #define FLASH_USERREG3_DATA_S 0 |
| #define FLASH_USERREG3_R (*((volatile uint32_t *)0x400FE1EC)) |
| #define GPIO_ICR_GPIO_M 0x000000FF |
| #define GPIO_ICR_GPIO_S 0 |
| #define GPIO_IM_GPIO_M 0x000000FF |
| #define GPIO_IM_GPIO_S 0 |
| #define GPIO_LOCK_KEY 0x4C4F434B |
| #define GPIO_LOCK_LOCKED 0x00000001 |
| #define GPIO_LOCK_M 0xFFFFFFFF |
| #define GPIO_LOCK_UNLOCKED 0x00000000 |
| #define GPIO_MIS_GPIO_M 0x000000FF |
| #define GPIO_MIS_GPIO_S 0 |
| #define GPIO_PCTL_PA0_CAN1RX 0x00000008 |
| #define GPIO_PCTL_PA0_M 0x0000000F |
| #define GPIO_PCTL_PA0_U0RX 0x00000001 |
| #define GPIO_PCTL_PA1_CAN1TX 0x00000080 |
| #define GPIO_PCTL_PA1_M 0x000000F0 |
| #define GPIO_PCTL_PA1_U0TX 0x00000010 |
| #define GPIO_PCTL_PA2_M 0x00000F00 |
| #define GPIO_PCTL_PA2_SSI0CLK 0x00000200 |
| #define GPIO_PCTL_PA3_M 0x0000F000 |
| #define GPIO_PCTL_PA3_SSI0FSS 0x00002000 |
| #define GPIO_PCTL_PA4_M 0x000F0000 |
| #define GPIO_PCTL_PA4_SSI0RX 0x00020000 |
| #define GPIO_PCTL_PA5_M 0x00F00000 |
| #define GPIO_PCTL_PA5_SSI0TX 0x00200000 |
| #define GPIO_PCTL_PA6_I2C1SCL 0x03000000 |
| #define GPIO_PCTL_PA6_M 0x0F000000 |
| #define GPIO_PCTL_PA6_M1PWM2 0x05000000 |
| #define GPIO_PCTL_PA7_I2C1SDA 0x30000000 |
| #define GPIO_PCTL_PA7_M 0xF0000000 |
| #define GPIO_PCTL_PA7_M1PWM3 0x50000000 |
| #define GPIO_PCTL_PB0_M 0x0000000F |
| #define GPIO_PCTL_PB0_T2CCP0 0x00000007 |
| #define GPIO_PCTL_PB0_U1RX 0x00000001 |
| #define GPIO_PCTL_PB0_USB0ID 0x00000000 |
| #define GPIO_PCTL_PB1_M 0x000000F0 |
| #define GPIO_PCTL_PB1_T2CCP1 0x00000070 |
| #define GPIO_PCTL_PB1_U1TX 0x00000010 |
| #define GPIO_PCTL_PB1_USB0VBUS 0x00000000 |
| #define GPIO_PCTL_PB2_I2C0SCL 0x00000300 |
| #define GPIO_PCTL_PB2_M 0x00000F00 |
| #define GPIO_PCTL_PB2_T3CCP0 0x00000700 |
| #define GPIO_PCTL_PB3_I2C0SDA 0x00003000 |
| #define GPIO_PCTL_PB3_M 0x0000F000 |
| #define GPIO_PCTL_PB3_T3CCP1 0x00007000 |
| #define GPIO_PCTL_PB4_CAN0RX 0x00080000 |
| #define GPIO_PCTL_PB4_M 0x000F0000 |
| #define GPIO_PCTL_PB4_M0PWM2 0x00040000 |
| #define GPIO_PCTL_PB4_SSI2CLK 0x00020000 |
| #define GPIO_PCTL_PB4_T1CCP0 0x00070000 |
| #define GPIO_PCTL_PB5_CAN0TX 0x00800000 |
| #define GPIO_PCTL_PB5_M 0x00F00000 |
| #define GPIO_PCTL_PB5_M0PWM3 0x00400000 |
| #define GPIO_PCTL_PB5_SSI2FSS 0x00200000 |
| #define GPIO_PCTL_PB5_T1CCP1 0x00700000 |
| #define GPIO_PCTL_PC0_M 0x0000000F |
| #define GPIO_PCTL_PC0_T4CCP0 0x00000007 |
| #define GPIO_PCTL_PC0_TCK 0x00000001 |
| #define GPIO_PCTL_PC1_M 0x000000F0 |
| #define GPIO_PCTL_PC1_T4CCP1 0x00000070 |
| #define GPIO_PCTL_PC1_TMS 0x00000010 |
| #define GPIO_PCTL_PC2_M 0x00000F00 |
| #define GPIO_PCTL_PC2_T5CCP0 0x00000700 |
| #define GPIO_PCTL_PC2_TDI 0x00000100 |
| #define GPIO_PCTL_PC3_M 0x0000F000 |
| #define GPIO_PCTL_PC3_T5CCP1 0x00007000 |
| #define GPIO_PCTL_PC3_TDO 0x00001000 |
| #define GPIO_PCTL_PC4_IDX1 0x00060000 |
| #define GPIO_PCTL_PC4_M 0x000F0000 |
| #define GPIO_PCTL_PC4_M0PWM6 0x00040000 |
| #define GPIO_PCTL_PC4_U1RTS 0x00080000 |
| #define GPIO_PCTL_PC4_U1RX 0x00020000 |
| #define GPIO_PCTL_PC4_U4RX 0x00010000 |
| #define GPIO_PCTL_PC4_WT0CCP0 0x00070000 |
| #define GPIO_PCTL_PC5_M 0x00F00000 |
| #define GPIO_PCTL_PC5_M0PWM7 0x00400000 |
| #define GPIO_PCTL_PC5_PHA1 0x00600000 |
| #define GPIO_PCTL_PC5_U1CTS 0x00800000 |
| #define GPIO_PCTL_PC5_U1TX 0x00200000 |
| #define GPIO_PCTL_PC5_U4TX 0x00100000 |
| #define GPIO_PCTL_PC5_WT0CCP1 0x00700000 |
| #define GPIO_PCTL_PC6_M 0x0F000000 |
| #define GPIO_PCTL_PC6_PHB1 0x06000000 |
| #define GPIO_PCTL_PC6_U3RX 0x01000000 |
| #define GPIO_PCTL_PC6_USB0EPEN 0x08000000 |
| #define GPIO_PCTL_PC6_WT1CCP0 0x07000000 |
| #define GPIO_PCTL_PC7_M 0xF0000000 |
| #define GPIO_PCTL_PC7_U3TX 0x10000000 |
| #define GPIO_PCTL_PC7_USB0PFLT 0x80000000 |
| #define GPIO_PCTL_PC7_WT1CCP1 0x70000000 |
| #define GPIO_PCTL_PD0_AIN15 0x00000000 |
| #define GPIO_PCTL_PD0_I2C3SCL 0x00000003 |
| #define GPIO_PCTL_PD0_M 0x0000000F |
| #define GPIO_PCTL_PD0_M0PWM6 0x00000004 |
| #define GPIO_PCTL_PD0_M1PWM0 0x00000005 |
| #define GPIO_PCTL_PD0_SSI1CLK 0x00000002 |
| #define GPIO_PCTL_PD0_SSI3CLK 0x00000001 |
| #define GPIO_PCTL_PD0_WT2CCP0 0x00000007 |
| #define GPIO_PCTL_PD1_AIN14 0x00000000 |
| #define GPIO_PCTL_PD1_I2C3SDA 0x00000030 |
| #define GPIO_PCTL_PD1_M 0x000000F0 |
| #define GPIO_PCTL_PD1_M0PWM7 0x00000040 |
| #define GPIO_PCTL_PD1_M1PWM1 0x00000050 |
| #define GPIO_PCTL_PD1_SSI1FSS 0x00000020 |
| #define GPIO_PCTL_PD1_SSI3FSS 0x00000010 |
| #define GPIO_PCTL_PD1_WT2CCP1 0x00000070 |
| #define GPIO_PCTL_PD2_AIN13 0x00000000 |
| #define GPIO_PCTL_PD2_M 0x00000F00 |
| #define GPIO_PCTL_PD2_M0FAULT0 0x00000400 |
| #define GPIO_PCTL_PD2_SSI1RX 0x00000200 |
| #define GPIO_PCTL_PD2_SSI3RX 0x00000100 |
| #define GPIO_PCTL_PD2_USB0EPEN 0x00000800 |
| #define GPIO_PCTL_PD2_WT3CCP0 0x00000700 |
| #define GPIO_PCTL_PD3_AIN12 0x00000000 |
| #define GPIO_PCTL_PD3_IDX0 0x00006000 |
| #define GPIO_PCTL_PD3_M 0x0000F000 |
| #define GPIO_PCTL_PD3_SSI1TX 0x00002000 |
| #define GPIO_PCTL_PD3_SSI3TX 0x00001000 |
| #define GPIO_PCTL_PD3_USB0PFLT 0x00008000 |
| #define GPIO_PCTL_PD3_WT3CCP1 0x00007000 |
| #define GPIO_PCTL_PD4_AIN7 0x00000000 |
| #define GPIO_PCTL_PD4_M 0x000F0000 |
| #define GPIO_PCTL_PD4_U6RX 0x00010000 |
| #define GPIO_PCTL_PD4_WT4CCP0 0x00070000 |
| #define GPIO_PCTL_PD5_M 0x00F00000 |
| #define GPIO_PCTL_PD5_U6TX 0x00100000 |
| #define GPIO_PCTL_PD5_WT4CCP1 0x00700000 |
| #define GPIO_PCTL_PD6_AIN5 0x00000000 |
| #define GPIO_PCTL_PD6_M 0x0F000000 |
| #define GPIO_PCTL_PD6_M0FAULT0 0x04000000 |
| #define GPIO_PCTL_PD6_PHA0 0x06000000 |
| #define GPIO_PCTL_PD6_U2RX 0x01000000 |
| #define GPIO_PCTL_PD6_WT5CCP0 0x07000000 |
| #define GPIO_PCTL_PD7_AIN4 0x00000000 |
| #define GPIO_PCTL_PD7_M 0xF0000000 |
| #define GPIO_PCTL_PD7_M0FAULT1 0x40000000 |
| #define GPIO_PCTL_PD7_NMI 0x80000000 |
| #define GPIO_PCTL_PD7_PHB0 0x60000000 |
| #define GPIO_PCTL_PD7_U2TX 0x10000000 |
| #define GPIO_PCTL_PD7_WT5CCP1 0x70000000 |
| #define GPIO_PCTL_PE0_AIN3 0x00000000 |
| #define GPIO_PCTL_PE0_M 0x0000000F |
| #define GPIO_PCTL_PE0_U7RX 0x00000001 |
| #define GPIO_PCTL_PE1_AIN2 0x00000000 |
| #define GPIO_PCTL_PE1_M 0x000000F0 |
| #define GPIO_PCTL_PE1_U7TX 0x00000010 |
| #define GPIO_PCTL_PE2_AIN1 0x00000000 |
| #define GPIO_PCTL_PE2_M 0x00000F00 |
| #define GPIO_PCTL_PE3_AIN0 0x00000000 |
| #define GPIO_PCTL_PE3_M 0x0000F000 |
| #define GPIO_PCTL_PE4_AIN9 0x00000000 |
| #define GPIO_PCTL_PE4_CAN0RX 0x00080000 |
| #define GPIO_PCTL_PE4_I2C2SCL 0x00030000 |
| #define GPIO_PCTL_PE4_M 0x000F0000 |
| #define GPIO_PCTL_PE4_M0PWM4 0x00040000 |
| #define GPIO_PCTL_PE4_M1PWM2 0x00050000 |
| #define GPIO_PCTL_PE4_U5RX 0x00010000 |
| #define GPIO_PCTL_PE5_AIN8 0x00000000 |
| #define GPIO_PCTL_PE5_CAN0TX 0x00800000 |
| #define GPIO_PCTL_PE5_I2C2SDA 0x00300000 |
| #define GPIO_PCTL_PE5_M 0x00F00000 |
| #define GPIO_PCTL_PE5_M0PWM5 0x00400000 |
| #define GPIO_PCTL_PE5_M1PWM3 0x00500000 |
| #define GPIO_PCTL_PE5_U5TX 0x00100000 |
| #define GPIO_PCTL_PE6_AIN21 0x00000000 |
| #define GPIO_PCTL_PE6_CAN1RX 0x08000000 |
| #define GPIO_PCTL_PE6_M 0x0F000000 |
| #define GPIO_PCTL_PE7_AIN20 0x00000000 |
| #define GPIO_PCTL_PE7_CAN1TX 0x80000000 |
| #define GPIO_PCTL_PE7_M 0xF0000000 |
| #define GPIO_PCTL_PE7_U1RI 0x10000000 |
| #define GPIO_PCTL_PF0_C0O 0x00000009 |
| #define GPIO_PCTL_PF0_CAN0RX 0x00000003 |
| #define GPIO_PCTL_PF0_M 0x0000000F |
| #define GPIO_PCTL_PF0_M1PWM4 0x00000005 |
| #define GPIO_PCTL_PF0_NMI 0x00000008 |
| #define GPIO_PCTL_PF0_PHA0 0x00000006 |
| #define GPIO_PCTL_PF0_SSI1RX 0x00000002 |
| #define GPIO_PCTL_PF0_T0CCP0 0x00000007 |
| #define GPIO_PCTL_PF0_TRD2 0x0000000E |
| #define GPIO_PCTL_PF0_U1RTS 0x00000001 |
| #define GPIO_PCTL_PF1_C1O 0x00000090 |
| #define GPIO_PCTL_PF1_M 0x000000F0 |
| #define GPIO_PCTL_PF1_M1PWM5 0x00000050 |
| #define GPIO_PCTL_PF1_PHB0 0x00000060 |
| #define GPIO_PCTL_PF1_SSI1TX 0x00000020 |
| #define GPIO_PCTL_PF1_T0CCP1 0x00000070 |
| #define GPIO_PCTL_PF1_TRD1 0x000000E0 |
| #define GPIO_PCTL_PF1_U1CTS 0x00000010 |
| #define GPIO_PCTL_PF2_C2O 0x00000900 |
| #define GPIO_PCTL_PF2_M 0x00000F00 |
| #define GPIO_PCTL_PF2_M0FAULT0 0x00000400 |
| #define GPIO_PCTL_PF2_M1PWM6 0x00000500 |
| #define GPIO_PCTL_PF2_SSI1CLK 0x00000200 |
| #define GPIO_PCTL_PF2_T1CCP0 0x00000700 |
| #define GPIO_PCTL_PF2_TRD0 0x00000E00 |
| #define GPIO_PCTL_PF2_U1DCD 0x00000100 |
| #define GPIO_PCTL_PF3_CAN0TX 0x00003000 |
| #define GPIO_PCTL_PF3_M 0x0000F000 |
| #define GPIO_PCTL_PF3_M0FAULT1 0x00004000 |
| #define GPIO_PCTL_PF3_M1PWM7 0x00005000 |
| #define GPIO_PCTL_PF3_SSI1FSS 0x00002000 |
| #define GPIO_PCTL_PF3_T1CCP1 0x00007000 |
| #define GPIO_PCTL_PF3_TRCLK 0x0000E000 |
| #define GPIO_PCTL_PF3_U1DSR 0x00001000 |
| #define GPIO_PCTL_PF4_IDX0 0x00060000 |
| #define GPIO_PCTL_PF4_M 0x000F0000 |
| #define GPIO_PCTL_PF4_M0FAULT2 0x00040000 |
| #define GPIO_PCTL_PF4_M1FAULT0 0x00050000 |
| #define GPIO_PCTL_PF4_T2CCP0 0x00070000 |
| #define GPIO_PCTL_PF4_TRD3 0x000E0000 |
| #define GPIO_PCTL_PF4_U1DTR 0x00010000 |
| #define GPIO_PCTL_PF4_USB0EPEN 0x00080000 |
| #define GPIO_PCTL_PF5_M 0x00F00000 |
| #define GPIO_PCTL_PF5_M0FAULT3 0x00400000 |
| #define GPIO_PCTL_PF5_T2CCP1 0x00700000 |
| #define GPIO_PCTL_PF5_USB0PFLT 0x00800000 |
| #define GPIO_PCTL_PF6_I2C2SCL 0x03000000 |
| #define GPIO_PCTL_PF6_M 0x0F000000 |
| #define GPIO_PCTL_PF6_T3CCP0 0x07000000 |
| #define GPIO_PCTL_PF7_I2C2SDA 0x30000000 |
| #define GPIO_PCTL_PF7_M 0xF0000000 |
| #define GPIO_PCTL_PF7_M1FAULT0 0x50000000 |
| #define GPIO_PCTL_PF7_T3CCP1 0x70000000 |
| #define GPIO_PCTL_PG0_I2C3SCL 0x00000003 |
| #define GPIO_PCTL_PG0_M 0x0000000F |
| #define GPIO_PCTL_PG0_M1FAULT1 0x00000005 |
| #define GPIO_PCTL_PG0_PHA1 0x00000006 |
| #define GPIO_PCTL_PG0_T4CCP0 0x00000007 |
| #define GPIO_PCTL_PG1_I2C3SDA 0x00000030 |
| #define GPIO_PCTL_PG1_M 0x000000F0 |
| #define GPIO_PCTL_PG1_M1FAULT2 0x00000050 |
| #define GPIO_PCTL_PG1_PHB1 0x00000060 |
| #define GPIO_PCTL_PG1_T4CCP1 0x00000070 |
| #define GPIO_PCTL_PG2_I2C4SCL 0x00000300 |
| #define GPIO_PCTL_PG2_M 0x00000F00 |
| #define GPIO_PCTL_PG2_M0FAULT1 0x00000400 |
| #define GPIO_PCTL_PG2_M1PWM0 0x00000500 |
| #define GPIO_PCTL_PG2_T5CCP0 0x00000700 |
| #define GPIO_PCTL_PG3_I2C4SDA 0x00003000 |
| #define GPIO_PCTL_PG3_M 0x0000F000 |
| #define GPIO_PCTL_PG3_M0FAULT2 0x00004000 |
| #define GPIO_PCTL_PG3_M1PWM1 0x00005000 |
| #define GPIO_PCTL_PG3_PHA1 0x00006000 |
| #define GPIO_PCTL_PG3_T5CCP1 0x00007000 |
| #define GPIO_PCTL_PG4_I2C1SCL 0x00030000 |
| #define GPIO_PCTL_PG4_M 0x000F0000 |
| #define GPIO_PCTL_PG4_M0PWM4 0x00040000 |
| #define GPIO_PCTL_PG4_M1PWM2 0x00050000 |
| #define GPIO_PCTL_PG4_PHB1 0x00060000 |
| #define GPIO_PCTL_PG4_U2RX 0x00010000 |
| #define GPIO_PCTL_PG4_USB0EPEN 0x00080000 |
| #define GPIO_PCTL_PG4_WT0CCP0 0x00070000 |
| #define GPIO_PCTL_PG5_I2C1SDA 0x00300000 |
| #define GPIO_PCTL_PG5_IDX1 0x00600000 |
| #define GPIO_PCTL_PG5_M 0x00F00000 |
| #define GPIO_PCTL_PG5_M0PWM5 0x00400000 |
| #define GPIO_PCTL_PG5_M1PWM3 0x00500000 |
| #define GPIO_PCTL_PG5_U2TX 0x00100000 |
| #define GPIO_PCTL_PG5_USB0PFLT 0x00800000 |
| #define GPIO_PCTL_PG5_WT0CCP1 0x00700000 |
| #define GPIO_PCTL_PG6_I2C5SCL 0x03000000 |
| #define GPIO_PCTL_PG6_M 0x0F000000 |
| #define GPIO_PCTL_PG6_M0PWM6 0x04000000 |
| #define GPIO_PCTL_PG6_WT1CCP0 0x07000000 |
| #define GPIO_PCTL_PG7_I2C5SDA 0x30000000 |
| #define GPIO_PCTL_PG7_IDX1 0x50000000 |
| #define GPIO_PCTL_PG7_M 0xF0000000 |
| #define GPIO_PCTL_PG7_M0PWM7 0x40000000 |
| #define GPIO_PCTL_PG7_WT1CCP1 0x70000000 |
| #define GPIO_PCTL_PH0_M 0x0000000F |
| #define GPIO_PCTL_PH0_M0FAULT0 0x00000006 |
| #define GPIO_PCTL_PH0_M0PWM0 0x00000004 |
| #define GPIO_PCTL_PH0_SSI3CLK 0x00000002 |
| #define GPIO_PCTL_PH0_WT2CCP0 0x00000007 |
| #define GPIO_PCTL_PH1_IDX0 0x00000050 |
| #define GPIO_PCTL_PH1_M 0x000000F0 |
| #define GPIO_PCTL_PH1_M0FAULT1 0x00000060 |
| #define GPIO_PCTL_PH1_M0PWM1 0x00000040 |
| #define GPIO_PCTL_PH1_SSI3FSS 0x00000020 |
| #define GPIO_PCTL_PH1_WT2CCP1 0x00000070 |
| #define GPIO_PCTL_PH2_M 0x00000F00 |
| #define GPIO_PCTL_PH2_M0FAULT2 0x00000600 |
| #define GPIO_PCTL_PH2_M0PWM2 0x00000400 |
| #define GPIO_PCTL_PH2_SSI3RX 0x00000200 |
| #define GPIO_PCTL_PH2_WT5CCP0 0x00000700 |
| #define GPIO_PCTL_PH3_M 0x0000F000 |
| #define GPIO_PCTL_PH3_M0FAULT3 0x00006000 |
| #define GPIO_PCTL_PH3_M0PWM3 0x00004000 |
| #define GPIO_PCTL_PH3_SSI3TX 0x00002000 |
| #define GPIO_PCTL_PH3_WT5CCP1 0x00007000 |
| #define GPIO_PCTL_PH4_M 0x000F0000 |
| #define GPIO_PCTL_PH4_M0PWM4 0x00040000 |
| #define GPIO_PCTL_PH4_PHA0 0x00050000 |
| #define GPIO_PCTL_PH4_SSI2CLK 0x00020000 |
| #define GPIO_PCTL_PH4_WT3CCP0 0x00070000 |
| #define GPIO_PCTL_PH5_M 0x00F00000 |
| #define GPIO_PCTL_PH5_M0PWM5 0x00400000 |
| #define GPIO_PCTL_PH5_PHB0 0x00500000 |
| #define GPIO_PCTL_PH5_SSI2FSS 0x00200000 |
| #define GPIO_PCTL_PH5_WT3CCP1 0x00700000 |
| #define GPIO_PCTL_PH6_M 0x0F000000 |
| #define GPIO_PCTL_PH6_M0PWM6 0x04000000 |
| #define GPIO_PCTL_PH6_SSI2RX 0x02000000 |
| #define GPIO_PCTL_PH6_WT4CCP0 0x07000000 |
| #define GPIO_PCTL_PH7_M 0xF0000000 |
| #define GPIO_PCTL_PH7_M0PWM7 0x40000000 |
| #define GPIO_PCTL_PH7_SSI2TX 0x20000000 |
| #define GPIO_PCTL_PH7_WT4CCP1 0x70000000 |
| #define GPIO_PCTL_PJ0_M 0x0000000F |
| #define GPIO_PCTL_PJ0_T1CCP0 0x00000007 |
| #define GPIO_PCTL_PJ0_U4RX 0x00000001 |
| #define GPIO_PCTL_PJ1_M 0x000000F0 |
| #define GPIO_PCTL_PJ1_T1CCP1 0x00000070 |
| #define GPIO_PCTL_PJ1_U4TX 0x00000010 |
| #define GPIO_PCTL_PJ2_IDX0 0x00000500 |
| #define GPIO_PCTL_PJ2_M 0x00000F00 |
| #define GPIO_PCTL_PJ2_T2CCP0 0x00000700 |
| #define GPIO_PCTL_PJ2_U5RX 0x00000100 |
| #define GPIO_PCTL_PJ3_M 0x0000F000 |
| #define GPIO_PCTL_PJ3_T2CCP1 0x00007000 |
| #define GPIO_PCTL_PJ3_U5TX 0x00001000 |
| #define GPIO_PCTL_PJ4_C2P 0x00000000 |
| #define GPIO_PCTL_PJ4_M 0x000F0000 |
| #define GPIO_PCTL_PJ4_T3CCP0 0x00070000 |
| #define GPIO_PCTL_PJ4_U6RX 0x00010000 |
| #define GPIO_PCTL_PJ5_C2M 0x00000000 |
| #define GPIO_PCTL_PJ5_M 0x00F00000 |
| #define GPIO_PCTL_PJ5_T3CCP1 0x00700000 |
| #define GPIO_PCTL_PJ5_U6TX 0x00100000 |
| #define GPIO_PCTL_PJ6_M 0x0F000000 |
| #define GPIO_PCTL_PJ7_M 0xF0000000 |
| #define GPIO_PCTL_PK0_AIN16 0x00000000 |
| #define GPIO_PCTL_PK0_M 0x0000000F |
| #define GPIO_PCTL_PK0_M1FAULT0 0x00000006 |
| #define GPIO_PCTL_PK0_SSI3CLK 0x00000002 |
| #define GPIO_PCTL_PK1_AIN17 0x00000000 |
| #define GPIO_PCTL_PK1_M 0x000000F0 |
| #define GPIO_PCTL_PK1_M1FAULT1 0x00000060 |
| #define GPIO_PCTL_PK1_SSI3FSS 0x00000020 |
| #define GPIO_PCTL_PK2_AIN18 0x00000000 |
| #define GPIO_PCTL_PK2_M 0x00000F00 |
| #define GPIO_PCTL_PK2_M1FAULT2 0x00000600 |
| #define GPIO_PCTL_PK2_SSI3RX 0x00000200 |
| #define GPIO_PCTL_PK3_AIN19 0x00000000 |
| #define GPIO_PCTL_PK3_M 0x0000F000 |
| #define GPIO_PCTL_PK3_M1FAULT3 0x00006000 |
| #define GPIO_PCTL_PK3_SSI3TX 0x00002000 |
| #define GPIO_PCTL_PK4_C0O 0x00080000 |
| #define GPIO_PCTL_PK4_M 0x000F0000 |
| #define GPIO_PCTL_PK4_M0FAULT0 0x00060000 |
| #define GPIO_PCTL_PK4_RTCCLK 0x00070000 |
| #define GPIO_PCTL_PK4_U7RX 0x00010000 |
| #define GPIO_PCTL_PK5_C1O 0x00800000 |
| #define GPIO_PCTL_PK5_M 0x00F00000 |
| #define GPIO_PCTL_PK5_M0FAULT1 0x00600000 |
| #define GPIO_PCTL_PK5_U7TX 0x00100000 |
| #define GPIO_PCTL_PK6_C2O 0x08000000 |
| #define GPIO_PCTL_PK6_M 0x0F000000 |
| #define GPIO_PCTL_PK6_M0FAULT2 0x06000000 |
| #define GPIO_PCTL_PK6_WT1CCP0 0x07000000 |
| #define GPIO_PCTL_PK7_M 0xF0000000 |
| #define GPIO_PCTL_PK7_M0FAULT3 0x60000000 |
| #define GPIO_PCTL_PK7_WT1CCP1 0x70000000 |
| #define GPIO_PCTL_PL0_M 0x0000000F |
| #define GPIO_PCTL_PL0_T0CCP0 0x00000007 |
| #define GPIO_PCTL_PL0_WT0CCP0 0x00000008 |
| #define GPIO_PCTL_PL1_M 0x000000F0 |
| #define GPIO_PCTL_PL1_T0CCP1 0x00000070 |
| #define GPIO_PCTL_PL1_WT0CCP1 0x00000080 |
| #define GPIO_PCTL_PL2_M 0x00000F00 |
| #define GPIO_PCTL_PL2_T1CCP0 0x00000700 |
| #define GPIO_PCTL_PL2_WT1CCP0 0x00000800 |
| #define GPIO_PCTL_PL3_M 0x0000F000 |
| #define GPIO_PCTL_PL3_T1CCP1 0x00007000 |
| #define GPIO_PCTL_PL3_WT1CCP1 0x00008000 |
| #define GPIO_PCTL_PL4_M 0x000F0000 |
| #define GPIO_PCTL_PL4_T2CCP0 0x00070000 |
| #define GPIO_PCTL_PL4_WT2CCP0 0x00080000 |
| #define GPIO_PCTL_PL5_M 0x00F00000 |
| #define GPIO_PCTL_PL5_T2CCP1 0x00700000 |
| #define GPIO_PCTL_PL5_WT2CCP1 0x00800000 |
| #define GPIO_PCTL_PL6_M 0x0F000000 |
| #define GPIO_PCTL_PL6_T3CCP0 0x07000000 |
| #define GPIO_PCTL_PL6_USB0DP 0x00000000 |
| #define GPIO_PCTL_PL6_WT3CCP0 0x08000000 |
| #define GPIO_PCTL_PL7_M 0xF0000000 |
| #define GPIO_PCTL_PL7_T3CCP1 0x70000000 |
| #define GPIO_PCTL_PL7_USB0DM 0x00000000 |
| #define GPIO_PCTL_PL7_WT3CCP1 0x80000000 |
| #define GPIO_PCTL_PM0_M 0x0000000F |
| #define GPIO_PCTL_PM0_T4CCP0 0x00000007 |
| #define GPIO_PCTL_PM0_WT4CCP0 0x00000008 |
| #define GPIO_PCTL_PM1_M 0x000000F0 |
| #define GPIO_PCTL_PM1_T4CCP1 0x00000070 |
| #define GPIO_PCTL_PM1_WT4CCP1 0x00000080 |
| #define GPIO_PCTL_PM2_M 0x00000F00 |
| #define GPIO_PCTL_PM2_T5CCP0 0x00000700 |
| #define GPIO_PCTL_PM2_WT5CCP0 0x00000800 |
| #define GPIO_PCTL_PM3_M 0x0000F000 |
| #define GPIO_PCTL_PM3_T5CCP1 0x00007000 |
| #define GPIO_PCTL_PM3_WT5CCP1 0x00008000 |
| #define GPIO_PCTL_PM4_M 0x000F0000 |
| #define GPIO_PCTL_PM5_M 0x00F00000 |
| #define GPIO_PCTL_PM6_M 0x0F000000 |
| #define GPIO_PCTL_PM6_M0PWM4 0x02000000 |
| #define GPIO_PCTL_PM6_WT0CCP0 0x07000000 |
| #define GPIO_PCTL_PM7_M 0xF0000000 |
| #define GPIO_PCTL_PM7_M0PWM5 0x20000000 |
| #define GPIO_PCTL_PM7_WT0CCP1 0x70000000 |
| #define GPIO_PCTL_PN0_CAN0RX 0x00000001 |
| #define GPIO_PCTL_PN0_M 0x0000000F |
| #define GPIO_PCTL_PN1_CAN0TX 0x00000010 |
| #define GPIO_PCTL_PN1_M 0x000000F0 |
| #define GPIO_PCTL_PN2_M 0x00000F00 |
| #define GPIO_PCTL_PN2_M0PWM6 0x00000200 |
| #define GPIO_PCTL_PN2_WT2CCP0 0x00000700 |
| #define GPIO_PCTL_PN3_M 0x0000F000 |
| #define GPIO_PCTL_PN3_M0PWM7 0x00002000 |
| #define GPIO_PCTL_PN3_WT2CCP1 0x00007000 |
| #define GPIO_PCTL_PN4_M 0x000F0000 |
| #define GPIO_PCTL_PN4_M1PWM4 0x00020000 |
| #define GPIO_PCTL_PN4_WT3CCP0 0x00070000 |
| #define GPIO_PCTL_PN5_M 0x00F00000 |
| #define GPIO_PCTL_PN5_M1PWM5 0x00200000 |
| #define GPIO_PCTL_PN5_WT3CCP1 0x00700000 |
| #define GPIO_PCTL_PN6_M 0x0F000000 |
| #define GPIO_PCTL_PN6_M1PWM6 0x02000000 |
| #define GPIO_PCTL_PN6_WT4CCP0 0x07000000 |
| #define GPIO_PCTL_PN7_M 0xF0000000 |
| #define GPIO_PCTL_PN7_M1PWM7 0x20000000 |
| #define GPIO_PCTL_PN7_WT4CCP1 0x70000000 |
| #define GPIO_PCTL_PP0_AIN23 0x00000000 |
| #define GPIO_PCTL_PP0_M 0x0000000F |
| #define GPIO_PCTL_PP0_M0PWM0 0x00000001 |
| #define GPIO_PCTL_PP0_T4CCP0 0x00000007 |
| #define GPIO_PCTL_PP1_AIN22 0x00000000 |
| #define GPIO_PCTL_PP1_M 0x000000F0 |
| #define GPIO_PCTL_PP1_M0PWM1 0x00000010 |
| #define GPIO_PCTL_PP1_T4CCP1 0x00000070 |
| #define GPIO_PCTL_PP2_M 0x00000F00 |
| #define GPIO_PCTL_PP2_M0PWM2 0x00000100 |
| #define GPIO_PCTL_PP2_T5CCP0 0x00000700 |
| #define GPIO_PORTA_ADCCTL_R (*((volatile uint32_t *)0x40004530)) |
| #define GPIO_PORTA_AFSEL_R (*((volatile uint32_t *)0x40004420)) |
| #define GPIO_PORTA_AHB_ADCCTL_R (*((volatile uint32_t *)0x40058530)) |
| #define GPIO_PORTA_AHB_AFSEL_R (*((volatile uint32_t *)0x40058420)) |
| #define GPIO_PORTA_AHB_AMSEL_R (*((volatile uint32_t *)0x40058528)) |
| #define GPIO_PORTA_AHB_CR_R (*((volatile uint32_t *)0x40058524)) |
| #define GPIO_PORTA_AHB_DATA_BITS_R ((volatile uint32_t *)0x40058000) |
| #define GPIO_PORTA_AHB_DATA_R (*((volatile uint32_t *)0x400583FC)) |
| #define GPIO_PORTA_AHB_DEN_R (*((volatile uint32_t *)0x4005851C)) |
| #define GPIO_PORTA_AHB_DIR_R (*((volatile uint32_t *)0x40058400)) |
| #define GPIO_PORTA_AHB_DMACTL_R (*((volatile uint32_t *)0x40058534)) |
| #define GPIO_PORTA_AHB_DR2R_R (*((volatile uint32_t *)0x40058500)) |
| #define GPIO_PORTA_AHB_DR4R_R (*((volatile uint32_t *)0x40058504)) |
| #define GPIO_PORTA_AHB_DR8R_R (*((volatile uint32_t *)0x40058508)) |
| #define GPIO_PORTA_AHB_IBE_R (*((volatile uint32_t *)0x40058408)) |
| #define GPIO_PORTA_AHB_ICR_R (*((volatile uint32_t *)0x4005841C)) |
| #define GPIO_PORTA_AHB_IEV_R (*((volatile uint32_t *)0x4005840C)) |
| #define GPIO_PORTA_AHB_IM_R (*((volatile uint32_t *)0x40058410)) |
| #define GPIO_PORTA_AHB_IS_R (*((volatile uint32_t *)0x40058404)) |
| #define GPIO_PORTA_AHB_LOCK_R (*((volatile uint32_t *)0x40058520)) |
| #define GPIO_PORTA_AHB_MIS_R (*((volatile uint32_t *)0x40058418)) |
| #define GPIO_PORTA_AHB_ODR_R (*((volatile uint32_t *)0x4005850C)) |
| #define GPIO_PORTA_AHB_PCTL_R (*((volatile uint32_t *)0x4005852C)) |
| #define GPIO_PORTA_AHB_PDR_R (*((volatile uint32_t *)0x40058514)) |
| #define GPIO_PORTA_AHB_PUR_R (*((volatile uint32_t *)0x40058510)) |
| #define GPIO_PORTA_AHB_RIS_R (*((volatile uint32_t *)0x40058414)) |
| #define GPIO_PORTA_AHB_SI_R (*((volatile uint32_t *)0x40058538)) |
| #define GPIO_PORTA_AHB_SLR_R (*((volatile uint32_t *)0x40058518)) |
| #define GPIO_PORTA_AMSEL_R (*((volatile uint32_t *)0x40004528)) |
| #define GPIO_PORTA_CR_R (*((volatile uint32_t *)0x40004524)) |
| #define GPIO_PORTA_DATA_BITS_R ((volatile uint32_t *)0x40004000) |
| #define GPIO_PORTA_DATA_R (*((volatile uint32_t *)0x400043FC)) |
| #define GPIO_PORTA_DEN_R (*((volatile uint32_t *)0x4000451C)) |
| #define GPIO_PORTA_DIR_R (*((volatile uint32_t *)0x40004400)) |
| #define GPIO_PORTA_DMACTL_R (*((volatile uint32_t *)0x40004534)) |
| #define GPIO_PORTA_DR2R_R (*((volatile uint32_t *)0x40004500)) |
| #define GPIO_PORTA_DR4R_R (*((volatile uint32_t *)0x40004504)) |
| #define GPIO_PORTA_DR8R_R (*((volatile uint32_t *)0x40004508)) |
| #define GPIO_PORTA_IBE_R (*((volatile uint32_t *)0x40004408)) |
| #define GPIO_PORTA_ICR_R (*((volatile uint32_t *)0x4000441C)) |
| #define GPIO_PORTA_IEV_R (*((volatile uint32_t *)0x4000440C)) |
| #define GPIO_PORTA_IM_R (*((volatile uint32_t *)0x40004410)) |
| #define GPIO_PORTA_IS_R (*((volatile uint32_t *)0x40004404)) |
| #define GPIO_PORTA_LOCK_R (*((volatile uint32_t *)0x40004520)) |
| #define GPIO_PORTA_MIS_R (*((volatile uint32_t *)0x40004418)) |
| #define GPIO_PORTA_ODR_R (*((volatile uint32_t *)0x4000450C)) |
| #define GPIO_PORTA_PCTL_R (*((volatile uint32_t *)0x4000452C)) |
| #define GPIO_PORTA_PDR_R (*((volatile uint32_t *)0x40004514)) |
| #define GPIO_PORTA_PUR_R (*((volatile uint32_t *)0x40004510)) |
| #define GPIO_PORTA_RIS_R (*((volatile uint32_t *)0x40004414)) |
| #define GPIO_PORTA_SI_R (*((volatile uint32_t *)0x40004538)) |
| #define GPIO_PORTA_SLR_R (*((volatile uint32_t *)0x40004518)) |
| #define GPIO_PORTB_ADCCTL_R (*((volatile uint32_t *)0x40005530)) |
| #define GPIO_PORTB_AFSEL_R (*((volatile uint32_t *)0x40005420)) |
| #define GPIO_PORTB_AHB_ADCCTL_R (*((volatile uint32_t *)0x40059530)) |
| #define GPIO_PORTB_AHB_AFSEL_R (*((volatile uint32_t *)0x40059420)) |
| #define GPIO_PORTB_AHB_AMSEL_R (*((volatile uint32_t *)0x40059528)) |
| #define GPIO_PORTB_AHB_CR_R (*((volatile uint32_t *)0x40059524)) |
| #define GPIO_PORTB_AHB_DATA_BITS_R ((volatile uint32_t *)0x40059000) |
| #define GPIO_PORTB_AHB_DATA_R (*((volatile uint32_t *)0x400593FC)) |
| #define GPIO_PORTB_AHB_DEN_R (*((volatile uint32_t *)0x4005951C)) |
| #define GPIO_PORTB_AHB_DIR_R (*((volatile uint32_t *)0x40059400)) |
| #define GPIO_PORTB_AHB_DMACTL_R (*((volatile uint32_t *)0x40059534)) |
| #define GPIO_PORTB_AHB_DR2R_R (*((volatile uint32_t *)0x40059500)) |
| #define GPIO_PORTB_AHB_DR4R_R (*((volatile uint32_t *)0x40059504)) |
| #define GPIO_PORTB_AHB_DR8R_R (*((volatile uint32_t *)0x40059508)) |
| #define GPIO_PORTB_AHB_IBE_R (*((volatile uint32_t *)0x40059408)) |
| #define GPIO_PORTB_AHB_ICR_R (*((volatile uint32_t *)0x4005941C)) |
| #define GPIO_PORTB_AHB_IEV_R (*((volatile uint32_t *)0x4005940C)) |
| #define GPIO_PORTB_AHB_IM_R (*((volatile uint32_t *)0x40059410)) |
| #define GPIO_PORTB_AHB_IS_R (*((volatile uint32_t *)0x40059404)) |
| #define GPIO_PORTB_AHB_LOCK_R (*((volatile uint32_t *)0x40059520)) |
| #define GPIO_PORTB_AHB_MIS_R (*((volatile uint32_t *)0x40059418)) |
| #define GPIO_PORTB_AHB_ODR_R (*((volatile uint32_t *)0x4005950C)) |
| #define GPIO_PORTB_AHB_PCTL_R (*((volatile uint32_t *)0x4005952C)) |
| #define GPIO_PORTB_AHB_PDR_R (*((volatile uint32_t *)0x40059514)) |
| #define GPIO_PORTB_AHB_PUR_R (*((volatile uint32_t *)0x40059510)) |
| #define GPIO_PORTB_AHB_RIS_R (*((volatile uint32_t *)0x40059414)) |
| #define GPIO_PORTB_AHB_SI_R (*((volatile uint32_t *)0x40059538)) |
| #define GPIO_PORTB_AHB_SLR_R (*((volatile uint32_t *)0x40059518)) |
| #define GPIO_PORTB_AMSEL_R (*((volatile uint32_t *)0x40005528)) |
| #define GPIO_PORTB_CR_R (*((volatile uint32_t *)0x40005524)) |
| #define GPIO_PORTB_DATA_BITS_R ((volatile uint32_t *)0x40005000) |
| #define GPIO_PORTB_DATA_R (*((volatile uint32_t *)0x400053FC)) |
| #define GPIO_PORTB_DEN_R (*((volatile uint32_t *)0x4000551C)) |
| #define GPIO_PORTB_DIR_R (*((volatile uint32_t *)0x40005400)) |
| #define GPIO_PORTB_DMACTL_R (*((volatile uint32_t *)0x40005534)) |
| #define GPIO_PORTB_DR2R_R (*((volatile uint32_t *)0x40005500)) |
| #define GPIO_PORTB_DR4R_R (*((volatile uint32_t *)0x40005504)) |
| #define GPIO_PORTB_DR8R_R (*((volatile uint32_t *)0x40005508)) |
| #define GPIO_PORTB_IBE_R (*((volatile uint32_t *)0x40005408)) |
| #define GPIO_PORTB_ICR_R (*((volatile uint32_t *)0x4000541C)) |
| #define GPIO_PORTB_IEV_R (*((volatile uint32_t *)0x4000540C)) |
| #define GPIO_PORTB_IM_R (*((volatile uint32_t *)0x40005410)) |
| #define GPIO_PORTB_IS_R (*((volatile uint32_t *)0x40005404)) |
| #define GPIO_PORTB_LOCK_R (*((volatile uint32_t *)0x40005520)) |
| #define GPIO_PORTB_MIS_R (*((volatile uint32_t *)0x40005418)) |
| #define GPIO_PORTB_ODR_R (*((volatile uint32_t *)0x4000550C)) |
| #define GPIO_PORTB_PCTL_R (*((volatile uint32_t *)0x4000552C)) |
| #define GPIO_PORTB_PDR_R (*((volatile uint32_t *)0x40005514)) |
| #define GPIO_PORTB_PUR_R (*((volatile uint32_t *)0x40005510)) |
| #define GPIO_PORTB_RIS_R (*((volatile uint32_t *)0x40005414)) |
| #define GPIO_PORTB_SI_R (*((volatile uint32_t *)0x40005538)) |
| #define GPIO_PORTB_SLR_R (*((volatile uint32_t *)0x40005518)) |
| #define GPIO_PORTC_ADCCTL_R (*((volatile uint32_t *)0x40006530)) |
| #define GPIO_PORTC_AFSEL_R (*((volatile uint32_t *)0x40006420)) |
| #define GPIO_PORTC_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005A530)) |
| #define GPIO_PORTC_AHB_AFSEL_R (*((volatile uint32_t *)0x4005A420)) |
| #define GPIO_PORTC_AHB_AMSEL_R (*((volatile uint32_t *)0x4005A528)) |
| #define GPIO_PORTC_AHB_CR_R (*((volatile uint32_t *)0x4005A524)) |
| #define GPIO_PORTC_AHB_DATA_BITS_R ((volatile uint32_t *)0x4005A000) |
| #define GPIO_PORTC_AHB_DATA_R (*((volatile uint32_t *)0x4005A3FC)) |
| #define GPIO_PORTC_AHB_DEN_R (*((volatile uint32_t *)0x4005A51C)) |
| #define GPIO_PORTC_AHB_DIR_R (*((volatile uint32_t *)0x4005A400)) |
| #define GPIO_PORTC_AHB_DMACTL_R (*((volatile uint32_t *)0x4005A534)) |
| #define GPIO_PORTC_AHB_DR2R_R (*((volatile uint32_t *)0x4005A500)) |
| #define GPIO_PORTC_AHB_DR4R_R (*((volatile uint32_t *)0x4005A504)) |
| #define GPIO_PORTC_AHB_DR8R_R (*((volatile uint32_t *)0x4005A508)) |
| #define GPIO_PORTC_AHB_IBE_R (*((volatile uint32_t *)0x4005A408)) |
| #define GPIO_PORTC_AHB_ICR_R (*((volatile uint32_t *)0x4005A41C)) |
| #define GPIO_PORTC_AHB_IEV_R (*((volatile uint32_t *)0x4005A40C)) |
| #define GPIO_PORTC_AHB_IM_R (*((volatile uint32_t *)0x4005A410)) |
| #define GPIO_PORTC_AHB_IS_R (*((volatile uint32_t *)0x4005A404)) |
| #define GPIO_PORTC_AHB_LOCK_R (*((volatile uint32_t *)0x4005A520)) |
| #define GPIO_PORTC_AHB_MIS_R (*((volatile uint32_t *)0x4005A418)) |
| #define GPIO_PORTC_AHB_ODR_R (*((volatile uint32_t *)0x4005A50C)) |
| #define GPIO_PORTC_AHB_PCTL_R (*((volatile uint32_t *)0x4005A52C)) |
| #define GPIO_PORTC_AHB_PDR_R (*((volatile uint32_t *)0x4005A514)) |
| #define GPIO_PORTC_AHB_PUR_R (*((volatile uint32_t *)0x4005A510)) |
| #define GPIO_PORTC_AHB_RIS_R (*((volatile uint32_t *)0x4005A414)) |
| #define GPIO_PORTC_AHB_SI_R (*((volatile uint32_t *)0x4005A538)) |
| #define GPIO_PORTC_AHB_SLR_R (*((volatile uint32_t *)0x4005A518)) |
| #define GPIO_PORTC_AMSEL_R (*((volatile uint32_t *)0x40006528)) |
| #define GPIO_PORTC_CR_R (*((volatile uint32_t *)0x40006524)) |
| #define GPIO_PORTC_DATA_BITS_R ((volatile uint32_t *)0x40006000) |
| #define GPIO_PORTC_DATA_R (*((volatile uint32_t *)0x400063FC)) |
| #define GPIO_PORTC_DEN_R (*((volatile uint32_t *)0x4000651C)) |
| #define GPIO_PORTC_DIR_R (*((volatile uint32_t *)0x40006400)) |
| #define GPIO_PORTC_DMACTL_R (*((volatile uint32_t *)0x40006534)) |
| #define GPIO_PORTC_DR2R_R (*((volatile uint32_t *)0x40006500)) |
| #define GPIO_PORTC_DR4R_R (*((volatile uint32_t *)0x40006504)) |
| #define GPIO_PORTC_DR8R_R (*((volatile uint32_t *)0x40006508)) |
| #define GPIO_PORTC_IBE_R (*((volatile uint32_t *)0x40006408)) |
| #define GPIO_PORTC_ICR_R (*((volatile uint32_t *)0x4000641C)) |
| #define GPIO_PORTC_IEV_R (*((volatile uint32_t *)0x4000640C)) |
| #define GPIO_PORTC_IM_R (*((volatile uint32_t *)0x40006410)) |
| #define GPIO_PORTC_IS_R (*((volatile uint32_t *)0x40006404)) |
| #define GPIO_PORTC_LOCK_R (*((volatile uint32_t *)0x40006520)) |
| #define GPIO_PORTC_MIS_R (*((volatile uint32_t *)0x40006418)) |
| #define GPIO_PORTC_ODR_R (*((volatile uint32_t *)0x4000650C)) |
| #define GPIO_PORTC_PCTL_R (*((volatile uint32_t *)0x4000652C)) |
| #define GPIO_PORTC_PDR_R (*((volatile uint32_t *)0x40006514)) |
| #define GPIO_PORTC_PUR_R (*((volatile uint32_t *)0x40006510)) |
| #define GPIO_PORTC_RIS_R (*((volatile uint32_t *)0x40006414)) |
| #define GPIO_PORTC_SI_R (*((volatile uint32_t *)0x40006538)) |
| #define GPIO_PORTC_SLR_R (*((volatile uint32_t *)0x40006518)) |
| #define GPIO_PORTD_ADCCTL_R (*((volatile uint32_t *)0x40007530)) |
| #define GPIO_PORTD_AFSEL_R (*((volatile uint32_t *)0x40007420)) |
| #define GPIO_PORTD_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005B530)) |
| #define GPIO_PORTD_AHB_AFSEL_R (*((volatile uint32_t *)0x4005B420)) |
| #define GPIO_PORTD_AHB_AMSEL_R (*((volatile uint32_t *)0x4005B528)) |
| #define GPIO_PORTD_AHB_CR_R (*((volatile uint32_t *)0x4005B524)) |
| #define GPIO_PORTD_AHB_DATA_BITS_R ((volatile uint32_t *)0x4005B000) |
| #define GPIO_PORTD_AHB_DATA_R (*((volatile uint32_t *)0x4005B3FC)) |
| #define GPIO_PORTD_AHB_DEN_R (*((volatile uint32_t *)0x4005B51C)) |
| #define GPIO_PORTD_AHB_DIR_R (*((volatile uint32_t *)0x4005B400)) |
| #define GPIO_PORTD_AHB_DMACTL_R (*((volatile uint32_t *)0x4005B534)) |
| #define GPIO_PORTD_AHB_DR2R_R (*((volatile uint32_t *)0x4005B500)) |
| #define GPIO_PORTD_AHB_DR4R_R (*((volatile uint32_t *)0x4005B504)) |
| #define GPIO_PORTD_AHB_DR8R_R (*((volatile uint32_t *)0x4005B508)) |
| #define GPIO_PORTD_AHB_IBE_R (*((volatile uint32_t *)0x4005B408)) |
| #define GPIO_PORTD_AHB_ICR_R (*((volatile uint32_t *)0x4005B41C)) |
| #define GPIO_PORTD_AHB_IEV_R (*((volatile uint32_t *)0x4005B40C)) |
| #define GPIO_PORTD_AHB_IM_R (*((volatile uint32_t *)0x4005B410)) |
| #define GPIO_PORTD_AHB_IS_R (*((volatile uint32_t *)0x4005B404)) |
| #define GPIO_PORTD_AHB_LOCK_R (*((volatile uint32_t *)0x4005B520)) |
| #define GPIO_PORTD_AHB_MIS_R (*((volatile uint32_t *)0x4005B418)) |
| #define GPIO_PORTD_AHB_ODR_R (*((volatile uint32_t *)0x4005B50C)) |
| #define GPIO_PORTD_AHB_PCTL_R (*((volatile uint32_t *)0x4005B52C)) |
| #define GPIO_PORTD_AHB_PDR_R (*((volatile uint32_t *)0x4005B514)) |
| #define GPIO_PORTD_AHB_PUR_R (*((volatile uint32_t *)0x4005B510)) |
| #define GPIO_PORTD_AHB_RIS_R (*((volatile uint32_t *)0x4005B414)) |
| #define GPIO_PORTD_AHB_SI_R (*((volatile uint32_t *)0x4005B538)) |
| #define GPIO_PORTD_AHB_SLR_R (*((volatile uint32_t *)0x4005B518)) |
| #define GPIO_PORTD_AMSEL_R (*((volatile uint32_t *)0x40007528)) |
| #define GPIO_PORTD_CR_R (*((volatile uint32_t *)0x40007524)) |
| #define GPIO_PORTD_DATA_BITS_R ((volatile uint32_t *)0x40007000) |
| #define GPIO_PORTD_DATA_R (*((volatile uint32_t *)0x400073FC)) |
| #define GPIO_PORTD_DEN_R (*((volatile uint32_t *)0x4000751C)) |
| #define GPIO_PORTD_DIR_R (*((volatile uint32_t *)0x40007400)) |
| #define GPIO_PORTD_DMACTL_R (*((volatile uint32_t *)0x40007534)) |
| #define GPIO_PORTD_DR2R_R (*((volatile uint32_t *)0x40007500)) |
| #define GPIO_PORTD_DR4R_R (*((volatile uint32_t *)0x40007504)) |
| #define GPIO_PORTD_DR8R_R (*((volatile uint32_t *)0x40007508)) |
| #define GPIO_PORTD_IBE_R (*((volatile uint32_t *)0x40007408)) |
| #define GPIO_PORTD_ICR_R (*((volatile uint32_t *)0x4000741C)) |
| #define GPIO_PORTD_IEV_R (*((volatile uint32_t *)0x4000740C)) |
| #define GPIO_PORTD_IM_R (*((volatile uint32_t *)0x40007410)) |
| #define GPIO_PORTD_IS_R (*((volatile uint32_t *)0x40007404)) |
| #define GPIO_PORTD_LOCK_R (*((volatile uint32_t *)0x40007520)) |
| #define GPIO_PORTD_MIS_R (*((volatile uint32_t *)0x40007418)) |
| #define GPIO_PORTD_ODR_R (*((volatile uint32_t *)0x4000750C)) |
| #define GPIO_PORTD_PCTL_R (*((volatile uint32_t *)0x4000752C)) |
| #define GPIO_PORTD_PDR_R (*((volatile uint32_t *)0x40007514)) |
| #define GPIO_PORTD_PUR_R (*((volatile uint32_t *)0x40007510)) |
| #define GPIO_PORTD_RIS_R (*((volatile uint32_t *)0x40007414)) |
| #define GPIO_PORTD_SI_R (*((volatile uint32_t *)0x40007538)) |
| #define GPIO_PORTD_SLR_R (*((volatile uint32_t *)0x40007518)) |
| #define GPIO_PORTE_ADCCTL_R (*((volatile uint32_t *)0x40024530)) |
| #define GPIO_PORTE_AFSEL_R (*((volatile uint32_t *)0x40024420)) |
| #define GPIO_PORTE_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005C530)) |
| #define GPIO_PORTE_AHB_AFSEL_R (*((volatile uint32_t *)0x4005C420)) |
| #define GPIO_PORTE_AHB_AMSEL_R (*((volatile uint32_t *)0x4005C528)) |
| #define GPIO_PORTE_AHB_CR_R (*((volatile uint32_t *)0x4005C524)) |
| #define GPIO_PORTE_AHB_DATA_BITS_R ((volatile uint32_t *)0x4005C000) |
| #define GPIO_PORTE_AHB_DATA_R (*((volatile uint32_t *)0x4005C3FC)) |
| #define GPIO_PORTE_AHB_DEN_R (*((volatile uint32_t *)0x4005C51C)) |
| #define GPIO_PORTE_AHB_DIR_R (*((volatile uint32_t *)0x4005C400)) |
| #define GPIO_PORTE_AHB_DMACTL_R (*((volatile uint32_t *)0x4005C534)) |
| #define GPIO_PORTE_AHB_DR2R_R (*((volatile uint32_t *)0x4005C500)) |
| #define GPIO_PORTE_AHB_DR4R_R (*((volatile uint32_t *)0x4005C504)) |
| #define GPIO_PORTE_AHB_DR8R_R (*((volatile uint32_t *)0x4005C508)) |
| #define GPIO_PORTE_AHB_IBE_R (*((volatile uint32_t *)0x4005C408)) |
| #define GPIO_PORTE_AHB_ICR_R (*((volatile uint32_t *)0x4005C41C)) |
| #define GPIO_PORTE_AHB_IEV_R (*((volatile uint32_t *)0x4005C40C)) |
| #define GPIO_PORTE_AHB_IM_R (*((volatile uint32_t *)0x4005C410)) |
| #define GPIO_PORTE_AHB_IS_R (*((volatile uint32_t *)0x4005C404)) |
| #define GPIO_PORTE_AHB_LOCK_R (*((volatile uint32_t *)0x4005C520)) |
| #define GPIO_PORTE_AHB_MIS_R (*((volatile uint32_t *)0x4005C418)) |
| #define GPIO_PORTE_AHB_ODR_R (*((volatile uint32_t *)0x4005C50C)) |
| #define GPIO_PORTE_AHB_PCTL_R (*((volatile uint32_t *)0x4005C52C)) |
| #define GPIO_PORTE_AHB_PDR_R (*((volatile uint32_t *)0x4005C514)) |
| #define GPIO_PORTE_AHB_PUR_R (*((volatile uint32_t *)0x4005C510)) |
| #define GPIO_PORTE_AHB_RIS_R (*((volatile uint32_t *)0x4005C414)) |
| #define GPIO_PORTE_AHB_SI_R (*((volatile uint32_t *)0x4005C538)) |
| #define GPIO_PORTE_AHB_SLR_R (*((volatile uint32_t *)0x4005C518)) |
| #define GPIO_PORTE_AMSEL_R (*((volatile uint32_t *)0x40024528)) |
| #define GPIO_PORTE_CR_R (*((volatile uint32_t *)0x40024524)) |
| #define GPIO_PORTE_DATA_BITS_R ((volatile uint32_t *)0x40024000) |
| #define GPIO_PORTE_DATA_R (*((volatile uint32_t *)0x400243FC)) |
| #define GPIO_PORTE_DEN_R (*((volatile uint32_t *)0x4002451C)) |
| #define GPIO_PORTE_DIR_R (*((volatile uint32_t *)0x40024400)) |
| #define GPIO_PORTE_DMACTL_R (*((volatile uint32_t *)0x40024534)) |
| #define GPIO_PORTE_DR2R_R (*((volatile uint32_t *)0x40024500)) |
| #define GPIO_PORTE_DR4R_R (*((volatile uint32_t *)0x40024504)) |
| #define GPIO_PORTE_DR8R_R (*((volatile uint32_t *)0x40024508)) |
| #define GPIO_PORTE_IBE_R (*((volatile uint32_t *)0x40024408)) |
| #define GPIO_PORTE_ICR_R (*((volatile uint32_t *)0x4002441C)) |
| #define GPIO_PORTE_IEV_R (*((volatile uint32_t *)0x4002440C)) |
| #define GPIO_PORTE_IM_R (*((volatile uint32_t *)0x40024410)) |
| #define GPIO_PORTE_IS_R (*((volatile uint32_t *)0x40024404)) |
| #define GPIO_PORTE_LOCK_R (*((volatile uint32_t *)0x40024520)) |
| #define GPIO_PORTE_MIS_R (*((volatile uint32_t *)0x40024418)) |
| #define GPIO_PORTE_ODR_R (*((volatile uint32_t *)0x4002450C)) |
| #define GPIO_PORTE_PCTL_R (*((volatile uint32_t *)0x4002452C)) |
| #define GPIO_PORTE_PDR_R (*((volatile uint32_t *)0x40024514)) |
| #define GPIO_PORTE_PUR_R (*((volatile uint32_t *)0x40024510)) |
| #define GPIO_PORTE_RIS_R (*((volatile uint32_t *)0x40024414)) |
| #define GPIO_PORTE_SI_R (*((volatile uint32_t *)0x40024538)) |
| #define GPIO_PORTE_SLR_R (*((volatile uint32_t *)0x40024518)) |
| #define GPIO_PORTF_ADCCTL_R (*((volatile uint32_t *)0x40025530)) |
| #define GPIO_PORTF_AFSEL_R (*((volatile uint32_t *)0x40025420)) |
| #define GPIO_PORTF_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005D530)) |
| #define GPIO_PORTF_AHB_AFSEL_R (*((volatile uint32_t *)0x4005D420)) |
| #define GPIO_PORTF_AHB_AMSEL_R (*((volatile uint32_t *)0x4005D528)) |
| #define GPIO_PORTF_AHB_CR_R (*((volatile uint32_t *)0x4005D524)) |
| #define GPIO_PORTF_AHB_DATA_BITS_R ((volatile uint32_t *)0x4005D000) |
| #define GPIO_PORTF_AHB_DATA_R (*((volatile uint32_t *)0x4005D3FC)) |
| #define GPIO_PORTF_AHB_DEN_R (*((volatile uint32_t *)0x4005D51C)) |
| #define GPIO_PORTF_AHB_DIR_R (*((volatile uint32_t *)0x4005D400)) |
| #define GPIO_PORTF_AHB_DMACTL_R (*((volatile uint32_t *)0x4005D534)) |
| #define GPIO_PORTF_AHB_DR2R_R (*((volatile uint32_t *)0x4005D500)) |
| #define GPIO_PORTF_AHB_DR4R_R (*((volatile uint32_t *)0x4005D504)) |
| #define GPIO_PORTF_AHB_DR8R_R (*((volatile uint32_t *)0x4005D508)) |
| #define GPIO_PORTF_AHB_IBE_R (*((volatile uint32_t *)0x4005D408)) |
| #define GPIO_PORTF_AHB_ICR_R (*((volatile uint32_t *)0x4005D41C)) |
| #define GPIO_PORTF_AHB_IEV_R (*((volatile uint32_t *)0x4005D40C)) |
| #define GPIO_PORTF_AHB_IM_R (*((volatile uint32_t *)0x4005D410)) |
| #define GPIO_PORTF_AHB_IS_R (*((volatile uint32_t *)0x4005D404)) |
| #define GPIO_PORTF_AHB_LOCK_R (*((volatile uint32_t *)0x4005D520)) |
| #define GPIO_PORTF_AHB_MIS_R (*((volatile uint32_t *)0x4005D418)) |
| #define GPIO_PORTF_AHB_ODR_R (*((volatile uint32_t *)0x4005D50C)) |
| #define GPIO_PORTF_AHB_PCTL_R (*((volatile uint32_t *)0x4005D52C)) |
| #define GPIO_PORTF_AHB_PDR_R (*((volatile uint32_t *)0x4005D514)) |
| #define GPIO_PORTF_AHB_PUR_R (*((volatile uint32_t *)0x4005D510)) |
| #define GPIO_PORTF_AHB_RIS_R (*((volatile uint32_t *)0x4005D414)) |
| #define GPIO_PORTF_AHB_SI_R (*((volatile uint32_t *)0x4005D538)) |
| #define GPIO_PORTF_AHB_SLR_R (*((volatile uint32_t *)0x4005D518)) |
| #define GPIO_PORTF_AMSEL_R (*((volatile uint32_t *)0x40025528)) |
| #define GPIO_PORTF_CR_R (*((volatile uint32_t *)0x40025524)) |
| #define GPIO_PORTF_DATA_BITS_R ((volatile uint32_t *)0x40025000) |
| #define GPIO_PORTF_DATA_R (*((volatile uint32_t *)0x400253FC)) |
| #define GPIO_PORTF_DEN_R (*((volatile uint32_t *)0x4002551C)) |
| #define GPIO_PORTF_DIR_R (*((volatile uint32_t *)0x40025400)) |
| #define GPIO_PORTF_DMACTL_R (*((volatile uint32_t *)0x40025534)) |
| #define GPIO_PORTF_DR2R_R (*((volatile uint32_t *)0x40025500)) |
| #define GPIO_PORTF_DR4R_R (*((volatile uint32_t *)0x40025504)) |
| #define GPIO_PORTF_DR8R_R (*((volatile uint32_t *)0x40025508)) |
| #define GPIO_PORTF_IBE_R (*((volatile uint32_t *)0x40025408)) |
| #define GPIO_PORTF_ICR_R (*((volatile uint32_t *)0x4002541C)) |
| #define GPIO_PORTF_IEV_R (*((volatile uint32_t *)0x4002540C)) |
| #define GPIO_PORTF_IM_R (*((volatile uint32_t *)0x40025410)) |
| #define GPIO_PORTF_IS_R (*((volatile uint32_t *)0x40025404)) |
| #define GPIO_PORTF_LOCK_R (*((volatile uint32_t *)0x40025520)) |
| #define GPIO_PORTF_MIS_R (*((volatile uint32_t *)0x40025418)) |
| #define GPIO_PORTF_ODR_R (*((volatile uint32_t *)0x4002550C)) |
| #define GPIO_PORTF_PCTL_R (*((volatile uint32_t *)0x4002552C)) |
| #define GPIO_PORTF_PDR_R (*((volatile uint32_t *)0x40025514)) |
| #define GPIO_PORTF_PUR_R (*((volatile uint32_t *)0x40025510)) |
| #define GPIO_PORTF_RIS_R (*((volatile uint32_t *)0x40025414)) |
| #define GPIO_PORTF_SI_R (*((volatile uint32_t *)0x40025538)) |
| #define GPIO_PORTF_SLR_R (*((volatile uint32_t *)0x40025518)) |
| #define GPIO_PORTG_ADCCTL_R (*((volatile uint32_t *)0x40026530)) |
| #define GPIO_PORTG_AFSEL_R (*((volatile uint32_t *)0x40026420)) |
| #define GPIO_PORTG_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005E530)) |
| #define GPIO_PORTG_AHB_AFSEL_R (*((volatile uint32_t *)0x4005E420)) |
| #define GPIO_PORTG_AHB_AMSEL_R (*((volatile uint32_t *)0x4005E528)) |
| #define GPIO_PORTG_AHB_CR_R (*((volatile uint32_t *)0x4005E524)) |
| #define GPIO_PORTG_AHB_DATA_BITS_R ((volatile uint32_t *)0x4005E000) |
| #define GPIO_PORTG_AHB_DATA_R (*((volatile uint32_t *)0x4005E3FC)) |
| #define GPIO_PORTG_AHB_DEN_R (*((volatile uint32_t *)0x4005E51C)) |
| #define GPIO_PORTG_AHB_DIR_R (*((volatile uint32_t *)0x4005E400)) |
| #define GPIO_PORTG_AHB_DMACTL_R (*((volatile uint32_t *)0x4005E534)) |
| #define GPIO_PORTG_AHB_DR2R_R (*((volatile uint32_t *)0x4005E500)) |
| #define GPIO_PORTG_AHB_DR4R_R (*((volatile uint32_t *)0x4005E504)) |
| #define GPIO_PORTG_AHB_DR8R_R (*((volatile uint32_t *)0x4005E508)) |
| #define GPIO_PORTG_AHB_IBE_R (*((volatile uint32_t *)0x4005E408)) |
| #define GPIO_PORTG_AHB_ICR_R (*((volatile uint32_t *)0x4005E41C)) |
| #define GPIO_PORTG_AHB_IEV_R (*((volatile uint32_t *)0x4005E40C)) |
| #define GPIO_PORTG_AHB_IM_R (*((volatile uint32_t *)0x4005E410)) |
| #define GPIO_PORTG_AHB_IS_R (*((volatile uint32_t *)0x4005E404)) |
| #define GPIO_PORTG_AHB_LOCK_R (*((volatile uint32_t *)0x4005E520)) |
| #define GPIO_PORTG_AHB_MIS_R (*((volatile uint32_t *)0x4005E418)) |
| #define GPIO_PORTG_AHB_ODR_R (*((volatile uint32_t *)0x4005E50C)) |
| #define GPIO_PORTG_AHB_PCTL_R (*((volatile uint32_t *)0x4005E52C)) |
| #define GPIO_PORTG_AHB_PDR_R (*((volatile uint32_t *)0x4005E514)) |
| #define GPIO_PORTG_AHB_PUR_R (*((volatile uint32_t *)0x4005E510)) |
| #define GPIO_PORTG_AHB_RIS_R (*((volatile uint32_t *)0x4005E414)) |
| #define GPIO_PORTG_AHB_SI_R (*((volatile uint32_t *)0x4005E538)) |
| #define GPIO_PORTG_AHB_SLR_R (*((volatile uint32_t *)0x4005E518)) |
| #define GPIO_PORTG_AMSEL_R (*((volatile uint32_t *)0x40026528)) |
| #define GPIO_PORTG_CR_R (*((volatile uint32_t *)0x40026524)) |
| #define GPIO_PORTG_DATA_BITS_R ((volatile uint32_t *)0x40026000) |
| #define GPIO_PORTG_DATA_R (*((volatile uint32_t *)0x400263FC)) |
| #define GPIO_PORTG_DEN_R (*((volatile uint32_t *)0x4002651C)) |
| #define GPIO_PORTG_DIR_R (*((volatile uint32_t *)0x40026400)) |
| #define GPIO_PORTG_DMACTL_R (*((volatile uint32_t *)0x40026534)) |
| #define GPIO_PORTG_DR2R_R (*((volatile uint32_t *)0x40026500)) |
| #define GPIO_PORTG_DR4R_R (*((volatile uint32_t *)0x40026504)) |
| #define GPIO_PORTG_DR8R_R (*((volatile uint32_t *)0x40026508)) |
| #define GPIO_PORTG_IBE_R (*((volatile uint32_t *)0x40026408)) |
| #define GPIO_PORTG_ICR_R (*((volatile uint32_t *)0x4002641C)) |
| #define GPIO_PORTG_IEV_R (*((volatile uint32_t *)0x4002640C)) |
| #define GPIO_PORTG_IM_R (*((volatile uint32_t *)0x40026410)) |
| #define GPIO_PORTG_IS_R (*((volatile uint32_t *)0x40026404)) |
| #define GPIO_PORTG_LOCK_R (*((volatile uint32_t *)0x40026520)) |
| #define GPIO_PORTG_MIS_R (*((volatile uint32_t *)0x40026418)) |
| #define GPIO_PORTG_ODR_R (*((volatile uint32_t *)0x4002650C)) |
| #define GPIO_PORTG_PCTL_R (*((volatile uint32_t *)0x4002652C)) |
| #define GPIO_PORTG_PDR_R (*((volatile uint32_t *)0x40026514)) |
| #define GPIO_PORTG_PUR_R (*((volatile uint32_t *)0x40026510)) |
| #define GPIO_PORTG_RIS_R (*((volatile uint32_t *)0x40026414)) |
| #define GPIO_PORTG_SI_R (*((volatile uint32_t *)0x40026538)) |
| #define GPIO_PORTG_SLR_R (*((volatile uint32_t *)0x40026518)) |
| #define GPIO_PORTH_ADCCTL_R (*((volatile uint32_t *)0x40027530)) |
| #define GPIO_PORTH_AFSEL_R (*((volatile uint32_t *)0x40027420)) |
| #define GPIO_PORTH_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005F530)) |
| #define GPIO_PORTH_AHB_AFSEL_R (*((volatile uint32_t *)0x4005F420)) |
| #define GPIO_PORTH_AHB_AMSEL_R (*((volatile uint32_t *)0x4005F528)) |
| #define GPIO_PORTH_AHB_CR_R (*((volatile uint32_t *)0x4005F524)) |
| #define GPIO_PORTH_AHB_DATA_BITS_R ((volatile uint32_t *)0x4005F000) |
| #define GPIO_PORTH_AHB_DATA_R (*((volatile uint32_t *)0x4005F3FC)) |
| #define GPIO_PORTH_AHB_DEN_R (*((volatile uint32_t *)0x4005F51C)) |
| #define GPIO_PORTH_AHB_DIR_R (*((volatile uint32_t *)0x4005F400)) |
| #define GPIO_PORTH_AHB_DMACTL_R (*((volatile uint32_t *)0x4005F534)) |
| #define GPIO_PORTH_AHB_DR2R_R (*((volatile uint32_t *)0x4005F500)) |
| #define GPIO_PORTH_AHB_DR4R_R (*((volatile uint32_t *)0x4005F504)) |
| #define GPIO_PORTH_AHB_DR8R_R (*((volatile uint32_t *)0x4005F508)) |
| #define GPIO_PORTH_AHB_IBE_R (*((volatile uint32_t *)0x4005F408)) |
| #define GPIO_PORTH_AHB_ICR_R (*((volatile uint32_t *)0x4005F41C)) |
| #define GPIO_PORTH_AHB_IEV_R (*((volatile uint32_t *)0x4005F40C)) |
| #define GPIO_PORTH_AHB_IM_R (*((volatile uint32_t *)0x4005F410)) |
| #define GPIO_PORTH_AHB_IS_R (*((volatile uint32_t *)0x4005F404)) |
| #define GPIO_PORTH_AHB_LOCK_R (*((volatile uint32_t *)0x4005F520)) |
| #define GPIO_PORTH_AHB_MIS_R (*((volatile uint32_t *)0x4005F418)) |
| #define GPIO_PORTH_AHB_ODR_R (*((volatile uint32_t *)0x4005F50C)) |
| #define GPIO_PORTH_AHB_PCTL_R (*((volatile uint32_t *)0x4005F52C)) |
| #define GPIO_PORTH_AHB_PDR_R (*((volatile uint32_t *)0x4005F514)) |
| #define GPIO_PORTH_AHB_PUR_R (*((volatile uint32_t *)0x4005F510)) |
| #define GPIO_PORTH_AHB_RIS_R (*((volatile uint32_t *)0x4005F414)) |
| #define GPIO_PORTH_AHB_SI_R (*((volatile uint32_t *)0x4005F538)) |
| #define GPIO_PORTH_AHB_SLR_R (*((volatile uint32_t *)0x4005F518)) |
| #define GPIO_PORTH_AMSEL_R (*((volatile uint32_t *)0x40027528)) |
| #define GPIO_PORTH_CR_R (*((volatile uint32_t *)0x40027524)) |
| #define GPIO_PORTH_DATA_BITS_R ((volatile uint32_t *)0x40027000) |
| #define GPIO_PORTH_DATA_R (*((volatile uint32_t *)0x400273FC)) |
| #define GPIO_PORTH_DEN_R (*((volatile uint32_t *)0x4002751C)) |
| #define GPIO_PORTH_DIR_R (*((volatile uint32_t *)0x40027400)) |
| #define GPIO_PORTH_DMACTL_R (*((volatile uint32_t *)0x40027534)) |
| #define GPIO_PORTH_DR2R_R (*((volatile uint32_t *)0x40027500)) |
| #define GPIO_PORTH_DR4R_R (*((volatile uint32_t *)0x40027504)) |
| #define GPIO_PORTH_DR8R_R (*((volatile uint32_t *)0x40027508)) |
| #define GPIO_PORTH_IBE_R (*((volatile uint32_t *)0x40027408)) |
| #define GPIO_PORTH_ICR_R (*((volatile uint32_t *)0x4002741C)) |
| #define GPIO_PORTH_IEV_R (*((volatile uint32_t *)0x4002740C)) |
| #define GPIO_PORTH_IM_R (*((volatile uint32_t *)0x40027410)) |
| #define GPIO_PORTH_IS_R (*((volatile uint32_t *)0x40027404)) |
| #define GPIO_PORTH_LOCK_R (*((volatile uint32_t *)0x40027520)) |
| #define GPIO_PORTH_MIS_R (*((volatile uint32_t *)0x40027418)) |
| #define GPIO_PORTH_ODR_R (*((volatile uint32_t *)0x4002750C)) |
| #define GPIO_PORTH_PCTL_R (*((volatile uint32_t *)0x4002752C)) |
| #define GPIO_PORTH_PDR_R (*((volatile uint32_t *)0x40027514)) |
| #define GPIO_PORTH_PUR_R (*((volatile uint32_t *)0x40027510)) |
| #define GPIO_PORTH_RIS_R (*((volatile uint32_t *)0x40027414)) |
| #define GPIO_PORTH_SI_R (*((volatile uint32_t *)0x40027538)) |
| #define GPIO_PORTH_SLR_R (*((volatile uint32_t *)0x40027518)) |
| #define GPIO_PORTJ_ADCCTL_R (*((volatile uint32_t *)0x4003D530)) |
| #define GPIO_PORTJ_AFSEL_R (*((volatile uint32_t *)0x4003D420)) |
| #define GPIO_PORTJ_AHB_ADCCTL_R (*((volatile uint32_t *)0x40060530)) |
| #define GPIO_PORTJ_AHB_AFSEL_R (*((volatile uint32_t *)0x40060420)) |
| #define GPIO_PORTJ_AHB_AMSEL_R (*((volatile uint32_t *)0x40060528)) |
| #define GPIO_PORTJ_AHB_CR_R (*((volatile uint32_t *)0x40060524)) |
| #define GPIO_PORTJ_AHB_DATA_BITS_R ((volatile uint32_t *)0x40060000) |
| #define GPIO_PORTJ_AHB_DATA_R (*((volatile uint32_t *)0x400603FC)) |
| #define GPIO_PORTJ_AHB_DEN_R (*((volatile uint32_t *)0x4006051C)) |
| #define GPIO_PORTJ_AHB_DIR_R (*((volatile uint32_t *)0x40060400)) |
| #define GPIO_PORTJ_AHB_DMACTL_R (*((volatile uint32_t *)0x40060534)) |
| #define GPIO_PORTJ_AHB_DR2R_R (*((volatile uint32_t *)0x40060500)) |
| #define GPIO_PORTJ_AHB_DR4R_R (*((volatile uint32_t *)0x40060504)) |
| #define GPIO_PORTJ_AHB_DR8R_R (*((volatile uint32_t *)0x40060508)) |
| #define GPIO_PORTJ_AHB_IBE_R (*((volatile uint32_t *)0x40060408)) |
| #define GPIO_PORTJ_AHB_ICR_R (*((volatile uint32_t *)0x4006041C)) |
| #define GPIO_PORTJ_AHB_IEV_R (*((volatile uint32_t *)0x4006040C)) |
| #define GPIO_PORTJ_AHB_IM_R (*((volatile uint32_t *)0x40060410)) |
| #define GPIO_PORTJ_AHB_IS_R (*((volatile uint32_t *)0x40060404)) |
| #define GPIO_PORTJ_AHB_LOCK_R (*((volatile uint32_t *)0x40060520)) |
| #define GPIO_PORTJ_AHB_MIS_R (*((volatile uint32_t *)0x40060418)) |
| #define GPIO_PORTJ_AHB_ODR_R (*((volatile uint32_t *)0x4006050C)) |
| #define GPIO_PORTJ_AHB_PCTL_R (*((volatile uint32_t *)0x4006052C)) |
| #define GPIO_PORTJ_AHB_PDR_R (*((volatile uint32_t *)0x40060514)) |
| #define GPIO_PORTJ_AHB_PUR_R (*((volatile uint32_t *)0x40060510)) |
| #define GPIO_PORTJ_AHB_RIS_R (*((volatile uint32_t *)0x40060414)) |
| #define GPIO_PORTJ_AHB_SI_R (*((volatile uint32_t *)0x40060538)) |
| #define GPIO_PORTJ_AHB_SLR_R (*((volatile uint32_t *)0x40060518)) |
| #define GPIO_PORTJ_AMSEL_R (*((volatile uint32_t *)0x4003D528)) |
| #define GPIO_PORTJ_CR_R (*((volatile uint32_t *)0x4003D524)) |
| #define GPIO_PORTJ_DATA_BITS_R ((volatile uint32_t *)0x4003D000) |
| #define GPIO_PORTJ_DATA_R (*((volatile uint32_t *)0x4003D3FC)) |
| #define GPIO_PORTJ_DEN_R (*((volatile uint32_t *)0x4003D51C)) |
| #define GPIO_PORTJ_DIR_R (*((volatile uint32_t *)0x4003D400)) |
| #define GPIO_PORTJ_DMACTL_R (*((volatile uint32_t *)0x4003D534)) |
| #define GPIO_PORTJ_DR2R_R (*((volatile uint32_t *)0x4003D500)) |
| #define GPIO_PORTJ_DR4R_R (*((volatile uint32_t *)0x4003D504)) |
| #define GPIO_PORTJ_DR8R_R (*((volatile uint32_t *)0x4003D508)) |
| #define GPIO_PORTJ_IBE_R (*((volatile uint32_t *)0x4003D408)) |
| #define GPIO_PORTJ_ICR_R (*((volatile uint32_t *)0x4003D41C)) |
| #define GPIO_PORTJ_IEV_R (*((volatile uint32_t *)0x4003D40C)) |
| #define GPIO_PORTJ_IM_R (*((volatile uint32_t *)0x4003D410)) |
| #define GPIO_PORTJ_IS_R (*((volatile uint32_t *)0x4003D404)) |
| #define GPIO_PORTJ_LOCK_R (*((volatile uint32_t *)0x4003D520)) |
| #define GPIO_PORTJ_MIS_R (*((volatile uint32_t *)0x4003D418)) |
| #define GPIO_PORTJ_ODR_R (*((volatile uint32_t *)0x4003D50C)) |
| #define GPIO_PORTJ_PCTL_R (*((volatile uint32_t *)0x4003D52C)) |
| #define GPIO_PORTJ_PDR_R (*((volatile uint32_t *)0x4003D514)) |
| #define GPIO_PORTJ_PUR_R (*((volatile uint32_t *)0x4003D510)) |
| #define GPIO_PORTJ_RIS_R (*((volatile uint32_t *)0x4003D414)) |
| #define GPIO_PORTJ_SI_R (*((volatile uint32_t *)0x4003D538)) |
| #define GPIO_PORTJ_SLR_R (*((volatile uint32_t *)0x4003D518)) |
| #define GPIO_PORTK_ADCCTL_R (*((volatile uint32_t *)0x40061530)) |
| #define GPIO_PORTK_AFSEL_R (*((volatile uint32_t *)0x40061420)) |
| #define GPIO_PORTK_AMSEL_R (*((volatile uint32_t *)0x40061528)) |
| #define GPIO_PORTK_CR_R (*((volatile uint32_t *)0x40061524)) |
| #define GPIO_PORTK_DATA_BITS_R ((volatile uint32_t *)0x40061000) |
| #define GPIO_PORTK_DATA_R (*((volatile uint32_t *)0x400613FC)) |
| #define GPIO_PORTK_DEN_R (*((volatile uint32_t *)0x4006151C)) |
| #define GPIO_PORTK_DIR_R (*((volatile uint32_t *)0x40061400)) |
| #define GPIO_PORTK_DMACTL_R (*((volatile uint32_t *)0x40061534)) |
| #define GPIO_PORTK_DR2R_R (*((volatile uint32_t *)0x40061500)) |
| #define GPIO_PORTK_DR4R_R (*((volatile uint32_t *)0x40061504)) |
| #define GPIO_PORTK_DR8R_R (*((volatile uint32_t *)0x40061508)) |
| #define GPIO_PORTK_IBE_R (*((volatile uint32_t *)0x40061408)) |
| #define GPIO_PORTK_ICR_R (*((volatile uint32_t *)0x4006141C)) |
| #define GPIO_PORTK_IEV_R (*((volatile uint32_t *)0x4006140C)) |
| #define GPIO_PORTK_IM_R (*((volatile uint32_t *)0x40061410)) |
| #define GPIO_PORTK_IS_R (*((volatile uint32_t *)0x40061404)) |
| #define GPIO_PORTK_LOCK_R (*((volatile uint32_t *)0x40061520)) |
| #define GPIO_PORTK_MIS_R (*((volatile uint32_t *)0x40061418)) |
| #define GPIO_PORTK_ODR_R (*((volatile uint32_t *)0x4006150C)) |
| #define GPIO_PORTK_PCTL_R (*((volatile uint32_t *)0x4006152C)) |
| #define GPIO_PORTK_PDR_R (*((volatile uint32_t *)0x40061514)) |
| #define GPIO_PORTK_PUR_R (*((volatile uint32_t *)0x40061510)) |
| #define GPIO_PORTK_RIS_R (*((volatile uint32_t *)0x40061414)) |
| #define GPIO_PORTK_SI_R (*((volatile uint32_t *)0x40061538)) |
| #define GPIO_PORTK_SLR_R (*((volatile uint32_t *)0x40061518)) |
| #define GPIO_PORTL_ADCCTL_R (*((volatile uint32_t *)0x40062530)) |
| #define GPIO_PORTL_AFSEL_R (*((volatile uint32_t *)0x40062420)) |
| #define GPIO_PORTL_AMSEL_R (*((volatile uint32_t *)0x40062528)) |
| #define GPIO_PORTL_CR_R (*((volatile uint32_t *)0x40062524)) |
| #define GPIO_PORTL_DATA_BITS_R ((volatile uint32_t *)0x40062000) |
| #define GPIO_PORTL_DATA_R (*((volatile uint32_t *)0x400623FC)) |
| #define GPIO_PORTL_DEN_R (*((volatile uint32_t *)0x4006251C)) |
| #define GPIO_PORTL_DIR_R (*((volatile uint32_t *)0x40062400)) |
| #define GPIO_PORTL_DMACTL_R (*((volatile uint32_t *)0x40062534)) |
| #define GPIO_PORTL_DR2R_R (*((volatile uint32_t *)0x40062500)) |
| #define GPIO_PORTL_DR4R_R (*((volatile uint32_t *)0x40062504)) |
| #define GPIO_PORTL_DR8R_R (*((volatile uint32_t *)0x40062508)) |
| #define GPIO_PORTL_IBE_R (*((volatile uint32_t *)0x40062408)) |
| #define GPIO_PORTL_ICR_R (*((volatile uint32_t *)0x4006241C)) |
| #define GPIO_PORTL_IEV_R (*((volatile uint32_t *)0x4006240C)) |
| #define GPIO_PORTL_IM_R (*((volatile uint32_t *)0x40062410)) |
| #define GPIO_PORTL_IS_R (*((volatile uint32_t *)0x40062404)) |
| #define GPIO_PORTL_LOCK_R (*((volatile uint32_t *)0x40062520)) |
| #define GPIO_PORTL_MIS_R (*((volatile uint32_t *)0x40062418)) |
| #define GPIO_PORTL_ODR_R (*((volatile uint32_t *)0x4006250C)) |
| #define GPIO_PORTL_PCTL_R (*((volatile uint32_t *)0x4006252C)) |
| #define GPIO_PORTL_PDR_R (*((volatile uint32_t *)0x40062514)) |
| #define GPIO_PORTL_PUR_R (*((volatile uint32_t *)0x40062510)) |
| #define GPIO_PORTL_RIS_R (*((volatile uint32_t *)0x40062414)) |
| #define GPIO_PORTL_SI_R (*((volatile uint32_t *)0x40062538)) |
| #define GPIO_PORTL_SLR_R (*((volatile uint32_t *)0x40062518)) |
| #define GPIO_PORTM_ADCCTL_R (*((volatile uint32_t *)0x40063530)) |
| #define GPIO_PORTM_AFSEL_R (*((volatile uint32_t *)0x40063420)) |
| #define GPIO_PORTM_AMSEL_R (*((volatile uint32_t *)0x40063528)) |
| #define GPIO_PORTM_CR_R (*((volatile uint32_t *)0x40063524)) |
| #define GPIO_PORTM_DATA_BITS_R ((volatile uint32_t *)0x40063000) |
| #define GPIO_PORTM_DATA_R (*((volatile uint32_t *)0x400633FC)) |
| #define GPIO_PORTM_DEN_R (*((volatile uint32_t *)0x4006351C)) |
| #define GPIO_PORTM_DIR_R (*((volatile uint32_t *)0x40063400)) |
| #define GPIO_PORTM_DMACTL_R (*((volatile uint32_t *)0x40063534)) |
| #define GPIO_PORTM_DR2R_R (*((volatile uint32_t *)0x40063500)) |
| #define GPIO_PORTM_DR4R_R (*((volatile uint32_t *)0x40063504)) |
| #define GPIO_PORTM_DR8R_R (*((volatile uint32_t *)0x40063508)) |
| #define GPIO_PORTM_IBE_R (*((volatile uint32_t *)0x40063408)) |
| #define GPIO_PORTM_ICR_R (*((volatile uint32_t *)0x4006341C)) |
| #define GPIO_PORTM_IEV_R (*((volatile uint32_t *)0x4006340C)) |
| #define GPIO_PORTM_IM_R (*((volatile uint32_t *)0x40063410)) |
| #define GPIO_PORTM_IS_R (*((volatile uint32_t *)0x40063404)) |
| #define GPIO_PORTM_LOCK_R (*((volatile uint32_t *)0x40063520)) |
| #define GPIO_PORTM_MIS_R (*((volatile uint32_t *)0x40063418)) |
| #define GPIO_PORTM_ODR_R (*((volatile uint32_t *)0x4006350C)) |
| #define GPIO_PORTM_PCTL_R (*((volatile uint32_t *)0x4006352C)) |
| #define GPIO_PORTM_PDR_R (*((volatile uint32_t *)0x40063514)) |
| #define GPIO_PORTM_PUR_R (*((volatile uint32_t *)0x40063510)) |
| #define GPIO_PORTM_RIS_R (*((volatile uint32_t *)0x40063414)) |
| #define GPIO_PORTM_SI_R (*((volatile uint32_t *)0x40063538)) |
| #define GPIO_PORTM_SLR_R (*((volatile uint32_t *)0x40063518)) |
| #define GPIO_PORTN_ADCCTL_R (*((volatile uint32_t *)0x40064530)) |
| #define GPIO_PORTN_AFSEL_R (*((volatile uint32_t *)0x40064420)) |
| #define GPIO_PORTN_AMSEL_R (*((volatile uint32_t *)0x40064528)) |
| #define GPIO_PORTN_CR_R (*((volatile uint32_t *)0x40064524)) |
| #define GPIO_PORTN_DATA_BITS_R ((volatile uint32_t *)0x40064000) |
| #define GPIO_PORTN_DATA_R (*((volatile uint32_t *)0x400643FC)) |
| #define GPIO_PORTN_DEN_R (*((volatile uint32_t *)0x4006451C)) |
| #define GPIO_PORTN_DIR_R (*((volatile uint32_t *)0x40064400)) |
| #define GPIO_PORTN_DMACTL_R (*((volatile uint32_t *)0x40064534)) |
| #define GPIO_PORTN_DR2R_R (*((volatile uint32_t *)0x40064500)) |
| #define GPIO_PORTN_DR4R_R (*((volatile uint32_t *)0x40064504)) |
| #define GPIO_PORTN_DR8R_R (*((volatile uint32_t *)0x40064508)) |
| #define GPIO_PORTN_IBE_R (*((volatile uint32_t *)0x40064408)) |
| #define GPIO_PORTN_ICR_R (*((volatile uint32_t *)0x4006441C)) |
| #define GPIO_PORTN_IEV_R (*((volatile uint32_t *)0x4006440C)) |
| #define GPIO_PORTN_IM_R (*((volatile uint32_t *)0x40064410)) |
| #define GPIO_PORTN_IS_R (*((volatile uint32_t *)0x40064404)) |
| #define GPIO_PORTN_LOCK_R (*((volatile uint32_t *)0x40064520)) |
| #define GPIO_PORTN_MIS_R (*((volatile uint32_t *)0x40064418)) |
| #define GPIO_PORTN_ODR_R (*((volatile uint32_t *)0x4006450C)) |
| #define GPIO_PORTN_PCTL_R (*((volatile uint32_t *)0x4006452C)) |
| #define GPIO_PORTN_PDR_R (*((volatile uint32_t *)0x40064514)) |
| #define GPIO_PORTN_PUR_R (*((volatile uint32_t *)0x40064510)) |
| #define GPIO_PORTN_RIS_R (*((volatile uint32_t *)0x40064414)) |
| #define GPIO_PORTN_SI_R (*((volatile uint32_t *)0x40064538)) |
| #define GPIO_PORTN_SLR_R (*((volatile uint32_t *)0x40064518)) |
| #define GPIO_PORTP_ADCCTL_R (*((volatile uint32_t *)0x40065530)) |
| #define GPIO_PORTP_AFSEL_R (*((volatile uint32_t *)0x40065420)) |
| #define GPIO_PORTP_AMSEL_R (*((volatile uint32_t *)0x40065528)) |
| #define GPIO_PORTP_CR_R (*((volatile uint32_t *)0x40065524)) |
| #define GPIO_PORTP_DATA_BITS_R ((volatile uint32_t *)0x40065000) |
| #define GPIO_PORTP_DATA_R (*((volatile uint32_t *)0x400653FC)) |
| #define GPIO_PORTP_DEN_R (*((volatile uint32_t *)0x4006551C)) |
| #define GPIO_PORTP_DIR_R (*((volatile uint32_t *)0x40065400)) |
| #define GPIO_PORTP_DMACTL_R (*((volatile uint32_t *)0x40065534)) |
| #define GPIO_PORTP_DR2R_R (*((volatile uint32_t *)0x40065500)) |
| #define GPIO_PORTP_DR4R_R (*((volatile uint32_t *)0x40065504)) |
| #define GPIO_PORTP_DR8R_R (*((volatile uint32_t *)0x40065508)) |
| #define GPIO_PORTP_IBE_R (*((volatile uint32_t *)0x40065408)) |
| #define GPIO_PORTP_ICR_R (*((volatile uint32_t *)0x4006541C)) |
| #define GPIO_PORTP_IEV_R (*((volatile uint32_t *)0x4006540C)) |
| #define GPIO_PORTP_IM_R (*((volatile uint32_t *)0x40065410)) |
| #define GPIO_PORTP_IS_R (*((volatile uint32_t *)0x40065404)) |
| #define GPIO_PORTP_LOCK_R (*((volatile uint32_t *)0x40065520)) |
| #define GPIO_PORTP_MIS_R (*((volatile uint32_t *)0x40065418)) |
| #define GPIO_PORTP_ODR_R (*((volatile uint32_t *)0x4006550C)) |
| #define GPIO_PORTP_PCTL_R (*((volatile uint32_t *)0x4006552C)) |
| #define GPIO_PORTP_PDR_R (*((volatile uint32_t *)0x40065514)) |
| #define GPIO_PORTP_PUR_R (*((volatile uint32_t *)0x40065510)) |
| #define GPIO_PORTP_RIS_R (*((volatile uint32_t *)0x40065414)) |
| #define GPIO_PORTP_SI_R (*((volatile uint32_t *)0x40065538)) |
| #define GPIO_PORTP_SLR_R (*((volatile uint32_t *)0x40065518)) |
| #define GPIO_RIS_GPIO_M 0x000000FF |
| #define GPIO_RIS_GPIO_S 0 |
| #define GPIO_SI_SUM 0x00000001 |
| #define HIB_CTL_BATCHK 0x00000400 |
| #define HIB_CTL_BATWKEN 0x00000200 |
| #define HIB_CTL_CLK32EN 0x00000040 |
| #define HIB_CTL_HIBREQ 0x00000002 |
| #define HIB_CTL_OSCBYP 0x00010000 |
| #define HIB_CTL_OSCDRV 0x00020000 |
| #define HIB_CTL_PINWEN 0x00000010 |
| #define HIB_CTL_R (*((volatile uint32_t *)0x400FC010)) |
| #define HIB_CTL_RTCEN 0x00000001 |
| #define HIB_CTL_RTCWEN 0x00000008 |
| #define HIB_CTL_VABORT 0x00000080 |
| #define HIB_CTL_VBATSEL_1_9V 0x00000000 |
| #define HIB_CTL_VBATSEL_2_1V 0x00002000 |
| #define HIB_CTL_VBATSEL_2_3V 0x00004000 |
| #define HIB_CTL_VBATSEL_2_5V 0x00006000 |
| #define HIB_CTL_VBATSEL_M 0x00006000 |
| #define HIB_CTL_VDD3ON 0x00000100 |
| #define HIB_CTL_WRC 0x80000000 |
| #define HIB_DATA_R (*((volatile uint32_t *)0x400FC030)) |
| #define HIB_DATA_RTD_M 0xFFFFFFFF |
| #define HIB_DATA_RTD_S 0 |
| #define HIB_IC_EXTW 0x00000008 |
| #define HIB_IC_LOWBAT 0x00000004 |
| #define HIB_IC_R (*((volatile uint32_t *)0x400FC020)) |
| #define HIB_IC_RTCALT0 0x00000001 |
| #define HIB_IC_WC 0x00000010 |
| #define HIB_IM_EXTW 0x00000008 |
| #define HIB_IM_LOWBAT 0x00000004 |
| #define HIB_IM_R (*((volatile uint32_t *)0x400FC014)) |
| #define HIB_IM_RTCALT0 0x00000001 |
| #define HIB_IM_WC 0x00000010 |
| #define HIB_MIS_EXTW 0x00000008 |
| #define HIB_MIS_LOWBAT 0x00000004 |
| #define HIB_MIS_R (*((volatile uint32_t *)0x400FC01C)) |
| #define HIB_MIS_RTCALT0 0x00000001 |
| #define HIB_MIS_WC 0x00000010 |
| #define HIB_RIS_EXTW 0x00000008 |
| #define HIB_RIS_LOWBAT 0x00000004 |
| #define HIB_RIS_R (*((volatile uint32_t *)0x400FC018)) |
| #define HIB_RIS_RTCALT0 0x00000001 |
| #define HIB_RIS_WC 0x00000010 |
| #define HIB_RTCC_M 0xFFFFFFFF |
| #define HIB_RTCC_R (*((volatile uint32_t *)0x400FC000)) |
| #define HIB_RTCC_S 0 |
| #define HIB_RTCLD_M 0xFFFFFFFF |
| #define HIB_RTCLD_R (*((volatile uint32_t *)0x400FC00C)) |
| #define HIB_RTCLD_S 0 |
| #define HIB_RTCM0_M 0xFFFFFFFF |
| #define HIB_RTCM0_R (*((volatile uint32_t *)0x400FC004)) |
| #define HIB_RTCM0_S 0 |
| #define HIB_RTCSS_R (*((volatile uint32_t *)0x400FC028)) |
| #define HIB_RTCSS_RTCSSC_M 0x00007FFF |
| #define HIB_RTCSS_RTCSSC_S 0 |
| #define HIB_RTCSS_RTCSSM_M 0x7FFF0000 |
| #define HIB_RTCSS_RTCSSM_S 16 |
| #define HIB_RTCT_R (*((volatile uint32_t *)0x400FC024)) |
| #define HIB_RTCT_TRIM_M 0x0000FFFF |
| #define HIB_RTCT_TRIM_S 0 |
| #define I2C0_MBMON_R (*((volatile uint32_t *)0x4002002C)) |
| #define I2C0_MCLKOCNT_R (*((volatile uint32_t *)0x40020024)) |
| #define I2C0_MCR2_R (*((volatile uint32_t *)0x40020038)) |
| #define I2C0_MCR_R (*((volatile uint32_t *)0x40020020)) |
| #define I2C0_MCS_R (*((volatile uint32_t *)0x40020004)) |
| #define I2C0_MDR_R (*((volatile uint32_t *)0x40020008)) |
| #define I2C0_MICR_R (*((volatile uint32_t *)0x4002001C)) |
| #define I2C0_MIMR_R (*((volatile uint32_t *)0x40020010)) |
| #define I2C0_MMIS_R (*((volatile uint32_t *)0x40020018)) |
| #define I2C0_MRIS_R (*((volatile uint32_t *)0x40020014)) |
| #define I2C0_MSA_R (*((volatile uint32_t *)0x40020000)) |
| #define I2C0_MTPR_R (*((volatile uint32_t *)0x4002000C)) |
| #define I2C0_PC_R (*((volatile uint32_t *)0x40020FC4)) |
| #define I2C0_PP_R (*((volatile uint32_t *)0x40020FC0)) |
| #define I2C0_SACKCTL_R (*((volatile uint32_t *)0x40020820)) |
| #define I2C0_SCSR_R (*((volatile uint32_t *)0x40020804)) |
| #define I2C0_SDR_R (*((volatile uint32_t *)0x40020808)) |
| #define I2C0_SICR_R (*((volatile uint32_t *)0x40020818)) |
| #define I2C0_SIMR_R (*((volatile uint32_t *)0x4002080C)) |
| #define I2C0_SMIS_R (*((volatile uint32_t *)0x40020814)) |
| #define I2C0_SOAR2_R (*((volatile uint32_t *)0x4002081C)) |
| #define I2C0_SOAR_R (*((volatile uint32_t *)0x40020800)) |
| #define I2C0_SRIS_R (*((volatile uint32_t *)0x40020810)) |
| #define I2C1_MBMON_R (*((volatile uint32_t *)0x4002102C)) |
| #define I2C1_MCLKOCNT_R (*((volatile uint32_t *)0x40021024)) |
| #define I2C1_MCR2_R (*((volatile uint32_t *)0x40021038)) |
| #define I2C1_MCR_R (*((volatile uint32_t *)0x40021020)) |
| #define I2C1_MCS_R (*((volatile uint32_t *)0x40021004)) |
| #define I2C1_MDR_R (*((volatile uint32_t *)0x40021008)) |
| #define I2C1_MICR_R (*((volatile uint32_t *)0x4002101C)) |
| #define I2C1_MIMR_R (*((volatile uint32_t *)0x40021010)) |
| #define I2C1_MMIS_R (*((volatile uint32_t *)0x40021018)) |
| #define I2C1_MRIS_R (*((volatile uint32_t *)0x40021014)) |
| #define I2C1_MSA_R (*((volatile uint32_t *)0x40021000)) |
| #define I2C1_MTPR_R (*((volatile uint32_t *)0x4002100C)) |
| #define I2C1_PC_R (*((volatile uint32_t *)0x40021FC4)) |
| #define I2C1_PP_R (*((volatile uint32_t *)0x40021FC0)) |
| #define I2C1_SACKCTL_R (*((volatile uint32_t *)0x40021820)) |
| #define I2C1_SCSR_R (*((volatile uint32_t *)0x40021804)) |
| #define I2C1_SDR_R (*((volatile uint32_t *)0x40021808)) |
| #define I2C1_SICR_R (*((volatile uint32_t *)0x40021818)) |
| #define I2C1_SIMR_R (*((volatile uint32_t *)0x4002180C)) |
| #define I2C1_SMIS_R (*((volatile uint32_t *)0x40021814)) |
| #define I2C1_SOAR2_R (*((volatile uint32_t *)0x4002181C)) |
| #define I2C1_SOAR_R (*((volatile uint32_t *)0x40021800)) |
| #define I2C1_SRIS_R (*((volatile uint32_t *)0x40021810)) |
| #define I2C2_MBMON_R (*((volatile uint32_t *)0x4002202C)) |
| #define I2C2_MCLKOCNT_R (*((volatile uint32_t *)0x40022024)) |
| #define I2C2_MCR2_R (*((volatile uint32_t *)0x40022038)) |
| #define I2C2_MCR_R (*((volatile uint32_t *)0x40022020)) |
| #define I2C2_MCS_R (*((volatile uint32_t *)0x40022004)) |
| #define I2C2_MDR_R (*((volatile uint32_t *)0x40022008)) |
| #define I2C2_MICR_R (*((volatile uint32_t *)0x4002201C)) |
| #define I2C2_MIMR_R (*((volatile uint32_t *)0x40022010)) |
| #define I2C2_MMIS_R (*((volatile uint32_t *)0x40022018)) |
| #define I2C2_MRIS_R (*((volatile uint32_t *)0x40022014)) |
| #define I2C2_MSA_R (*((volatile uint32_t *)0x40022000)) |
| #define I2C2_MTPR_R (*((volatile uint32_t *)0x4002200C)) |
| #define I2C2_PC_R (*((volatile uint32_t *)0x40022FC4)) |
| #define I2C2_PP_R (*((volatile uint32_t *)0x40022FC0)) |
| #define I2C2_SACKCTL_R (*((volatile uint32_t *)0x40022820)) |
| #define I2C2_SCSR_R (*((volatile uint32_t *)0x40022804)) |
| #define I2C2_SDR_R (*((volatile uint32_t *)0x40022808)) |
| #define I2C2_SICR_R (*((volatile uint32_t *)0x40022818)) |
| #define I2C2_SIMR_R (*((volatile uint32_t *)0x4002280C)) |
| #define I2C2_SMIS_R (*((volatile uint32_t *)0x40022814)) |
| #define I2C2_SOAR2_R (*((volatile uint32_t *)0x4002281C)) |
| #define I2C2_SOAR_R (*((volatile uint32_t *)0x40022800)) |
| #define I2C2_SRIS_R (*((volatile uint32_t *)0x40022810)) |
| #define I2C3_MBMON_R (*((volatile uint32_t *)0x4002302C)) |
| #define I2C3_MCLKOCNT_R (*((volatile uint32_t *)0x40023024)) |
| #define I2C3_MCR2_R (*((volatile uint32_t *)0x40023038)) |
| #define I2C3_MCR_R (*((volatile uint32_t *)0x40023020)) |
| #define I2C3_MCS_R (*((volatile uint32_t *)0x40023004)) |
| #define I2C3_MDR_R (*((volatile uint32_t *)0x40023008)) |
| #define I2C3_MICR_R (*((volatile uint32_t *)0x4002301C)) |
| #define I2C3_MIMR_R (*((volatile uint32_t *)0x40023010)) |
| #define I2C3_MMIS_R (*((volatile uint32_t *)0x40023018)) |
| #define I2C3_MRIS_R (*((volatile uint32_t *)0x40023014)) |
| #define I2C3_MSA_R (*((volatile uint32_t *)0x40023000)) |
| #define I2C3_MTPR_R (*((volatile uint32_t *)0x4002300C)) |
| #define I2C3_PC_R (*((volatile uint32_t *)0x40023FC4)) |
| #define I2C3_PP_R (*((volatile uint32_t *)0x40023FC0)) |
| #define I2C3_SACKCTL_R (*((volatile uint32_t *)0x40023820)) |
| #define I2C3_SCSR_R (*((volatile uint32_t *)0x40023804)) |
| #define I2C3_SDR_R (*((volatile uint32_t *)0x40023808)) |
| #define I2C3_SICR_R (*((volatile uint32_t *)0x40023818)) |
| #define I2C3_SIMR_R (*((volatile uint32_t *)0x4002380C)) |
| #define I2C3_SMIS_R (*((volatile uint32_t *)0x40023814)) |
| #define I2C3_SOAR2_R (*((volatile uint32_t *)0x4002381C)) |
| #define I2C3_SOAR_R (*((volatile uint32_t *)0x40023800)) |
| #define I2C3_SRIS_R (*((volatile uint32_t *)0x40023810)) |
| #define I2C4_MBMON_R (*((volatile uint32_t *)0x400C002C)) |
| #define I2C4_MCLKOCNT_R (*((volatile uint32_t *)0x400C0024)) |
| #define I2C4_MCR2_R (*((volatile uint32_t *)0x400C0038)) |
| #define I2C4_MCR_R (*((volatile uint32_t *)0x400C0020)) |
| #define I2C4_MCS_R (*((volatile uint32_t *)0x400C0004)) |
| #define I2C4_MDR_R (*((volatile uint32_t *)0x400C0008)) |
| #define I2C4_MICR_R (*((volatile uint32_t *)0x400C001C)) |
| #define I2C4_MIMR_R (*((volatile uint32_t *)0x400C0010)) |
| #define I2C4_MMIS_R (*((volatile uint32_t *)0x400C0018)) |
| #define I2C4_MRIS_R (*((volatile uint32_t *)0x400C0014)) |
| #define I2C4_MSA_R (*((volatile uint32_t *)0x400C0000)) |
| #define I2C4_MTPR_R (*((volatile uint32_t *)0x400C000C)) |
| #define I2C4_PC_R (*((volatile uint32_t *)0x400C0FC4)) |
| #define I2C4_PP_R (*((volatile uint32_t *)0x400C0FC0)) |
| #define I2C4_SACKCTL_R (*((volatile uint32_t *)0x400C0820)) |
| #define I2C4_SCSR_R (*((volatile uint32_t *)0x400C0804)) |
| #define I2C4_SDR_R (*((volatile uint32_t *)0x400C0808)) |
| #define I2C4_SICR_R (*((volatile uint32_t *)0x400C0818)) |
| #define I2C4_SIMR_R (*((volatile uint32_t *)0x400C080C)) |
| #define I2C4_SMIS_R (*((volatile uint32_t *)0x400C0814)) |
| #define I2C4_SOAR2_R (*((volatile uint32_t *)0x400C081C)) |
| #define I2C4_SOAR_R (*((volatile uint32_t *)0x400C0800)) |
| #define I2C4_SRIS_R (*((volatile uint32_t *)0x400C0810)) |
| #define I2C5_MBMON_R (*((volatile uint32_t *)0x400C102C)) |
| #define I2C5_MCLKOCNT_R (*((volatile uint32_t *)0x400C1024)) |
| #define I2C5_MCR2_R (*((volatile uint32_t *)0x400C1038)) |
| #define I2C5_MCR_R (*((volatile uint32_t *)0x400C1020)) |
| #define I2C5_MCS_R (*((volatile uint32_t *)0x400C1004)) |
| #define I2C5_MDR_R (*((volatile uint32_t *)0x400C1008)) |
| #define I2C5_MICR_R (*((volatile uint32_t *)0x400C101C)) |
| #define I2C5_MIMR_R (*((volatile uint32_t *)0x400C1010)) |
| #define I2C5_MMIS_R (*((volatile uint32_t *)0x400C1018)) |
| #define I2C5_MRIS_R (*((volatile uint32_t *)0x400C1014)) |
| #define I2C5_MSA_R (*((volatile uint32_t *)0x400C1000)) |
| #define I2C5_MTPR_R (*((volatile uint32_t *)0x400C100C)) |
| #define I2C5_PC_R (*((volatile uint32_t *)0x400C1FC4)) |
| #define I2C5_PP_R (*((volatile uint32_t *)0x400C1FC0)) |
| #define I2C5_SACKCTL_R (*((volatile uint32_t *)0x400C1820)) |
| #define I2C5_SCSR_R (*((volatile uint32_t *)0x400C1804)) |
| #define I2C5_SDR_R (*((volatile uint32_t *)0x400C1808)) |
| #define I2C5_SICR_R (*((volatile uint32_t *)0x400C1818)) |
| #define I2C5_SIMR_R (*((volatile uint32_t *)0x400C180C)) |
| #define I2C5_SMIS_R (*((volatile uint32_t *)0x400C1814)) |
| #define I2C5_SOAR2_R (*((volatile uint32_t *)0x400C181C)) |
| #define I2C5_SOAR_R (*((volatile uint32_t *)0x400C1800)) |
| #define I2C5_SRIS_R (*((volatile uint32_t *)0x400C1810)) |
| #define I2C_MBMON_SCL 0x00000001 |
| #define I2C_MBMON_SDA 0x00000002 |
| #define I2C_MCLKOCNT_CNTL_M 0x000000FF |
| #define I2C_MCLKOCNT_CNTL_S 0 |
| #define I2C_MCR2_GFPW_1 0x00000010 |
| #define I2C_MCR2_GFPW_16 0x00000060 |
| #define I2C_MCR2_GFPW_2 0x00000020 |
| #define I2C_MCR2_GFPW_3 0x00000030 |
| #define I2C_MCR2_GFPW_31 0x00000070 |
| #define I2C_MCR2_GFPW_4 0x00000040 |
| #define I2C_MCR2_GFPW_8 0x00000050 |
| #define I2C_MCR2_GFPW_BYPASS 0x00000000 |
| #define I2C_MCR2_GFPW_M 0x00000070 |
| #define I2C_MCR_GFE 0x00000040 |
| #define I2C_MCR_LPBK 0x00000001 |
| #define I2C_MCR_MFE 0x00000010 |
| #define I2C_MCR_SFE 0x00000020 |
| #define I2C_MCS_ACK 0x00000008 |
| #define I2C_MCS_ADRACK 0x00000004 |
| #define I2C_MCS_ARBLST 0x00000010 |
| #define I2C_MCS_BUSBSY 0x00000040 |
| #define I2C_MCS_BUSY 0x00000001 |
| #define I2C_MCS_CLKTO 0x00000080 |
| #define I2C_MCS_DATACK 0x00000008 |
| #define I2C_MCS_ERROR 0x00000002 |
| #define I2C_MCS_HS 0x00000010 |
| #define I2C_MCS_IDLE 0x00000020 |
| #define I2C_MCS_RUN 0x00000001 |
| #define I2C_MCS_START 0x00000002 |
| #define I2C_MCS_STOP 0x00000004 |
| #define I2C_MDR_DATA_M 0x000000FF |
| #define I2C_MDR_DATA_S 0 |
| #define I2C_MICR_CLKIC 0x00000002 |
| #define I2C_MICR_IC 0x00000001 |
| #define I2C_MIMR_CLKIM 0x00000002 |
| #define I2C_MIMR_IM 0x00000001 |
| #define I2C_MMIS_CLKMIS 0x00000002 |
| #define I2C_MMIS_MIS 0x00000001 |
| #define I2C_MRIS_CLKRIS 0x00000002 |
| #define I2C_MRIS_RIS 0x00000001 |
| #define I2C_MSA_RS 0x00000001 |
| #define I2C_MSA_SA_M 0x000000FE |
| #define I2C_MSA_SA_S 1 |
| #define I2C_MTPR_HS 0x00000080 |
| #define I2C_MTPR_TPR_M 0x0000007F |
| #define I2C_MTPR_TPR_S 0 |
| #define I2C_PC_HS 0x00000001 |
| #define I2C_PP_HS 0x00000001 |
| #define I2C_SACKCTL_ACKOEN 0x00000001 |
| #define I2C_SACKCTL_ACKOVAL 0x00000002 |
| #define I2C_SCSR_DA 0x00000001 |
| #define I2C_SCSR_FBR 0x00000004 |
| #define I2C_SCSR_OAR2SEL 0x00000008 |
| #define I2C_SCSR_RREQ 0x00000001 |
| #define I2C_SCSR_TREQ 0x00000002 |
| #define I2C_SDR_DATA_M 0x000000FF |
| #define I2C_SDR_DATA_S 0 |
| #define I2C_SICR_DATAIC 0x00000001 |
| #define I2C_SICR_STARTIC 0x00000002 |
| #define I2C_SICR_STOPIC 0x00000004 |
| #define I2C_SIMR_DATAIM 0x00000001 |
| #define I2C_SIMR_STARTIM 0x00000002 |
| #define I2C_SIMR_STOPIM 0x00000004 |
| #define I2C_SMIS_DATAMIS 0x00000001 |
| #define I2C_SMIS_STARTMIS 0x00000002 |
| #define I2C_SMIS_STOPMIS 0x00000004 |
| #define I2C_SOAR2_OAR2_M 0x0000007F |
| #define I2C_SOAR2_OAR2_S 0 |
| #define I2C_SOAR2_OAR2EN 0x00000080 |
| #define I2C_SOAR_OAR_M 0x0000007F |
| #define I2C_SOAR_OAR_S 0 |
| #define I2C_SRIS_DATARIS 0x00000001 |
| #define I2C_SRIS_STARTRIS 0x00000002 |
| #define I2C_SRIS_STOPRIS 0x00000004 |
| #define INT_ADC0SS0 30 |
| #define INT_ADC0SS1 31 |
| #define INT_ADC0SS2 32 |
| #define INT_ADC0SS3 33 |
| #define INT_ADC1SS0 64 |
| #define INT_ADC1SS1 65 |
| #define INT_ADC1SS2 66 |
| #define INT_ADC1SS3 67 |
| #define INT_CAN0 55 |
| #define INT_CAN1 56 |
| #define INT_COMP0 41 |
| #define INT_COMP1 42 |
| #define INT_COMP2 43 |
| #define INT_FLASH 45 |
| #define INT_GPIOA 16 |
| #define INT_GPIOB 17 |
| #define INT_GPIOC 18 |
| #define INT_GPIOD 19 |
| #define INT_GPIOE 20 |
| #define INT_GPIOF 46 |
| #define INT_GPIOG 47 |
| #define INT_GPIOH 48 |
| #define INT_GPIOJ 70 |
| #define INT_GPIOK 71 |
| #define INT_GPIOL 72 |
| #define INT_GPIOM 127 |
| #define INT_GPION 128 |
| #define INT_GPIOP0 132 |
| #define INT_GPIOP1 133 |
| #define INT_GPIOP2 134 |
| #define INT_GPIOP3 135 |
| #define INT_GPIOP4 136 |
| #define INT_GPIOP5 137 |
| #define INT_GPIOP6 138 |
| #define INT_GPIOP7 139 |
| #define INT_HIBERNATE 59 |
| #define INT_I2C0 24 |
| #define INT_I2C1 53 |
| #define INT_I2C2 84 |
| #define INT_I2C3 85 |
| #define INT_I2C4 125 |
| #define INT_I2C5 126 |
| #define INT_PWM0_0 26 |
| #define INT_PWM0_1 27 |
| #define INT_PWM0_2 28 |
| #define INT_PWM0_3 61 |
| #define INT_PWM0_FAULT 25 |
| #define INT_PWM1_0 150 |
| #define INT_PWM1_1 151 |
| #define INT_PWM1_2 152 |
| #define INT_PWM1_3 153 |
| #define INT_PWM1_FAULT 154 |
| #define INT_QEI0 29 |
| #define INT_QEI1 54 |
| #define INT_SSI0 23 |
| #define INT_SSI1 50 |
| #define INT_SSI2 73 |
| #define INT_SSI3 74 |
| #define INT_SYSCTL 44 |
| #define INT_SYSEXC 122 |
| #define INT_TIMER0A 35 |
| #define INT_TIMER0B 36 |
| #define INT_TIMER1A 37 |
| #define INT_TIMER1B 38 |
| #define INT_TIMER2A 39 |
| #define INT_TIMER2B 40 |
| #define INT_TIMER3A 51 |
| #define INT_TIMER3B 52 |
| #define INT_TIMER4A 86 |
| #define INT_TIMER4B 87 |
| #define INT_TIMER5A 108 |
| #define INT_TIMER5B 109 |
| #define INT_UART0 21 |
| #define INT_UART1 22 |
| #define INT_UART2 49 |
| #define INT_UART3 75 |
| #define INT_UART4 76 |
| #define INT_UART5 77 |
| #define INT_UART6 78 |
| #define INT_UART7 79 |
| #define INT_UDMA 62 |
| #define INT_UDMAERR 63 |
| #define INT_USB0 60 |
| #define INT_WATCHDOG 34 |
| #define INT_WTIMER0A 110 |
| #define INT_WTIMER0B 111 |
| #define INT_WTIMER1A 112 |
| #define INT_WTIMER1B 113 |
| #define INT_WTIMER2A 114 |
| #define INT_WTIMER2B 115 |
| #define INT_WTIMER3A 116 |
| #define INT_WTIMER3B 117 |
| #define INT_WTIMER4A 118 |
| #define INT_WTIMER4B 119 |
| #define INT_WTIMER5A 120 |
| #define INT_WTIMER5B 121 |
| #define NVIC_ACTIVE0_INT_M 0xFFFFFFFF |
| #define NVIC_ACTIVE0_R (*((volatile uint32_t *)0xE000E300)) |
| #define NVIC_ACTIVE1_INT_M 0xFFFFFFFF |
| #define NVIC_ACTIVE1_R (*((volatile uint32_t *)0xE000E304)) |
| #define NVIC_ACTIVE2_INT_M 0xFFFFFFFF |
| #define NVIC_ACTIVE2_R (*((volatile uint32_t *)0xE000E308)) |
| #define NVIC_ACTIVE3_INT_M 0xFFFFFFFF |
| #define NVIC_ACTIVE3_R (*((volatile uint32_t *)0xE000E30C)) |
| #define NVIC_ACTIVE4_INT_M 0x000007FF |
| #define NVIC_ACTIVE4_R (*((volatile uint32_t *)0xE000E310)) |
| #define NVIC_ACTLR_DISFOLD 0x00000004 |
| #define NVIC_ACTLR_DISFPCA 0x00000100 |
| #define NVIC_ACTLR_DISMCYC 0x00000001 |
| #define NVIC_ACTLR_DISOOFP 0x00000200 |
| #define NVIC_ACTLR_DISWBUF 0x00000002 |
| #define NVIC_ACTLR_R (*((volatile uint32_t *)0xE000E008)) |
| #define NVIC_APINT_ENDIANESS 0x00008000 |
| #define NVIC_APINT_PRIGROUP_0_8 0x00000700 |
| #define NVIC_APINT_PRIGROUP_1_7 0x00000600 |
| #define NVIC_APINT_PRIGROUP_2_6 0x00000500 |
| #define NVIC_APINT_PRIGROUP_3_5 0x00000400 |
| #define NVIC_APINT_PRIGROUP_4_4 0x00000300 |
| #define NVIC_APINT_PRIGROUP_5_3 0x00000200 |
| #define NVIC_APINT_PRIGROUP_6_2 0x00000100 |
| #define NVIC_APINT_PRIGROUP_7_1 0x00000000 |
| #define NVIC_APINT_PRIGROUP_M 0x00000700 |
| #define NVIC_APINT_R (*((volatile uint32_t *)0xE000ED0C)) |
| #define NVIC_APINT_SYSRESETREQ 0x00000004 |
| #define NVIC_APINT_VECT_CLR_ACT 0x00000002 |
| #define NVIC_APINT_VECT_RESET 0x00000001 |
| #define NVIC_APINT_VECTKEY 0x05FA0000 |
| #define NVIC_APINT_VECTKEY_M 0xFFFF0000 |
| #define NVIC_CFG_CTRL_BASE_THR 0x00000001 |
| #define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 |
| #define NVIC_CFG_CTRL_DIV0 0x00000010 |
| #define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 |
| #define NVIC_CFG_CTRL_R (*((volatile uint32_t *)0xE000ED14)) |
| #define NVIC_CFG_CTRL_STKALIGN 0x00000200 |
| #define NVIC_CFG_CTRL_UNALIGNED 0x00000008 |
| #define NVIC_CPAC_CP10_DIS 0x00000000 |
| #define NVIC_CPAC_CP10_FULL 0x00300000 |
| #define NVIC_CPAC_CP10_M 0x00300000 |
| #define NVIC_CPAC_CP10_PRIV 0x00100000 |
| #define NVIC_CPAC_CP11_DIS 0x00000000 |
| #define NVIC_CPAC_CP11_FULL 0x00C00000 |
| #define NVIC_CPAC_CP11_M 0x00C00000 |
| #define NVIC_CPAC_CP11_PRIV 0x00400000 |
| #define NVIC_CPAC_R (*((volatile uint32_t *)0xE000ED88)) |
| #define NVIC_CPUID_CON_M 0x000F0000 |
| #define NVIC_CPUID_IMP_ARM 0x41000000 |
| #define NVIC_CPUID_IMP_M 0xFF000000 |
| #define NVIC_CPUID_PARTNO_CM4 0x0000C240 |
| #define NVIC_CPUID_PARTNO_M 0x0000FFF0 |
| #define NVIC_CPUID_R (*((volatile uint32_t *)0xE000ED00)) |
| #define NVIC_CPUID_REV_M 0x0000000F |
| #define NVIC_CPUID_VAR_M 0x00F00000 |
| #define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 |
| #define NVIC_DBG_CTRL_C_HALT 0x00000002 |
| #define NVIC_DBG_CTRL_C_MASKINT 0x00000008 |
| #define NVIC_DBG_CTRL_C_SNAPSTALL 0x00000020 |
| #define NVIC_DBG_CTRL_C_STEP 0x00000004 |
| #define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 |
| #define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 |
| #define NVIC_DBG_CTRL_R (*((volatile uint32_t *)0xE000EDF0)) |
| #define NVIC_DBG_CTRL_S_HALT 0x00020000 |
| #define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 |
| #define NVIC_DBG_CTRL_S_REGRDY 0x00010000 |
| #define NVIC_DBG_CTRL_S_RESET_ST 0x02000000 |
| #define NVIC_DBG_CTRL_S_RETIRE_ST 0x01000000 |
| #define NVIC_DBG_CTRL_S_SLEEP 0x00040000 |
| #define NVIC_DBG_DATA_M 0xFFFFFFFF |
| #define NVIC_DBG_DATA_R (*((volatile uint32_t *)0xE000EDF8)) |
| #define NVIC_DBG_DATA_S 0 |
| #define NVIC_DBG_INT_BUSERR 0x00000100 |
| #define NVIC_DBG_INT_CHKERR 0x00000040 |
| #define NVIC_DBG_INT_HARDERR 0x00000400 |
| #define NVIC_DBG_INT_INTERR 0x00000200 |
| #define NVIC_DBG_INT_MMERR 0x00000010 |
| #define NVIC_DBG_INT_NOCPERR 0x00000020 |
| #define NVIC_DBG_INT_R (*((volatile uint32_t *)0xE000EDFC)) |
| #define NVIC_DBG_INT_RESET 0x00000008 |
| #define NVIC_DBG_INT_RSTPENDCLR 0x00000004 |
| #define NVIC_DBG_INT_RSTPENDING 0x00000002 |
| #define NVIC_DBG_INT_RSTVCATCH 0x00000001 |
| #define NVIC_DBG_INT_STATERR 0x00000080 |
| #define NVIC_DBG_XFER_R (*((volatile uint32_t *)0xE000EDF4)) |
| #define NVIC_DBG_XFER_REG_CFBP 0x00000014 |
| #define NVIC_DBG_XFER_REG_DSP 0x00000013 |
| #define NVIC_DBG_XFER_REG_FLAGS 0x00000010 |
| #define NVIC_DBG_XFER_REG_MSP 0x00000011 |
| #define NVIC_DBG_XFER_REG_PSP 0x00000012 |
| #define NVIC_DBG_XFER_REG_R0 0x00000000 |
| #define NVIC_DBG_XFER_REG_R1 0x00000001 |
| #define NVIC_DBG_XFER_REG_R10 0x0000000A |
| #define NVIC_DBG_XFER_REG_R11 0x0000000B |
| #define NVIC_DBG_XFER_REG_R12 0x0000000C |
| #define NVIC_DBG_XFER_REG_R13 0x0000000D |
| #define NVIC_DBG_XFER_REG_R14 0x0000000E |
| #define NVIC_DBG_XFER_REG_R15 0x0000000F |
| #define NVIC_DBG_XFER_REG_R2 0x00000002 |
| #define NVIC_DBG_XFER_REG_R3 0x00000003 |
| #define NVIC_DBG_XFER_REG_R4 0x00000004 |
| #define NVIC_DBG_XFER_REG_R5 0x00000005 |
| #define NVIC_DBG_XFER_REG_R6 0x00000006 |
| #define NVIC_DBG_XFER_REG_R7 0x00000007 |
| #define NVIC_DBG_XFER_REG_R8 0x00000008 |
| #define NVIC_DBG_XFER_REG_R9 0x00000009 |
| #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F |
| #define NVIC_DBG_XFER_REG_WNR 0x00010000 |
| #define NVIC_DEBUG_STAT_BKPT 0x00000002 |
| #define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 |
| #define NVIC_DEBUG_STAT_EXTRNL 0x00000010 |
| #define NVIC_DEBUG_STAT_HALTED 0x00000001 |
| #define NVIC_DEBUG_STAT_R (*((volatile uint32_t *)0xE000ED30)) |
| #define NVIC_DEBUG_STAT_VCATCH 0x00000008 |
| #define NVIC_DIS0_INT_M 0xFFFFFFFF |
| #define NVIC_DIS0_R (*((volatile uint32_t *)0xE000E180)) |
| #define NVIC_DIS1_INT_M 0xFFFFFFFF |
| #define NVIC_DIS1_R (*((volatile uint32_t *)0xE000E184)) |
| #define NVIC_DIS2_INT_M 0xFFFFFFFF |
| #define NVIC_DIS2_R (*((volatile uint32_t *)0xE000E188)) |
| #define NVIC_DIS3_INT_M 0xFFFFFFFF |
| #define NVIC_DIS3_R (*((volatile uint32_t *)0xE000E18C)) |
| #define NVIC_DIS4_INT_M 0x000007FF |
| #define NVIC_DIS4_R (*((volatile uint32_t *)0xE000E190)) |
| #define NVIC_EN0_INT_M 0xFFFFFFFF |
| #define NVIC_EN0_R (*((volatile uint32_t *)0xE000E100)) |
| #define NVIC_EN1_INT_M 0xFFFFFFFF |
| #define NVIC_EN1_R (*((volatile uint32_t *)0xE000E104)) |
| #define NVIC_EN2_INT_M 0xFFFFFFFF |
| #define NVIC_EN2_R (*((volatile uint32_t *)0xE000E108)) |
| #define NVIC_EN3_INT_M 0xFFFFFFFF |
| #define NVIC_EN3_R (*((volatile uint32_t *)0xE000E10C)) |
| #define NVIC_EN4_INT_M 0x000007FF |
| #define NVIC_EN4_R (*((volatile uint32_t *)0xE000E110)) |
| #define NVIC_FAULT_ADDR_M 0xFFFFFFFF |
| #define NVIC_FAULT_ADDR_R (*((volatile uint32_t *)0xE000ED38)) |
| #define NVIC_FAULT_ADDR_S 0 |
| #define NVIC_FAULT_STAT_BFARV 0x00008000 |
| #define NVIC_FAULT_STAT_BLSPERR 0x00002000 |
| #define NVIC_FAULT_STAT_BSTKE 0x00001000 |
| #define NVIC_FAULT_STAT_BUSTKE 0x00000800 |
| #define NVIC_FAULT_STAT_DERR 0x00000002 |
| #define NVIC_FAULT_STAT_DIV0 0x02000000 |
| #define NVIC_FAULT_STAT_IBUS 0x00000100 |
| #define NVIC_FAULT_STAT_IERR 0x00000001 |
| #define NVIC_FAULT_STAT_IMPRE 0x00000400 |
| #define NVIC_FAULT_STAT_INVPC 0x00040000 |
| #define NVIC_FAULT_STAT_INVSTAT 0x00020000 |
| #define NVIC_FAULT_STAT_MLSPERR 0x00000020 |
| #define NVIC_FAULT_STAT_MMARV 0x00000080 |
| #define NVIC_FAULT_STAT_MSTKE 0x00000010 |
| #define NVIC_FAULT_STAT_MUSTKE 0x00000008 |
| #define NVIC_FAULT_STAT_NOCP 0x00080000 |
| #define NVIC_FAULT_STAT_PRECISE 0x00000200 |
| #define NVIC_FAULT_STAT_R (*((volatile uint32_t *)0xE000ED28)) |
| #define NVIC_FAULT_STAT_UNALIGN 0x01000000 |
| #define NVIC_FAULT_STAT_UNDEF 0x00010000 |
| #define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 |
| #define NVIC_FPCA_ADDRESS_S 3 |
| #define NVIC_FPCA_R (*((volatile uint32_t *)0xE000EF38)) |
| #define NVIC_FPCC_ASPEN 0x80000000 |
| #define NVIC_FPCC_BFRDY 0x00000040 |
| #define NVIC_FPCC_HFRDY 0x00000010 |
| #define NVIC_FPCC_LSPACT 0x00000001 |
| #define NVIC_FPCC_LSPEN 0x40000000 |
| #define NVIC_FPCC_MMRDY 0x00000020 |
| #define NVIC_FPCC_MONRDY 0x00000100 |
| #define NVIC_FPCC_R (*((volatile uint32_t *)0xE000EF34)) |
| #define NVIC_FPCC_THREAD 0x00000008 |
| #define NVIC_FPCC_USER 0x00000002 |
| #define NVIC_FPDSC_AHP 0x04000000 |
| #define NVIC_FPDSC_DN 0x02000000 |
| #define NVIC_FPDSC_FZ 0x01000000 |
| #define NVIC_FPDSC_R (*((volatile uint32_t *)0xE000EF3C)) |
| #define NVIC_FPDSC_RMODE_M 0x00C00000 |
| #define NVIC_FPDSC_RMODE_RM 0x00800000 |
| #define NVIC_FPDSC_RMODE_RN 0x00000000 |
| #define NVIC_FPDSC_RMODE_RP 0x00400000 |
| #define NVIC_FPDSC_RMODE_RZ 0x00C00000 |
| #define NVIC_HFAULT_STAT_DBG 0x80000000 |
| #define NVIC_HFAULT_STAT_FORCED 0x40000000 |
| #define NVIC_HFAULT_STAT_R (*((volatile uint32_t *)0xE000ED2C)) |
| #define NVIC_HFAULT_STAT_VECT 0x00000002 |
| #define NVIC_INT_CTRL_ISR_PEND 0x00400000 |
| #define NVIC_INT_CTRL_ISR_PRE 0x00800000 |
| #define NVIC_INT_CTRL_NMI_SET 0x80000000 |
| #define NVIC_INT_CTRL_PEND_SV 0x10000000 |
| #define NVIC_INT_CTRL_PENDSTCLR 0x02000000 |
| #define NVIC_INT_CTRL_PENDSTSET 0x04000000 |
| #define NVIC_INT_CTRL_R (*((volatile uint32_t *)0xE000ED04)) |
| #define NVIC_INT_CTRL_RET_BASE 0x00000800 |
| #define NVIC_INT_CTRL_UNPEND_SV 0x08000000 |
| #define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF |
| #define NVIC_INT_CTRL_VEC_ACT_S 0 |
| #define NVIC_INT_CTRL_VEC_PEN_BUS 0x00005000 |
| #define NVIC_INT_CTRL_VEC_PEN_HARD 0x00003000 |
| #define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 |
| #define NVIC_INT_CTRL_VEC_PEN_MEM 0x00004000 |
| #define NVIC_INT_CTRL_VEC_PEN_NMI 0x00002000 |
| #define NVIC_INT_CTRL_VEC_PEN_PNDSV 0x0000E000 |
| #define NVIC_INT_CTRL_VEC_PEN_SVC 0x0000B000 |
| #define NVIC_INT_CTRL_VEC_PEN_TICK 0x0000F000 |
| #define NVIC_INT_CTRL_VEC_PEN_USG 0x00006000 |
| #define NVIC_MM_ADDR_M 0xFFFFFFFF |
| #define NVIC_MM_ADDR_R (*((volatile uint32_t *)0xE000ED34)) |
| #define NVIC_MM_ADDR_S 0 |
| #define NVIC_MPU_ATTR1_AP_M 0x07000000 |
| #define NVIC_MPU_ATTR1_BUFFRABLE 0x00010000 |
| #define NVIC_MPU_ATTR1_CACHEABLE 0x00020000 |
| #define NVIC_MPU_ATTR1_ENABLE 0x00000001 |
| #define NVIC_MPU_ATTR1_R (*((volatile uint32_t *)0xE000EDA8)) |
| #define NVIC_MPU_ATTR1_SHAREABLE 0x00040000 |
| #define NVIC_MPU_ATTR1_SIZE_M 0x0000003E |
| #define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 |
| #define NVIC_MPU_ATTR1_TEX_M 0x00380000 |
| #define NVIC_MPU_ATTR1_XN 0x10000000 |
| #define NVIC_MPU_ATTR2_AP_M 0x07000000 |
| #define NVIC_MPU_ATTR2_BUFFRABLE 0x00010000 |
| #define NVIC_MPU_ATTR2_CACHEABLE 0x00020000 |
| #define NVIC_MPU_ATTR2_ENABLE 0x00000001 |
| #define NVIC_MPU_ATTR2_R (*((volatile uint32_t *)0xE000EDB0)) |
| #define NVIC_MPU_ATTR2_SHAREABLE 0x00040000 |
| #define NVIC_MPU_ATTR2_SIZE_M 0x0000003E |
| #define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 |
| #define NVIC_MPU_ATTR2_TEX_M 0x00380000 |
| #define NVIC_MPU_ATTR2_XN 0x10000000 |
| #define NVIC_MPU_ATTR3_AP_M 0x07000000 |
| #define NVIC_MPU_ATTR3_BUFFRABLE 0x00010000 |
| #define NVIC_MPU_ATTR3_CACHEABLE 0x00020000 |
| #define NVIC_MPU_ATTR3_ENABLE 0x00000001 |
| #define NVIC_MPU_ATTR3_R (*((volatile uint32_t *)0xE000EDB8)) |
| #define NVIC_MPU_ATTR3_SHAREABLE 0x00040000 |
| #define NVIC_MPU_ATTR3_SIZE_M 0x0000003E |
| #define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 |
| #define NVIC_MPU_ATTR3_TEX_M 0x00380000 |
| #define NVIC_MPU_ATTR3_XN 0x10000000 |
| #define NVIC_MPU_ATTR_AP_M 0x07000000 |
| #define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 |
| #define NVIC_MPU_ATTR_CACHEABLE 0x00020000 |
| #define NVIC_MPU_ATTR_ENABLE 0x00000001 |
| #define NVIC_MPU_ATTR_R (*((volatile uint32_t *)0xE000EDA0)) |
| #define NVIC_MPU_ATTR_SHAREABLE 0x00040000 |
| #define NVIC_MPU_ATTR_SIZE_M 0x0000003E |
| #define NVIC_MPU_ATTR_SRD_M 0x0000FF00 |
| #define NVIC_MPU_ATTR_TEX_M 0x00380000 |
| #define NVIC_MPU_ATTR_XN 0x10000000 |
| #define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 |
| #define NVIC_MPU_BASE1_ADDR_S 5 |
| #define NVIC_MPU_BASE1_R (*((volatile uint32_t *)0xE000EDA4)) |
| #define NVIC_MPU_BASE1_REGION_M 0x00000007 |
| #define NVIC_MPU_BASE1_REGION_S 0 |
| #define NVIC_MPU_BASE1_VALID 0x00000010 |
| #define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 |
| #define NVIC_MPU_BASE2_ADDR_S 5 |
| #define NVIC_MPU_BASE2_R (*((volatile uint32_t *)0xE000EDAC)) |
| #define NVIC_MPU_BASE2_REGION_M 0x00000007 |
| #define NVIC_MPU_BASE2_REGION_S 0 |
| #define NVIC_MPU_BASE2_VALID 0x00000010 |
| #define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 |
| #define NVIC_MPU_BASE3_ADDR_S 5 |
| #define NVIC_MPU_BASE3_R (*((volatile uint32_t *)0xE000EDB4)) |
| #define NVIC_MPU_BASE3_REGION_M 0x00000007 |
| #define NVIC_MPU_BASE3_REGION_S 0 |
| #define NVIC_MPU_BASE3_VALID 0x00000010 |
| #define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 |
| #define NVIC_MPU_BASE_ADDR_S 5 |
| #define NVIC_MPU_BASE_R (*((volatile uint32_t *)0xE000ED9C)) |
| #define NVIC_MPU_BASE_REGION_M 0x00000007 |
| #define NVIC_MPU_BASE_REGION_S 0 |
| #define NVIC_MPU_BASE_VALID 0x00000010 |
| #define NVIC_MPU_CTRL_ENABLE 0x00000001 |
| #define NVIC_MPU_CTRL_HFNMIENA 0x00000002 |
| #define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 |
| #define NVIC_MPU_CTRL_R (*((volatile uint32_t *)0xE000ED94)) |
| #define NVIC_MPU_NUMBER_M 0x00000007 |
| #define NVIC_MPU_NUMBER_R (*((volatile uint32_t *)0xE000ED98)) |
| #define NVIC_MPU_NUMBER_S 0 |
| #define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 |
| #define NVIC_MPU_TYPE_DREGION_S 8 |
| #define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 |
| #define NVIC_MPU_TYPE_IREGION_S 16 |
| #define NVIC_MPU_TYPE_R (*((volatile uint32_t *)0xE000ED90)) |
| #define NVIC_MPU_TYPE_SEPARATE 0x00000001 |
| #define NVIC_PEND0_INT_M 0xFFFFFFFF |
| #define NVIC_PEND0_R (*((volatile uint32_t *)0xE000E200)) |
| #define NVIC_PEND1_INT_M 0xFFFFFFFF |
| #define NVIC_PEND1_R (*((volatile uint32_t *)0xE000E204)) |
| #define NVIC_PEND2_INT_M 0xFFFFFFFF |
| #define NVIC_PEND2_R (*((volatile uint32_t *)0xE000E208)) |
| #define NVIC_PEND3_INT_M 0xFFFFFFFF |
| #define NVIC_PEND3_R (*((volatile uint32_t *)0xE000E20C)) |
| #define NVIC_PEND4_INT_M 0x000007FF |
| #define NVIC_PEND4_R (*((volatile uint32_t *)0xE000E210)) |
| #define NVIC_PRI0_INT0_M 0x000000E0 |
| #define NVIC_PRI0_INT0_S 5 |
| #define NVIC_PRI0_INT1_M 0x0000E000 |
| #define NVIC_PRI0_INT1_S 13 |
| #define NVIC_PRI0_INT2_M 0x00E00000 |
| #define NVIC_PRI0_INT2_S 21 |
| #define NVIC_PRI0_INT3_M 0xE0000000 |
| #define NVIC_PRI0_INT3_S 29 |
| #define NVIC_PRI0_R (*((volatile uint32_t *)0xE000E400)) |
| #define NVIC_PRI10_INT40_M 0x000000E0 |
| #define NVIC_PRI10_INT40_S 5 |
| #define NVIC_PRI10_INT41_M 0x0000E000 |
| #define NVIC_PRI10_INT41_S 13 |
| #define NVIC_PRI10_INT42_M 0x00E00000 |
| #define NVIC_PRI10_INT42_S 21 |
| #define NVIC_PRI10_INT43_M 0xE0000000 |
| #define NVIC_PRI10_INT43_S 29 |
| #define NVIC_PRI10_R (*((volatile uint32_t *)0xE000E428)) |
| #define NVIC_PRI11_INT44_M 0x000000E0 |
| #define NVIC_PRI11_INT44_S 5 |
| #define NVIC_PRI11_INT45_M 0x0000E000 |
| #define NVIC_PRI11_INT45_S 13 |
| #define NVIC_PRI11_INT46_M 0x00E00000 |
| #define NVIC_PRI11_INT46_S 21 |
| #define NVIC_PRI11_INT47_M 0xE0000000 |
| #define NVIC_PRI11_INT47_S 29 |
| #define NVIC_PRI11_R (*((volatile uint32_t *)0xE000E42C)) |
| #define NVIC_PRI12_INT48_M 0x000000E0 |
| #define NVIC_PRI12_INT48_S 5 |
| #define NVIC_PRI12_INT49_M 0x0000E000 |
| #define NVIC_PRI12_INT49_S 13 |
| #define NVIC_PRI12_INT50_M 0x00E00000 |
| #define NVIC_PRI12_INT50_S 21 |
| #define NVIC_PRI12_INT51_M 0xE0000000 |
| #define NVIC_PRI12_INT51_S 29 |
| #define NVIC_PRI12_R (*((volatile uint32_t *)0xE000E430)) |
| #define NVIC_PRI13_INT52_M 0x000000E0 |
| #define NVIC_PRI13_INT52_S 5 |
| #define NVIC_PRI13_INT53_M 0x0000E000 |
| #define NVIC_PRI13_INT53_S 13 |
| #define NVIC_PRI13_INT54_M 0x00E00000 |
| #define NVIC_PRI13_INT54_S 21 |
| #define NVIC_PRI13_INT55_M 0xE0000000 |
| #define NVIC_PRI13_INT55_S 29 |
| #define NVIC_PRI13_R (*((volatile uint32_t *)0xE000E434)) |
| #define NVIC_PRI14_INTA_M 0x000000E0 |
| #define NVIC_PRI14_INTA_S 5 |
| #define NVIC_PRI14_INTB_M 0x0000E000 |
| #define NVIC_PRI14_INTB_S 13 |
| #define NVIC_PRI14_INTC_M 0x00E00000 |
| #define NVIC_PRI14_INTC_S 21 |
| #define NVIC_PRI14_INTD_M 0xE0000000 |
| #define NVIC_PRI14_INTD_S 29 |
| #define NVIC_PRI14_R (*((volatile uint32_t *)0xE000E438)) |
| #define NVIC_PRI15_INTA_M 0x000000E0 |
| #define NVIC_PRI15_INTA_S 5 |
| #define NVIC_PRI15_INTB_M 0x0000E000 |
| #define NVIC_PRI15_INTB_S 13 |
| #define NVIC_PRI15_INTC_M 0x00E00000 |
| #define NVIC_PRI15_INTC_S 21 |
| #define NVIC_PRI15_INTD_M 0xE0000000 |
| #define NVIC_PRI15_INTD_S 29 |
| #define NVIC_PRI15_R (*((volatile uint32_t *)0xE000E43C)) |
| #define NVIC_PRI16_INTA_M 0x000000E0 |
| #define NVIC_PRI16_INTA_S 5 |
| #define NVIC_PRI16_INTB_M 0x0000E000 |
| #define NVIC_PRI16_INTB_S 13 |
| #define NVIC_PRI16_INTC_M 0x00E00000 |
| #define NVIC_PRI16_INTC_S 21 |
| #define NVIC_PRI16_INTD_M 0xE0000000 |
| #define NVIC_PRI16_INTD_S 29 |
| #define NVIC_PRI16_R (*((volatile uint32_t *)0xE000E440)) |
| #define NVIC_PRI17_INTA_M 0x000000E0 |
| #define NVIC_PRI17_INTA_S 5 |
| #define NVIC_PRI17_INTB_M 0x0000E000 |
| #define NVIC_PRI17_INTB_S 13 |
| #define NVIC_PRI17_INTC_M 0x00E00000 |
| #define NVIC_PRI17_INTC_S 21 |
| #define NVIC_PRI17_INTD_M 0xE0000000 |
| #define NVIC_PRI17_INTD_S 29 |
| #define NVIC_PRI17_R (*((volatile uint32_t *)0xE000E444)) |
| #define NVIC_PRI18_INTA_M 0x000000E0 |
| #define NVIC_PRI18_INTA_S 5 |
| #define NVIC_PRI18_INTB_M 0x0000E000 |
| #define NVIC_PRI18_INTB_S 13 |
| #define NVIC_PRI18_INTC_M 0x00E00000 |
| #define NVIC_PRI18_INTC_S 21 |
| #define NVIC_PRI18_INTD_M 0xE0000000 |
| #define NVIC_PRI18_INTD_S 29 |
| #define NVIC_PRI18_R (*((volatile uint32_t *)0xE000E448)) |
| #define NVIC_PRI19_INTA_M 0x000000E0 |
| #define NVIC_PRI19_INTA_S 5 |
| #define NVIC_PRI19_INTB_M 0x0000E000 |
| #define NVIC_PRI19_INTB_S 13 |
| #define NVIC_PRI19_INTC_M 0x00E00000 |
| #define NVIC_PRI19_INTC_S 21 |
| #define NVIC_PRI19_INTD_M 0xE0000000 |
| #define NVIC_PRI19_INTD_S 29 |
| #define NVIC_PRI19_R (*((volatile uint32_t *)0xE000E44C)) |
| #define NVIC_PRI1_INT4_M 0x000000E0 |
| #define NVIC_PRI1_INT4_S 5 |
| #define NVIC_PRI1_INT5_M 0x0000E000 |
| #define NVIC_PRI1_INT5_S 13 |
| #define NVIC_PRI1_INT6_M 0x00E00000 |
| #define NVIC_PRI1_INT6_S 21 |
| #define NVIC_PRI1_INT7_M 0xE0000000 |
| #define NVIC_PRI1_INT7_S 29 |
| #define NVIC_PRI1_R (*((volatile uint32_t *)0xE000E404)) |
| #define NVIC_PRI20_INTA_M 0x000000E0 |
| #define NVIC_PRI20_INTA_S 5 |
| #define NVIC_PRI20_INTB_M 0x0000E000 |
| #define NVIC_PRI20_INTB_S 13 |
| #define NVIC_PRI20_INTC_M 0x00E00000 |
| #define NVIC_PRI20_INTC_S 21 |
| #define NVIC_PRI20_INTD_M 0xE0000000 |
| #define NVIC_PRI20_INTD_S 29 |
| #define NVIC_PRI20_R (*((volatile uint32_t *)0xE000E450)) |
| #define NVIC_PRI21_INTA_M 0x000000E0 |
| #define NVIC_PRI21_INTA_S 5 |
| #define NVIC_PRI21_INTB_M 0x0000E000 |
| #define NVIC_PRI21_INTB_S 13 |
| #define NVIC_PRI21_INTC_M 0x00E00000 |
| #define NVIC_PRI21_INTC_S 21 |
| #define NVIC_PRI21_INTD_M 0xE0000000 |
| #define NVIC_PRI21_INTD_S 29 |
| #define NVIC_PRI21_R (*((volatile uint32_t *)0xE000E454)) |
| #define NVIC_PRI22_INTA_M 0x000000E0 |
| #define NVIC_PRI22_INTA_S 5 |
| #define NVIC_PRI22_INTB_M 0x0000E000 |
| #define NVIC_PRI22_INTB_S 13 |
| #define NVIC_PRI22_INTC_M 0x00E00000 |
| #define NVIC_PRI22_INTC_S 21 |
| #define NVIC_PRI22_INTD_M 0xE0000000 |
| #define NVIC_PRI22_INTD_S 29 |
| #define NVIC_PRI22_R (*((volatile uint32_t *)0xE000E458)) |
| #define NVIC_PRI23_INTA_M 0x000000E0 |
| #define NVIC_PRI23_INTA_S 5 |
| #define NVIC_PRI23_INTB_M 0x0000E000 |
| #define NVIC_PRI23_INTB_S 13 |
| #define NVIC_PRI23_INTC_M 0x00E00000 |
| #define NVIC_PRI23_INTC_S 21 |
| #define NVIC_PRI23_INTD_M 0xE0000000 |
| #define NVIC_PRI23_INTD_S 29 |
| #define NVIC_PRI23_R (*((volatile uint32_t *)0xE000E45C)) |
| #define NVIC_PRI24_INTA_M 0x000000E0 |
| #define NVIC_PRI24_INTA_S 5 |
| #define NVIC_PRI24_INTB_M 0x0000E000 |
| #define NVIC_PRI24_INTB_S 13 |
| #define NVIC_PRI24_INTC_M 0x00E00000 |
| #define NVIC_PRI24_INTC_S 21 |
| #define NVIC_PRI24_INTD_M 0xE0000000 |
| #define NVIC_PRI24_INTD_S 29 |
| #define NVIC_PRI24_R (*((volatile uint32_t *)0xE000E460)) |
| #define NVIC_PRI25_INTA_M 0x000000E0 |
| #define NVIC_PRI25_INTA_S 5 |
| #define NVIC_PRI25_INTB_M 0x0000E000 |
| #define NVIC_PRI25_INTB_S 13 |
| #define NVIC_PRI25_INTC_M 0x00E00000 |
| #define NVIC_PRI25_INTC_S 21 |
| #define NVIC_PRI25_INTD_M 0xE0000000 |
| #define NVIC_PRI25_INTD_S 29 |
| #define NVIC_PRI25_R (*((volatile uint32_t *)0xE000E464)) |
| #define NVIC_PRI26_INTA_M 0x000000E0 |
| #define NVIC_PRI26_INTA_S 5 |
| #define NVIC_PRI26_INTB_M 0x0000E000 |
| #define NVIC_PRI26_INTB_S 13 |
| #define NVIC_PRI26_INTC_M 0x00E00000 |
| #define NVIC_PRI26_INTC_S 21 |
| #define NVIC_PRI26_INTD_M 0xE0000000 |
| #define NVIC_PRI26_INTD_S 29 |
| #define NVIC_PRI26_R (*((volatile uint32_t *)0xE000E468)) |
| #define NVIC_PRI27_INTA_M 0x000000E0 |
| #define NVIC_PRI27_INTA_S 5 |
| #define NVIC_PRI27_INTB_M 0x0000E000 |
| #define NVIC_PRI27_INTB_S 13 |
| #define NVIC_PRI27_INTC_M 0x00E00000 |
| #define NVIC_PRI27_INTC_S 21 |
| #define NVIC_PRI27_INTD_M 0xE0000000 |
| #define NVIC_PRI27_INTD_S 29 |
| #define NVIC_PRI27_R (*((volatile uint32_t *)0xE000E46C)) |
| #define NVIC_PRI28_INTA_M 0x000000E0 |
| #define NVIC_PRI28_INTA_S 5 |
| #define NVIC_PRI28_INTB_M 0x0000E000 |
| #define NVIC_PRI28_INTB_S 13 |
| #define NVIC_PRI28_INTC_M 0x00E00000 |
| #define NVIC_PRI28_INTC_S 21 |
| #define NVIC_PRI28_INTD_M 0xE0000000 |
| #define NVIC_PRI28_INTD_S 29 |
| #define NVIC_PRI28_R (*((volatile uint32_t *)0xE000E470)) |
| #define NVIC_PRI29_INTA_M 0x000000E0 |
| #define NVIC_PRI29_INTA_S 5 |
| #define NVIC_PRI29_INTB_M 0x0000E000 |
| #define NVIC_PRI29_INTB_S 13 |
| #define NVIC_PRI29_INTC_M 0x00E00000 |
| #define NVIC_PRI29_INTC_S 21 |
| #define NVIC_PRI29_INTD_M 0xE0000000 |
| #define NVIC_PRI29_INTD_S 29 |
| #define NVIC_PRI29_R (*((volatile uint32_t *)0xE000E474)) |
| #define NVIC_PRI2_INT10_M 0x00E00000 |
| #define NVIC_PRI2_INT10_S 21 |
| #define NVIC_PRI2_INT11_M 0xE0000000 |
| #define NVIC_PRI2_INT11_S 29 |
| #define NVIC_PRI2_INT8_M 0x000000E0 |
| #define NVIC_PRI2_INT8_S 5 |
| #define NVIC_PRI2_INT9_M 0x0000E000 |
| #define NVIC_PRI2_INT9_S 13 |
| #define NVIC_PRI2_R (*((volatile uint32_t *)0xE000E408)) |
| #define NVIC_PRI30_INTA_M 0x000000E0 |
| #define NVIC_PRI30_INTA_S 5 |
| #define NVIC_PRI30_INTB_M 0x0000E000 |
| #define NVIC_PRI30_INTB_S 13 |
| #define NVIC_PRI30_INTC_M 0x00E00000 |
| #define NVIC_PRI30_INTC_S 21 |
| #define NVIC_PRI30_INTD_M 0xE0000000 |
| #define NVIC_PRI30_INTD_S 29 |
| #define NVIC_PRI30_R (*((volatile uint32_t *)0xE000E478)) |
| #define NVIC_PRI31_INTA_M 0x000000E0 |
| #define NVIC_PRI31_INTA_S 5 |
| #define NVIC_PRI31_INTB_M 0x0000E000 |
| #define NVIC_PRI31_INTB_S 13 |
| #define NVIC_PRI31_INTC_M 0x00E00000 |
| #define NVIC_PRI31_INTC_S 21 |
| #define NVIC_PRI31_INTD_M 0xE0000000 |
| #define NVIC_PRI31_INTD_S 29 |
| #define NVIC_PRI31_R (*((volatile uint32_t *)0xE000E47C)) |
| #define NVIC_PRI32_INTA_M 0x000000E0 |
| #define NVIC_PRI32_INTA_S 5 |
| #define NVIC_PRI32_INTB_M 0x0000E000 |
| #define NVIC_PRI32_INTB_S 13 |
| #define NVIC_PRI32_INTC_M 0x00E00000 |
| #define NVIC_PRI32_INTC_S 21 |
| #define NVIC_PRI32_INTD_M 0xE0000000 |
| #define NVIC_PRI32_INTD_S 29 |
| #define NVIC_PRI32_R (*((volatile uint32_t *)0xE000E480)) |
| #define NVIC_PRI33_INTA_M 0x000000E0 |
| #define NVIC_PRI33_INTA_S 5 |
| #define NVIC_PRI33_INTB_M 0x0000E000 |
| #define NVIC_PRI33_INTB_S 13 |
| #define NVIC_PRI33_INTC_M 0x00E00000 |
| #define NVIC_PRI33_INTC_S 21 |
| #define NVIC_PRI33_INTD_M 0xE0000000 |
| #define NVIC_PRI33_INTD_S 29 |
| #define NVIC_PRI33_R (*((volatile uint32_t *)0xE000E484)) |
| #define NVIC_PRI34_INTA_M 0x000000E0 |
| #define NVIC_PRI34_INTA_S 5 |
| #define NVIC_PRI34_INTB_M 0x0000E000 |
| #define NVIC_PRI34_INTB_S 13 |
| #define NVIC_PRI34_INTC_M 0x00E00000 |
| #define NVIC_PRI34_INTC_S 21 |
| #define NVIC_PRI34_INTD_M 0xE0000000 |
| #define NVIC_PRI34_INTD_S 29 |
| #define NVIC_PRI34_R (*((volatile uint32_t *)0xE000E488)) |
| #define NVIC_PRI3_INT12_M 0x000000E0 |
| #define NVIC_PRI3_INT12_S 5 |
| #define NVIC_PRI3_INT13_M 0x0000E000 |
| #define NVIC_PRI3_INT13_S 13 |
| #define NVIC_PRI3_INT14_M 0x00E00000 |
| #define NVIC_PRI3_INT14_S 21 |
| #define NVIC_PRI3_INT15_M 0xE0000000 |
| #define NVIC_PRI3_INT15_S 29 |
| #define NVIC_PRI3_R (*((volatile uint32_t *)0xE000E40C)) |
| #define NVIC_PRI4_INT16_M 0x000000E0 |
| #define NVIC_PRI4_INT16_S 5 |
| #define NVIC_PRI4_INT17_M 0x0000E000 |
| #define NVIC_PRI4_INT17_S 13 |
| #define NVIC_PRI4_INT18_M 0x00E00000 |
| #define NVIC_PRI4_INT18_S 21 |
| #define NVIC_PRI4_INT19_M 0xE0000000 |
| #define NVIC_PRI4_INT19_S 29 |
| #define NVIC_PRI4_R (*((volatile uint32_t *)0xE000E410)) |
| #define NVIC_PRI5_INT20_M 0x000000E0 |
| #define NVIC_PRI5_INT20_S 5 |
| #define NVIC_PRI5_INT21_M 0x0000E000 |
| #define NVIC_PRI5_INT21_S 13 |
| #define NVIC_PRI5_INT22_M 0x00E00000 |
| #define NVIC_PRI5_INT22_S 21 |
| #define NVIC_PRI5_INT23_M 0xE0000000 |
| #define NVIC_PRI5_INT23_S 29 |
| #define NVIC_PRI5_R (*((volatile uint32_t *)0xE000E414)) |
| #define NVIC_PRI6_INT24_M 0x000000E0 |
| #define NVIC_PRI6_INT24_S 5 |
| #define NVIC_PRI6_INT25_M 0x0000E000 |
| #define NVIC_PRI6_INT25_S 13 |
| #define NVIC_PRI6_INT26_M 0x00E00000 |
| #define NVIC_PRI6_INT26_S 21 |
| #define NVIC_PRI6_INT27_M 0xE0000000 |
| #define NVIC_PRI6_INT27_S 29 |
| #define NVIC_PRI6_R (*((volatile uint32_t *)0xE000E418)) |
| #define NVIC_PRI7_INT28_M 0x000000E0 |
| #define NVIC_PRI7_INT28_S 5 |
| #define NVIC_PRI7_INT29_M 0x0000E000 |
| #define NVIC_PRI7_INT29_S 13 |
| #define NVIC_PRI7_INT30_M 0x00E00000 |
| #define NVIC_PRI7_INT30_S 21 |
| #define NVIC_PRI7_INT31_M 0xE0000000 |
| #define NVIC_PRI7_INT31_S 29 |
| #define NVIC_PRI7_R (*((volatile uint32_t *)0xE000E41C)) |
| #define NVIC_PRI8_INT32_M 0x000000E0 |
| #define NVIC_PRI8_INT32_S 5 |
| #define NVIC_PRI8_INT33_M 0x0000E000 |
| #define NVIC_PRI8_INT33_S 13 |
| #define NVIC_PRI8_INT34_M 0x00E00000 |
| #define NVIC_PRI8_INT34_S 21 |
| #define NVIC_PRI8_INT35_M 0xE0000000 |
| #define NVIC_PRI8_INT35_S 29 |
| #define NVIC_PRI8_R (*((volatile uint32_t *)0xE000E420)) |
| #define NVIC_PRI9_INT36_M 0x000000E0 |
| #define NVIC_PRI9_INT36_S 5 |
| #define NVIC_PRI9_INT37_M 0x0000E000 |
| #define NVIC_PRI9_INT37_S 13 |
| #define NVIC_PRI9_INT38_M 0x00E00000 |
| #define NVIC_PRI9_INT38_S 21 |
| #define NVIC_PRI9_INT39_M 0xE0000000 |
| #define NVIC_PRI9_INT39_S 29 |
| #define NVIC_PRI9_R (*((volatile uint32_t *)0xE000E424)) |
| #define NVIC_ST_CTRL_CLK_SRC 0x00000004 |
| #define NVIC_ST_CTRL_COUNT 0x00010000 |
| #define NVIC_ST_CTRL_ENABLE 0x00000001 |
| #define NVIC_ST_CTRL_INTEN 0x00000002 |
| #define NVIC_ST_CTRL_R (*((volatile uint32_t *)0xE000E010)) |
| #define NVIC_ST_CURRENT_M 0x00FFFFFF |
| #define NVIC_ST_CURRENT_R (*((volatile uint32_t *)0xE000E018)) |
| #define NVIC_ST_CURRENT_S 0 |
| #define NVIC_ST_RELOAD_M 0x00FFFFFF |
| #define NVIC_ST_RELOAD_R (*((volatile uint32_t *)0xE000E014)) |
| #define NVIC_ST_RELOAD_S 0 |
| #define NVIC_SW_TRIG_INTID_M 0x000000FF |
| #define NVIC_SW_TRIG_INTID_S 0 |
| #define NVIC_SW_TRIG_R (*((volatile uint32_t *)0xE000EF00)) |
| #define NVIC_SYS_CTRL_R (*((volatile uint32_t *)0xE000ED10)) |
| #define NVIC_SYS_CTRL_SEVONPEND 0x00000010 |
| #define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 |
| #define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 |
| #define NVIC_SYS_HND_CTRL_BUS 0x00020000 |
| #define NVIC_SYS_HND_CTRL_BUSA 0x00000002 |
| #define NVIC_SYS_HND_CTRL_BUSP 0x00004000 |
| #define NVIC_SYS_HND_CTRL_MEM 0x00010000 |
| #define NVIC_SYS_HND_CTRL_MEMA 0x00000001 |
| #define NVIC_SYS_HND_CTRL_MEMP 0x00002000 |
| #define NVIC_SYS_HND_CTRL_MON 0x00000100 |
| #define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 |
| #define NVIC_SYS_HND_CTRL_R (*((volatile uint32_t *)0xE000ED24)) |
| #define NVIC_SYS_HND_CTRL_SVC 0x00008000 |
| #define NVIC_SYS_HND_CTRL_SVCA 0x00000080 |
| #define NVIC_SYS_HND_CTRL_TICK 0x00000800 |
| #define NVIC_SYS_HND_CTRL_USAGE 0x00040000 |
| #define NVIC_SYS_HND_CTRL_USAGEP 0x00001000 |
| #define NVIC_SYS_HND_CTRL_USGA 0x00000008 |
| #define NVIC_SYS_PRI1_BUS_M 0x0000E000 |
| #define NVIC_SYS_PRI1_BUS_S 13 |
| #define NVIC_SYS_PRI1_MEM_M 0x000000E0 |
| #define NVIC_SYS_PRI1_MEM_S 5 |
| #define NVIC_SYS_PRI1_R (*((volatile uint32_t *)0xE000ED18)) |
| #define NVIC_SYS_PRI1_USAGE_M 0x00E00000 |
| #define NVIC_SYS_PRI1_USAGE_S 21 |
| #define NVIC_SYS_PRI2_R (*((volatile uint32_t *)0xE000ED1C)) |
| #define NVIC_SYS_PRI2_SVC_M 0xE0000000 |
| #define NVIC_SYS_PRI2_SVC_S 29 |
| #define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 |
| #define NVIC_SYS_PRI3_DEBUG_S 5 |
| #define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 |
| #define NVIC_SYS_PRI3_PENDSV_S 21 |
| #define NVIC_SYS_PRI3_R (*((volatile uint32_t *)0xE000ED20)) |
| #define NVIC_SYS_PRI3_TICK_M 0xE0000000 |
| #define NVIC_SYS_PRI3_TICK_S 29 |
| #define NVIC_UNPEND0_INT_M 0xFFFFFFFF |
| #define NVIC_UNPEND0_R (*((volatile uint32_t *)0xE000E280)) |
| #define NVIC_UNPEND1_INT_M 0xFFFFFFFF |
| #define NVIC_UNPEND1_R (*((volatile uint32_t *)0xE000E284)) |
| #define NVIC_UNPEND2_INT_M 0xFFFFFFFF |
| #define NVIC_UNPEND2_R (*((volatile uint32_t *)0xE000E288)) |
| #define NVIC_UNPEND3_INT_M 0xFFFFFFFF |
| #define NVIC_UNPEND3_R (*((volatile uint32_t *)0xE000E28C)) |
| #define NVIC_UNPEND4_INT_M 0x000007FF |
| #define NVIC_UNPEND4_R (*((volatile uint32_t *)0xE000E290)) |
| #define NVIC_VTABLE_OFFSET_M 0xFFFFFC00 |
| #define NVIC_VTABLE_OFFSET_S 10 |
| #define NVIC_VTABLE_R (*((volatile uint32_t *)0xE000ED08)) |
| #define PWM0_0_CMPA_R (*((volatile uint32_t *)0x40028058)) |
| #define PWM0_0_CMPB_R (*((volatile uint32_t *)0x4002805C)) |
| #define PWM0_0_COUNT_R (*((volatile uint32_t *)0x40028054)) |
| #define PWM0_0_CTL_R (*((volatile uint32_t *)0x40028040)) |
| #define PWM0_0_DBCTL_R (*((volatile uint32_t *)0x40028068)) |
| #define PWM0_0_DBFALL_R (*((volatile uint32_t *)0x40028070)) |
| #define PWM0_0_DBRISE_R (*((volatile uint32_t *)0x4002806C)) |
| #define PWM0_0_FLTSEN_R (*((volatile uint32_t *)0x40028800)) |
| #define PWM0_0_FLTSRC0_R (*((volatile uint32_t *)0x40028074)) |
| #define PWM0_0_FLTSRC1_R (*((volatile uint32_t *)0x40028078)) |
| #define PWM0_0_FLTSTAT0_R (*((volatile uint32_t *)0x40028804)) |
| #define PWM0_0_FLTSTAT1_R (*((volatile uint32_t *)0x40028808)) |
| #define PWM0_0_GENA_R (*((volatile uint32_t *)0x40028060)) |
| #define PWM0_0_GENB_R (*((volatile uint32_t *)0x40028064)) |
| #define PWM0_0_INTEN_R (*((volatile uint32_t *)0x40028044)) |
| #define PWM0_0_ISC_R (*((volatile uint32_t *)0x4002804C)) |
| #define PWM0_0_LOAD_R (*((volatile uint32_t *)0x40028050)) |
| #define PWM0_0_MINFLTPER_R (*((volatile uint32_t *)0x4002807C)) |
| #define PWM0_0_RIS_R (*((volatile uint32_t *)0x40028048)) |
| #define PWM0_1_CMPA_R (*((volatile uint32_t *)0x40028098)) |
| #define PWM0_1_CMPB_R (*((volatile uint32_t *)0x4002809C)) |
| #define PWM0_1_COUNT_R (*((volatile uint32_t *)0x40028094)) |
| #define PWM0_1_CTL_R (*((volatile uint32_t *)0x40028080)) |
| #define PWM0_1_DBCTL_R (*((volatile uint32_t *)0x400280A8)) |
| #define PWM0_1_DBFALL_R (*((volatile uint32_t *)0x400280B0)) |
| #define PWM0_1_DBRISE_R (*((volatile uint32_t *)0x400280AC)) |
| #define PWM0_1_FLTSEN_R (*((volatile uint32_t *)0x40028880)) |
| #define PWM0_1_FLTSRC0_R (*((volatile uint32_t *)0x400280B4)) |
| #define PWM0_1_FLTSRC1_R (*((volatile uint32_t *)0x400280B8)) |
| #define PWM0_1_FLTSTAT0_R (*((volatile uint32_t *)0x40028884)) |
| #define PWM0_1_FLTSTAT1_R (*((volatile uint32_t *)0x40028888)) |
| #define PWM0_1_GENA_R (*((volatile uint32_t *)0x400280A0)) |
| #define PWM0_1_GENB_R (*((volatile uint32_t *)0x400280A4)) |
| #define PWM0_1_INTEN_R (*((volatile uint32_t *)0x40028084)) |
| #define PWM0_1_ISC_R (*((volatile uint32_t *)0x4002808C)) |
| #define PWM0_1_LOAD_R (*((volatile uint32_t *)0x40028090)) |
| #define PWM0_1_MINFLTPER_R (*((volatile uint32_t *)0x400280BC)) |
| #define PWM0_1_RIS_R (*((volatile uint32_t *)0x40028088)) |
| #define PWM0_2_CMPA_R (*((volatile uint32_t *)0x400280D8)) |
| #define PWM0_2_CMPB_R (*((volatile uint32_t *)0x400280DC)) |
| #define PWM0_2_COUNT_R (*((volatile uint32_t *)0x400280D4)) |
| #define PWM0_2_CTL_R (*((volatile uint32_t *)0x400280C0)) |
| #define PWM0_2_DBCTL_R (*((volatile uint32_t *)0x400280E8)) |
| #define PWM0_2_DBFALL_R (*((volatile uint32_t *)0x400280F0)) |
| #define PWM0_2_DBRISE_R (*((volatile uint32_t *)0x400280EC)) |
| #define PWM0_2_FLTSEN_R (*((volatile uint32_t *)0x40028900)) |
| #define PWM0_2_FLTSRC0_R (*((volatile uint32_t *)0x400280F4)) |
| #define PWM0_2_FLTSRC1_R (*((volatile uint32_t *)0x400280F8)) |
| #define PWM0_2_FLTSTAT0_R (*((volatile uint32_t *)0x40028904)) |
| #define PWM0_2_FLTSTAT1_R (*((volatile uint32_t *)0x40028908)) |
| #define PWM0_2_GENA_R (*((volatile uint32_t *)0x400280E0)) |
| #define PWM0_2_GENB_R (*((volatile uint32_t *)0x400280E4)) |
| #define PWM0_2_INTEN_R (*((volatile uint32_t *)0x400280C4)) |
| #define PWM0_2_ISC_R (*((volatile uint32_t *)0x400280CC)) |
| #define PWM0_2_LOAD_R (*((volatile uint32_t *)0x400280D0)) |
| #define PWM0_2_MINFLTPER_R (*((volatile uint32_t *)0x400280FC)) |
| #define PWM0_2_RIS_R (*((volatile uint32_t *)0x400280C8)) |
| #define PWM0_3_CMPA_R (*((volatile uint32_t *)0x40028118)) |
| #define PWM0_3_CMPB_R (*((volatile uint32_t *)0x4002811C)) |
| #define PWM0_3_COUNT_R (*((volatile uint32_t *)0x40028114)) |
| #define PWM0_3_CTL_R (*((volatile uint32_t *)0x40028100)) |
| #define PWM0_3_DBCTL_R (*((volatile uint32_t *)0x40028128)) |
| #define PWM0_3_DBFALL_R (*((volatile uint32_t *)0x40028130)) |
| #define PWM0_3_DBRISE_R (*((volatile uint32_t *)0x4002812C)) |
| #define PWM0_3_FLTSEN_R (*((volatile uint32_t *)0x40028980)) |
| #define PWM0_3_FLTSRC0_R (*((volatile uint32_t *)0x40028134)) |
| #define PWM0_3_FLTSRC1_R (*((volatile uint32_t *)0x40028138)) |
| #define PWM0_3_FLTSTAT0_R (*((volatile uint32_t *)0x40028984)) |
| #define PWM0_3_FLTSTAT1_R (*((volatile uint32_t *)0x40028988)) |
| #define PWM0_3_GENA_R (*((volatile uint32_t *)0x40028120)) |
| #define PWM0_3_GENB_R (*((volatile uint32_t *)0x40028124)) |
| #define PWM0_3_INTEN_R (*((volatile uint32_t *)0x40028104)) |
| #define PWM0_3_ISC_R (*((volatile uint32_t *)0x4002810C)) |
| #define PWM0_3_LOAD_R (*((volatile uint32_t *)0x40028110)) |
| #define PWM0_3_MINFLTPER_R (*((volatile uint32_t *)0x4002813C)) |
| #define PWM0_3_RIS_R (*((volatile uint32_t *)0x40028108)) |
| #define PWM0_CTL_R (*((volatile uint32_t *)0x40028000)) |
| #define PWM0_ENABLE_R (*((volatile uint32_t *)0x40028008)) |
| #define PWM0_ENUPD_R (*((volatile uint32_t *)0x40028028)) |
| #define PWM0_FAULT_R (*((volatile uint32_t *)0x40028010)) |
| #define PWM0_FAULTVAL_R (*((volatile uint32_t *)0x40028024)) |
| #define PWM0_INTEN_R (*((volatile uint32_t *)0x40028014)) |
| #define PWM0_INVERT_R (*((volatile uint32_t *)0x4002800C)) |
| #define PWM0_ISC_R (*((volatile uint32_t *)0x4002801C)) |
| #define PWM0_PP_R (*((volatile uint32_t *)0x40028FC0)) |
| #define PWM0_RIS_R (*((volatile uint32_t *)0x40028018)) |
| #define PWM0_STATUS_R (*((volatile uint32_t *)0x40028020)) |
| #define PWM0_SYNC_R (*((volatile uint32_t *)0x40028004)) |
| #define PWM1_0_CMPA_R (*((volatile uint32_t *)0x40029058)) |
| #define PWM1_0_CMPB_R (*((volatile uint32_t *)0x4002905C)) |
| #define PWM1_0_COUNT_R (*((volatile uint32_t *)0x40029054)) |
| #define PWM1_0_CTL_R (*((volatile uint32_t *)0x40029040)) |
| #define PWM1_0_DBCTL_R (*((volatile uint32_t *)0x40029068)) |
| #define PWM1_0_DBFALL_R (*((volatile uint32_t *)0x40029070)) |
| #define PWM1_0_DBRISE_R (*((volatile uint32_t *)0x4002906C)) |
| #define PWM1_0_FLTSEN_R (*((volatile uint32_t *)0x40029800)) |
| #define PWM1_0_FLTSRC0_R (*((volatile uint32_t *)0x40029074)) |
| #define PWM1_0_FLTSRC1_R (*((volatile uint32_t *)0x40029078)) |
| #define PWM1_0_FLTSTAT0_R (*((volatile uint32_t *)0x40029804)) |
| #define PWM1_0_FLTSTAT1_R (*((volatile uint32_t *)0x40029808)) |
| #define PWM1_0_GENA_R (*((volatile uint32_t *)0x40029060)) |
| #define PWM1_0_GENB_R (*((volatile uint32_t *)0x40029064)) |
| #define PWM1_0_INTEN_R (*((volatile uint32_t *)0x40029044)) |
| #define PWM1_0_ISC_R (*((volatile uint32_t *)0x4002904C)) |
| #define PWM1_0_LOAD_R (*((volatile uint32_t *)0x40029050)) |
| #define PWM1_0_MINFLTPER_R (*((volatile uint32_t *)0x4002907C)) |
| #define PWM1_0_RIS_R (*((volatile uint32_t *)0x40029048)) |
| #define PWM1_1_CMPA_R (*((volatile uint32_t *)0x40029098)) |
| #define PWM1_1_CMPB_R (*((volatile uint32_t *)0x4002909C)) |
| #define PWM1_1_COUNT_R (*((volatile uint32_t *)0x40029094)) |
| #define PWM1_1_CTL_R (*((volatile uint32_t *)0x40029080)) |
| #define PWM1_1_DBCTL_R (*((volatile uint32_t *)0x400290A8)) |
| #define PWM1_1_DBFALL_R (*((volatile uint32_t *)0x400290B0)) |
| #define PWM1_1_DBRISE_R (*((volatile uint32_t *)0x400290AC)) |
| #define PWM1_1_FLTSEN_R (*((volatile uint32_t *)0x40029880)) |
| #define PWM1_1_FLTSRC0_R (*((volatile uint32_t *)0x400290B4)) |
| #define PWM1_1_FLTSRC1_R (*((volatile uint32_t *)0x400290B8)) |
| #define PWM1_1_FLTSTAT0_R (*((volatile uint32_t *)0x40029884)) |
| #define PWM1_1_FLTSTAT1_R (*((volatile uint32_t *)0x40029888)) |
| #define PWM1_1_GENA_R (*((volatile uint32_t *)0x400290A0)) |
| #define PWM1_1_GENB_R (*((volatile uint32_t *)0x400290A4)) |
| #define PWM1_1_INTEN_R (*((volatile uint32_t *)0x40029084)) |
| #define PWM1_1_ISC_R (*((volatile uint32_t *)0x4002908C)) |
| #define PWM1_1_LOAD_R (*((volatile uint32_t *)0x40029090)) |
| #define PWM1_1_MINFLTPER_R (*((volatile uint32_t *)0x400290BC)) |
| #define PWM1_1_RIS_R (*((volatile uint32_t *)0x40029088)) |
| #define PWM1_2_CMPA_R (*((volatile uint32_t *)0x400290D8)) |
| #define PWM1_2_CMPB_R (*((volatile uint32_t *)0x400290DC)) |
| #define PWM1_2_COUNT_R (*((volatile uint32_t *)0x400290D4)) |
| #define PWM1_2_CTL_R (*((volatile uint32_t *)0x400290C0)) |
| #define PWM1_2_DBCTL_R (*((volatile uint32_t *)0x400290E8)) |
| #define PWM1_2_DBFALL_R (*((volatile uint32_t *)0x400290F0)) |
| #define PWM1_2_DBRISE_R (*((volatile uint32_t *)0x400290EC)) |
| #define PWM1_2_FLTSEN_R (*((volatile uint32_t *)0x40029900)) |
| #define PWM1_2_FLTSRC0_R (*((volatile uint32_t *)0x400290F4)) |
| #define PWM1_2_FLTSRC1_R (*((volatile uint32_t *)0x400290F8)) |
| #define PWM1_2_FLTSTAT0_R (*((volatile uint32_t *)0x40029904)) |
| #define PWM1_2_FLTSTAT1_R (*((volatile uint32_t *)0x40029908)) |
| #define PWM1_2_GENA_R (*((volatile uint32_t *)0x400290E0)) |
| #define PWM1_2_GENB_R (*((volatile uint32_t *)0x400290E4)) |
| #define PWM1_2_INTEN_R (*((volatile uint32_t *)0x400290C4)) |
| #define PWM1_2_ISC_R (*((volatile uint32_t *)0x400290CC)) |
| #define PWM1_2_LOAD_R (*((volatile uint32_t *)0x400290D0)) |
| #define PWM1_2_MINFLTPER_R (*((volatile uint32_t *)0x400290FC)) |
| #define PWM1_2_RIS_R (*((volatile uint32_t *)0x400290C8)) |
| #define PWM1_3_CMPA_R (*((volatile uint32_t *)0x40029118)) |
| #define PWM1_3_CMPB_R (*((volatile uint32_t *)0x4002911C)) |
| #define PWM1_3_COUNT_R (*((volatile uint32_t *)0x40029114)) |
| #define PWM1_3_CTL_R (*((volatile uint32_t *)0x40029100)) |
| #define PWM1_3_DBCTL_R (*((volatile uint32_t *)0x40029128)) |
| #define PWM1_3_DBFALL_R (*((volatile uint32_t *)0x40029130)) |
| #define PWM1_3_DBRISE_R (*((volatile uint32_t *)0x4002912C)) |
| #define PWM1_3_FLTSEN_R (*((volatile uint32_t *)0x40029980)) |
| #define PWM1_3_FLTSRC0_R (*((volatile uint32_t *)0x40029134)) |
| #define PWM1_3_FLTSRC1_R (*((volatile uint32_t *)0x40029138)) |
| #define PWM1_3_FLTSTAT0_R (*((volatile uint32_t *)0x40029984)) |
| #define PWM1_3_FLTSTAT1_R (*((volatile uint32_t *)0x40029988)) |
| #define PWM1_3_GENA_R (*((volatile uint32_t *)0x40029120)) |
| #define PWM1_3_GENB_R (*((volatile uint32_t *)0x40029124)) |
| #define PWM1_3_INTEN_R (*((volatile uint32_t *)0x40029104)) |
| #define PWM1_3_ISC_R (*((volatile uint32_t *)0x4002910C)) |
| #define PWM1_3_LOAD_R (*((volatile uint32_t *)0x40029110)) |
| #define PWM1_3_MINFLTPER_R (*((volatile uint32_t *)0x4002913C)) |
| #define PWM1_3_RIS_R (*((volatile uint32_t *)0x40029108)) |
| #define PWM1_CTL_R (*((volatile uint32_t *)0x40029000)) |
| #define PWM1_ENABLE_R (*((volatile uint32_t *)0x40029008)) |
| #define PWM1_ENUPD_R (*((volatile uint32_t *)0x40029028)) |
| #define PWM1_FAULT_R (*((volatile uint32_t *)0x40029010)) |
| #define PWM1_FAULTVAL_R (*((volatile uint32_t *)0x40029024)) |
| #define PWM1_INTEN_R (*((volatile uint32_t *)0x40029014)) |
| #define PWM1_INVERT_R (*((volatile uint32_t *)0x4002900C)) |
| #define PWM1_ISC_R (*((volatile uint32_t *)0x4002901C)) |
| #define PWM1_PP_R (*((volatile uint32_t *)0x40029FC0)) |
| #define PWM1_RIS_R (*((volatile uint32_t *)0x40029018)) |
| #define PWM1_STATUS_R (*((volatile uint32_t *)0x40029020)) |
| #define PWM1_SYNC_R (*((volatile uint32_t *)0x40029004)) |
| #define PWM_0_CMPA_M 0x0000FFFF |
| #define PWM_0_CMPA_S 0 |
| #define PWM_0_CMPB_M 0x0000FFFF |
| #define PWM_0_CMPB_S 0 |
| #define PWM_0_COUNT_M 0x0000FFFF |
| #define PWM_0_COUNT_S 0 |
| #define PWM_0_CTL_CMPAUPD 0x00000010 |
| #define PWM_0_CTL_CMPBUPD 0x00000020 |
| #define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 |
| #define PWM_0_CTL_DBCTLUPD_I 0x00000000 |
| #define PWM_0_CTL_DBCTLUPD_LS 0x00000800 |
| #define PWM_0_CTL_DBCTLUPD_M 0x00000C00 |
| #define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 |
| #define PWM_0_CTL_DBFALLUPD_I 0x00000000 |
| #define PWM_0_CTL_DBFALLUPD_LS 0x00008000 |
| #define PWM_0_CTL_DBFALLUPD_M 0x0000C000 |
| #define PWM_0_CTL_DBRISEUPD_GS 0x00003000 |
| #define PWM_0_CTL_DBRISEUPD_I 0x00000000 |
| #define PWM_0_CTL_DBRISEUPD_LS 0x00002000 |
| #define PWM_0_CTL_DBRISEUPD_M 0x00003000 |
| #define PWM_0_CTL_DEBUG 0x00000004 |
| #define PWM_0_CTL_ENABLE 0x00000001 |
| #define PWM_0_CTL_FLTSRC 0x00010000 |
| #define PWM_0_CTL_GENAUPD_GS 0x000000C0 |
| #define PWM_0_CTL_GENAUPD_I 0x00000000 |
| #define PWM_0_CTL_GENAUPD_LS 0x00000080 |
| #define PWM_0_CTL_GENAUPD_M 0x000000C0 |
| #define PWM_0_CTL_GENBUPD_GS 0x00000300 |
| #define PWM_0_CTL_GENBUPD_I 0x00000000 |
| #define PWM_0_CTL_GENBUPD_LS 0x00000200 |
| #define PWM_0_CTL_GENBUPD_M 0x00000300 |
| #define PWM_0_CTL_LATCH 0x00040000 |
| #define PWM_0_CTL_LOADUPD 0x00000008 |
| #define PWM_0_CTL_MINFLTPER 0x00020000 |
| #define PWM_0_CTL_MODE 0x00000002 |
| #define PWM_0_DBCTL_ENABLE 0x00000001 |
| #define PWM_0_DBFALL_DELAY_M 0x00000FFF |
| #define PWM_0_DBFALL_DELAY_S 0 |
| #define PWM_0_DBRISE_DELAY_M 0x00000FFF |
| #define PWM_0_DBRISE_DELAY_S 0 |
| #define PWM_0_FLTSEN_FAULT0 0x00000001 |
| #define PWM_0_FLTSEN_FAULT1 0x00000002 |
| #define PWM_0_FLTSEN_FAULT2 0x00000004 |
| #define PWM_0_FLTSEN_FAULT3 0x00000008 |
| #define PWM_0_FLTSRC0_FAULT0 0x00000001 |
| #define PWM_0_FLTSRC0_FAULT1 0x00000002 |
| #define PWM_0_FLTSRC0_FAULT2 0x00000004 |
| #define PWM_0_FLTSRC0_FAULT3 0x00000008 |
| #define PWM_0_FLTSRC1_DCMP0 0x00000001 |
| #define PWM_0_FLTSRC1_DCMP1 0x00000002 |
| #define PWM_0_FLTSRC1_DCMP2 0x00000004 |
| #define PWM_0_FLTSRC1_DCMP3 0x00000008 |
| #define PWM_0_FLTSRC1_DCMP4 0x00000010 |
| #define PWM_0_FLTSRC1_DCMP5 0x00000020 |
| #define PWM_0_FLTSRC1_DCMP6 0x00000040 |
| #define PWM_0_FLTSRC1_DCMP7 0x00000080 |
| #define PWM_0_FLTSTAT0_FAULT0 0x00000001 |
| #define PWM_0_FLTSTAT0_FAULT1 0x00000002 |
| #define PWM_0_FLTSTAT0_FAULT2 0x00000004 |
| #define PWM_0_FLTSTAT0_FAULT3 0x00000008 |
| #define PWM_0_FLTSTAT1_DCMP0 0x00000001 |
| #define PWM_0_FLTSTAT1_DCMP1 0x00000002 |
| #define PWM_0_FLTSTAT1_DCMP2 0x00000004 |
| #define PWM_0_FLTSTAT1_DCMP3 0x00000008 |
| #define PWM_0_FLTSTAT1_DCMP4 0x00000010 |
| #define PWM_0_FLTSTAT1_DCMP5 0x00000020 |
| #define PWM_0_FLTSTAT1_DCMP6 0x00000040 |
| #define PWM_0_FLTSTAT1_DCMP7 0x00000080 |
| #define PWM_0_GENA_ACTCMPAD_INV 0x00000040 |
| #define PWM_0_GENA_ACTCMPAD_M 0x000000C0 |
| #define PWM_0_GENA_ACTCMPAD_NONE 0x00000000 |
| #define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 |
| #define PWM_0_GENA_ACTCMPAD_ZERO 0x00000080 |
| #define PWM_0_GENA_ACTCMPAU_INV 0x00000010 |
| #define PWM_0_GENA_ACTCMPAU_M 0x00000030 |
| #define PWM_0_GENA_ACTCMPAU_NONE 0x00000000 |
| #define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 |
| #define PWM_0_GENA_ACTCMPAU_ZERO 0x00000020 |
| #define PWM_0_GENA_ACTCMPBD_INV 0x00000400 |
| #define PWM_0_GENA_ACTCMPBD_M 0x00000C00 |
| #define PWM_0_GENA_ACTCMPBD_NONE 0x00000000 |
| #define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 |
| #define PWM_0_GENA_ACTCMPBD_ZERO 0x00000800 |
| #define PWM_0_GENA_ACTCMPBU_INV 0x00000100 |
| #define PWM_0_GENA_ACTCMPBU_M 0x00000300 |
| #define PWM_0_GENA_ACTCMPBU_NONE 0x00000000 |
| #define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 |
| #define PWM_0_GENA_ACTCMPBU_ZERO 0x00000200 |
| #define PWM_0_GENA_ACTLOAD_INV 0x00000004 |
| #define PWM_0_GENA_ACTLOAD_M 0x0000000C |
| #define PWM_0_GENA_ACTLOAD_NONE 0x00000000 |
| #define PWM_0_GENA_ACTLOAD_ONE 0x0000000C |
| #define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 |
| #define PWM_0_GENA_ACTZERO_INV 0x00000001 |
| #define PWM_0_GENA_ACTZERO_M 0x00000003 |
| #define PWM_0_GENA_ACTZERO_NONE 0x00000000 |
| #define PWM_0_GENA_ACTZERO_ONE 0x00000003 |
| #define PWM_0_GENA_ACTZERO_ZERO 0x00000002 |
| #define PWM_0_GENB_ACTCMPAD_INV 0x00000040 |
| #define PWM_0_GENB_ACTCMPAD_M 0x000000C0 |
| #define PWM_0_GENB_ACTCMPAD_NONE 0x00000000 |
| #define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 |
| #define PWM_0_GENB_ACTCMPAD_ZERO 0x00000080 |
| #define PWM_0_GENB_ACTCMPAU_INV 0x00000010 |
| #define PWM_0_GENB_ACTCMPAU_M 0x00000030 |
| #define PWM_0_GENB_ACTCMPAU_NONE 0x00000000 |
| #define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 |
| #define PWM_0_GENB_ACTCMPAU_ZERO 0x00000020 |
| #define PWM_0_GENB_ACTCMPBD_INV 0x00000400 |
| #define PWM_0_GENB_ACTCMPBD_M 0x00000C00 |
| #define PWM_0_GENB_ACTCMPBD_NONE 0x00000000 |
| #define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 |
| #define PWM_0_GENB_ACTCMPBD_ZERO 0x00000800 |
| #define PWM_0_GENB_ACTCMPBU_INV 0x00000100 |
| #define PWM_0_GENB_ACTCMPBU_M 0x00000300 |
| #define PWM_0_GENB_ACTCMPBU_NONE 0x00000000 |
| #define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 |
| #define PWM_0_GENB_ACTCMPBU_ZERO 0x00000200 |
| #define PWM_0_GENB_ACTLOAD_INV 0x00000004 |
| #define PWM_0_GENB_ACTLOAD_M 0x0000000C |
| #define PWM_0_GENB_ACTLOAD_NONE 0x00000000 |
| #define PWM_0_GENB_ACTLOAD_ONE 0x0000000C |
| #define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 |
| #define PWM_0_GENB_ACTZERO_INV 0x00000001 |
| #define PWM_0_GENB_ACTZERO_M 0x00000003 |
| #define PWM_0_GENB_ACTZERO_NONE 0x00000000 |
| #define PWM_0_GENB_ACTZERO_ONE 0x00000003 |
| #define PWM_0_GENB_ACTZERO_ZERO 0x00000002 |
| #define PWM_0_INTEN_INTCMPAD 0x00000008 |
| #define PWM_0_INTEN_INTCMPAU 0x00000004 |
| #define PWM_0_INTEN_INTCMPBD 0x00000020 |
| #define PWM_0_INTEN_INTCMPBU 0x00000010 |
| #define PWM_0_INTEN_INTCNTLOAD 0x00000002 |
| #define PWM_0_INTEN_INTCNTZERO 0x00000001 |
| #define PWM_0_INTEN_TRCMPAD 0x00000800 |
| #define PWM_0_INTEN_TRCMPAU 0x00000400 |
| #define PWM_0_INTEN_TRCMPBD 0x00002000 |
| #define PWM_0_INTEN_TRCMPBU 0x00001000 |
| #define PWM_0_INTEN_TRCNTLOAD 0x00000200 |
| #define PWM_0_INTEN_TRCNTZERO 0x00000100 |
| #define PWM_0_ISC_INTCMPAD 0x00000008 |
| #define PWM_0_ISC_INTCMPAU 0x00000004 |
| #define PWM_0_ISC_INTCMPBD 0x00000020 |
| #define PWM_0_ISC_INTCMPBU 0x00000010 |
| #define PWM_0_ISC_INTCNTLOAD 0x00000002 |
| #define PWM_0_ISC_INTCNTZERO 0x00000001 |
| #define PWM_0_LOAD_M 0x0000FFFF |
| #define PWM_0_LOAD_S 0 |
| #define PWM_0_MINFLTPER_M 0x0000FFFF |
| #define PWM_0_MINFLTPER_S 0 |
| #define PWM_0_RIS_INTCMPAD 0x00000008 |
| #define PWM_0_RIS_INTCMPAU 0x00000004 |
| #define PWM_0_RIS_INTCMPBD 0x00000020 |
| #define PWM_0_RIS_INTCMPBU 0x00000010 |
| #define PWM_0_RIS_INTCNTLOAD 0x00000002 |
| #define PWM_0_RIS_INTCNTZERO 0x00000001 |
| #define PWM_1_CMPA_COMPA_M 0x0000FFFF |
| #define PWM_1_CMPA_COMPA_S 0 |
| #define PWM_1_CMPB_COMPB_M 0x0000FFFF |
| #define PWM_1_CMPB_COMPB_S 0 |
| #define PWM_1_COUNT_COUNT_M 0x0000FFFF |
| #define PWM_1_COUNT_COUNT_S 0 |
| #define PWM_1_CTL_CMPAUPD 0x00000010 |
| #define PWM_1_CTL_CMPBUPD 0x00000020 |
| #define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 |
| #define PWM_1_CTL_DBCTLUPD_I 0x00000000 |
| #define PWM_1_CTL_DBCTLUPD_LS 0x00000800 |
| #define PWM_1_CTL_DBCTLUPD_M 0x00000C00 |
| #define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 |
| #define PWM_1_CTL_DBFALLUPD_I 0x00000000 |
| #define PWM_1_CTL_DBFALLUPD_LS 0x00008000 |
| #define PWM_1_CTL_DBFALLUPD_M 0x0000C000 |
| #define PWM_1_CTL_DBRISEUPD_GS 0x00003000 |
| #define PWM_1_CTL_DBRISEUPD_I 0x00000000 |
| #define PWM_1_CTL_DBRISEUPD_LS 0x00002000 |
| #define PWM_1_CTL_DBRISEUPD_M 0x00003000 |
| #define PWM_1_CTL_DEBUG 0x00000004 |
| #define PWM_1_CTL_ENABLE 0x00000001 |
| #define PWM_1_CTL_FLTSRC 0x00010000 |
| #define PWM_1_CTL_GENAUPD_GS 0x000000C0 |
| #define PWM_1_CTL_GENAUPD_I 0x00000000 |
| #define PWM_1_CTL_GENAUPD_LS 0x00000080 |
| #define PWM_1_CTL_GENAUPD_M 0x000000C0 |
| #define PWM_1_CTL_GENBUPD_GS 0x00000300 |
| #define PWM_1_CTL_GENBUPD_I 0x00000000 |
| #define PWM_1_CTL_GENBUPD_LS 0x00000200 |
| #define PWM_1_CTL_GENBUPD_M 0x00000300 |
| #define PWM_1_CTL_LATCH 0x00040000 |
| #define PWM_1_CTL_LOADUPD 0x00000008 |
| #define PWM_1_CTL_MINFLTPER 0x00020000 |
| #define PWM_1_CTL_MODE 0x00000002 |
| #define PWM_1_DBCTL_ENABLE 0x00000001 |
| #define PWM_1_DBFALL_FALLDELAY_M 0x00000FFF |
| #define PWM_1_DBFALL_FALLDELAY_S 0 |
| #define PWM_1_DBRISE_RISEDELAY_M 0x00000FFF |
| #define PWM_1_DBRISE_RISEDELAY_S 0 |
| #define PWM_1_FLTSEN_FAULT0 0x00000001 |
| #define PWM_1_FLTSEN_FAULT1 0x00000002 |
| #define PWM_1_FLTSEN_FAULT2 0x00000004 |
| #define PWM_1_FLTSEN_FAULT3 0x00000008 |
| #define PWM_1_FLTSRC0_FAULT0 0x00000001 |
| #define PWM_1_FLTSRC0_FAULT1 0x00000002 |
| #define PWM_1_FLTSRC0_FAULT2 0x00000004 |
| #define PWM_1_FLTSRC0_FAULT3 0x00000008 |
| #define PWM_1_FLTSRC1_DCMP0 0x00000001 |
| #define PWM_1_FLTSRC1_DCMP1 0x00000002 |
| #define PWM_1_FLTSRC1_DCMP2 0x00000004 |
| #define PWM_1_FLTSRC1_DCMP3 0x00000008 |
| #define PWM_1_FLTSRC1_DCMP4 0x00000010 |
| #define PWM_1_FLTSRC1_DCMP5 0x00000020 |
| #define PWM_1_FLTSRC1_DCMP6 0x00000040 |
| #define PWM_1_FLTSRC1_DCMP7 0x00000080 |
| #define PWM_1_FLTSTAT0_FAULT0 0x00000001 |
| #define PWM_1_FLTSTAT0_FAULT1 0x00000002 |
| #define PWM_1_FLTSTAT0_FAULT2 0x00000004 |
| #define PWM_1_FLTSTAT0_FAULT3 0x00000008 |
| #define PWM_1_FLTSTAT1_DCMP0 0x00000001 |
| #define PWM_1_FLTSTAT1_DCMP1 0x00000002 |
| #define PWM_1_FLTSTAT1_DCMP2 0x00000004 |
| #define PWM_1_FLTSTAT1_DCMP3 0x00000008 |
| #define PWM_1_FLTSTAT1_DCMP4 0x00000010 |
| #define PWM_1_FLTSTAT1_DCMP5 0x00000020 |
| #define PWM_1_FLTSTAT1_DCMP6 0x00000040 |
| #define PWM_1_FLTSTAT1_DCMP7 0x00000080 |
| #define PWM_1_GENA_ACTCMPAD_INV 0x00000040 |
| #define PWM_1_GENA_ACTCMPAD_M 0x000000C0 |
| #define PWM_1_GENA_ACTCMPAD_NONE 0x00000000 |
| #define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 |
| #define PWM_1_GENA_ACTCMPAD_ZERO 0x00000080 |
| #define PWM_1_GENA_ACTCMPAU_INV 0x00000010 |
| #define PWM_1_GENA_ACTCMPAU_M 0x00000030 |
| #define PWM_1_GENA_ACTCMPAU_NONE 0x00000000 |
| #define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 |
| #define PWM_1_GENA_ACTCMPAU_ZERO 0x00000020 |
| #define PWM_1_GENA_ACTCMPBD_INV 0x00000400 |
| #define PWM_1_GENA_ACTCMPBD_M 0x00000C00 |
| #define PWM_1_GENA_ACTCMPBD_NONE 0x00000000 |
| #define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 |
| #define PWM_1_GENA_ACTCMPBD_ZERO 0x00000800 |
| #define PWM_1_GENA_ACTCMPBU_INV 0x00000100 |
| #define PWM_1_GENA_ACTCMPBU_M 0x00000300 |
| #define PWM_1_GENA_ACTCMPBU_NONE 0x00000000 |
| #define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 |
| #define PWM_1_GENA_ACTCMPBU_ZERO 0x00000200 |
| #define PWM_1_GENA_ACTLOAD_INV 0x00000004 |
| #define PWM_1_GENA_ACTLOAD_M 0x0000000C |
| #define PWM_1_GENA_ACTLOAD_NONE 0x00000000 |
| #define PWM_1_GENA_ACTLOAD_ONE 0x0000000C |
| #define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 |
| #define PWM_1_GENA_ACTZERO_INV 0x00000001 |
| #define PWM_1_GENA_ACTZERO_M 0x00000003 |
| #define PWM_1_GENA_ACTZERO_NONE 0x00000000 |
| #define PWM_1_GENA_ACTZERO_ONE 0x00000003 |
| #define PWM_1_GENA_ACTZERO_ZERO 0x00000002 |
| #define PWM_1_GENB_ACTCMPAD_INV 0x00000040 |
| #define PWM_1_GENB_ACTCMPAD_M 0x000000C0 |
| #define PWM_1_GENB_ACTCMPAD_NONE 0x00000000 |
| #define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 |
| #define PWM_1_GENB_ACTCMPAD_ZERO 0x00000080 |
| #define PWM_1_GENB_ACTCMPAU_INV 0x00000010 |
| #define PWM_1_GENB_ACTCMPAU_M 0x00000030 |
| #define PWM_1_GENB_ACTCMPAU_NONE 0x00000000 |
| #define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 |
| #define PWM_1_GENB_ACTCMPAU_ZERO 0x00000020 |
| #define PWM_1_GENB_ACTCMPBD_INV 0x00000400 |
| #define PWM_1_GENB_ACTCMPBD_M 0x00000C00 |
| #define PWM_1_GENB_ACTCMPBD_NONE 0x00000000 |
| #define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 |
| #define PWM_1_GENB_ACTCMPBD_ZERO 0x00000800 |
| #define PWM_1_GENB_ACTCMPBU_INV 0x00000100 |
| #define PWM_1_GENB_ACTCMPBU_M 0x00000300 |
| #define PWM_1_GENB_ACTCMPBU_NONE 0x00000000 |
| #define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 |
| #define PWM_1_GENB_ACTCMPBU_ZERO 0x00000200 |
| #define PWM_1_GENB_ACTLOAD_INV 0x00000004 |
| #define PWM_1_GENB_ACTLOAD_M 0x0000000C |
| #define PWM_1_GENB_ACTLOAD_NONE 0x00000000 |
| #define PWM_1_GENB_ACTLOAD_ONE 0x0000000C |
| #define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 |
| #define PWM_1_GENB_ACTZERO_INV 0x00000001 |
| #define PWM_1_GENB_ACTZERO_M 0x00000003 |
| #define PWM_1_GENB_ACTZERO_NONE 0x00000000 |
| #define PWM_1_GENB_ACTZERO_ONE 0x00000003 |
| #define PWM_1_GENB_ACTZERO_ZERO 0x00000002 |
| #define PWM_1_INTEN_INTCMPAD 0x00000008 |
| #define PWM_1_INTEN_INTCMPAU 0x00000004 |
| #define PWM_1_INTEN_INTCMPBD 0x00000020 |
| #define PWM_1_INTEN_INTCMPBU 0x00000010 |
| #define PWM_1_INTEN_INTCNTLOAD 0x00000002 |
| #define PWM_1_INTEN_INTCNTZERO 0x00000001 |
| #define PWM_1_INTEN_TRCMPAD 0x00000800 |
| #define PWM_1_INTEN_TRCMPAU 0x00000400 |
| #define PWM_1_INTEN_TRCMPBD 0x00002000 |
| #define PWM_1_INTEN_TRCMPBU 0x00001000 |
| #define PWM_1_INTEN_TRCNTLOAD 0x00000200 |
| #define PWM_1_INTEN_TRCNTZERO 0x00000100 |
| #define PWM_1_ISC_INTCMPAD 0x00000008 |
| #define PWM_1_ISC_INTCMPAU 0x00000004 |
| #define PWM_1_ISC_INTCMPBD 0x00000020 |
| #define PWM_1_ISC_INTCMPBU 0x00000010 |
| #define PWM_1_ISC_INTCNTLOAD 0x00000002 |
| #define PWM_1_ISC_INTCNTZERO 0x00000001 |
| #define PWM_1_LOAD_LOAD_M 0x0000FFFF |
| #define PWM_1_LOAD_LOAD_S 0 |
| #define PWM_1_MINFLTPER_MFP_M 0x0000FFFF |
| #define PWM_1_MINFLTPER_MFP_S 0 |
| #define PWM_1_RIS_INTCMPAD 0x00000008 |
| #define PWM_1_RIS_INTCMPAU 0x00000004 |
| #define PWM_1_RIS_INTCMPBD 0x00000020 |
| #define PWM_1_RIS_INTCMPBU 0x00000010 |
| #define PWM_1_RIS_INTCNTLOAD 0x00000002 |
| #define PWM_1_RIS_INTCNTZERO 0x00000001 |
| #define PWM_2_CMPA_COMPA_M 0x0000FFFF |
| #define PWM_2_CMPA_COMPA_S 0 |
| #define PWM_2_CMPB_COMPB_M 0x0000FFFF |
| #define PWM_2_CMPB_COMPB_S 0 |
| #define PWM_2_COUNT_COUNT_M 0x0000FFFF |
| #define PWM_2_COUNT_COUNT_S 0 |
| #define PWM_2_CTL_CMPAUPD 0x00000010 |
| #define PWM_2_CTL_CMPBUPD 0x00000020 |
| #define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 |
| #define PWM_2_CTL_DBCTLUPD_I 0x00000000 |
| #define PWM_2_CTL_DBCTLUPD_LS 0x00000800 |
| #define PWM_2_CTL_DBCTLUPD_M 0x00000C00 |
| #define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 |
| #define PWM_2_CTL_DBFALLUPD_I 0x00000000 |
| #define PWM_2_CTL_DBFALLUPD_LS 0x00008000 |
| #define PWM_2_CTL_DBFALLUPD_M 0x0000C000 |
| #define PWM_2_CTL_DBRISEUPD_GS 0x00003000 |
| #define PWM_2_CTL_DBRISEUPD_I 0x00000000 |
| #define PWM_2_CTL_DBRISEUPD_LS 0x00002000 |
| #define PWM_2_CTL_DBRISEUPD_M 0x00003000 |
| #define PWM_2_CTL_DEBUG 0x00000004 |
| #define PWM_2_CTL_ENABLE 0x00000001 |
| #define PWM_2_CTL_FLTSRC 0x00010000 |
| #define PWM_2_CTL_GENAUPD_GS 0x000000C0 |
| #define PWM_2_CTL_GENAUPD_I 0x00000000 |
| #define PWM_2_CTL_GENAUPD_LS 0x00000080 |
| #define PWM_2_CTL_GENAUPD_M 0x000000C0 |
| #define PWM_2_CTL_GENBUPD_GS 0x00000300 |
| #define PWM_2_CTL_GENBUPD_I 0x00000000 |
| #define PWM_2_CTL_GENBUPD_LS 0x00000200 |
| #define PWM_2_CTL_GENBUPD_M 0x00000300 |
| #define PWM_2_CTL_LATCH 0x00040000 |
| #define PWM_2_CTL_LOADUPD 0x00000008 |
| #define PWM_2_CTL_MINFLTPER 0x00020000 |
| #define PWM_2_CTL_MODE 0x00000002 |
| #define PWM_2_DBCTL_ENABLE 0x00000001 |
| #define PWM_2_DBFALL_FALLDELAY_M 0x00000FFF |
| #define PWM_2_DBFALL_FALLDELAY_S 0 |
| #define PWM_2_DBRISE_RISEDELAY_M 0x00000FFF |
| #define PWM_2_DBRISE_RISEDELAY_S 0 |
| #define PWM_2_FLTSEN_FAULT0 0x00000001 |
| #define PWM_2_FLTSEN_FAULT1 0x00000002 |
| #define PWM_2_FLTSEN_FAULT2 0x00000004 |
| #define PWM_2_FLTSEN_FAULT3 0x00000008 |
| #define PWM_2_FLTSRC0_FAULT0 0x00000001 |
| #define PWM_2_FLTSRC0_FAULT1 0x00000002 |
| #define PWM_2_FLTSRC0_FAULT2 0x00000004 |
| #define PWM_2_FLTSRC0_FAULT3 0x00000008 |
| #define PWM_2_FLTSRC1_DCMP0 0x00000001 |
| #define PWM_2_FLTSRC1_DCMP1 0x00000002 |
| #define PWM_2_FLTSRC1_DCMP2 0x00000004 |
| #define PWM_2_FLTSRC1_DCMP3 0x00000008 |
| #define PWM_2_FLTSRC1_DCMP4 0x00000010 |
| #define PWM_2_FLTSRC1_DCMP5 0x00000020 |
| #define PWM_2_FLTSRC1_DCMP6 0x00000040 |
| #define PWM_2_FLTSRC1_DCMP7 0x00000080 |
| #define PWM_2_FLTSTAT0_FAULT0 0x00000001 |
| #define PWM_2_FLTSTAT0_FAULT1 0x00000002 |
| #define PWM_2_FLTSTAT0_FAULT2 0x00000004 |
| #define PWM_2_FLTSTAT0_FAULT3 0x00000008 |
| #define PWM_2_FLTSTAT1_DCMP0 0x00000001 |
| #define PWM_2_FLTSTAT1_DCMP1 0x00000002 |
| #define PWM_2_FLTSTAT1_DCMP2 0x00000004 |
| #define PWM_2_FLTSTAT1_DCMP3 0x00000008 |
| #define PWM_2_FLTSTAT1_DCMP4 0x00000010 |
| #define PWM_2_FLTSTAT1_DCMP5 0x00000020 |
| #define PWM_2_FLTSTAT1_DCMP6 0x00000040 |
| #define PWM_2_FLTSTAT1_DCMP7 0x00000080 |
| #define PWM_2_GENA_ACTCMPAD_INV 0x00000040 |
| #define PWM_2_GENA_ACTCMPAD_M 0x000000C0 |
| #define PWM_2_GENA_ACTCMPAD_NONE 0x00000000 |
| #define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 |
| #define PWM_2_GENA_ACTCMPAD_ZERO 0x00000080 |
| #define PWM_2_GENA_ACTCMPAU_INV 0x00000010 |
| #define PWM_2_GENA_ACTCMPAU_M 0x00000030 |
| #define PWM_2_GENA_ACTCMPAU_NONE 0x00000000 |
| #define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 |
| #define PWM_2_GENA_ACTCMPAU_ZERO 0x00000020 |
| #define PWM_2_GENA_ACTCMPBD_INV 0x00000400 |
| #define PWM_2_GENA_ACTCMPBD_M 0x00000C00 |
| #define PWM_2_GENA_ACTCMPBD_NONE 0x00000000 |
| #define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 |
| #define PWM_2_GENA_ACTCMPBD_ZERO 0x00000800 |
| #define PWM_2_GENA_ACTCMPBU_INV 0x00000100 |
| #define PWM_2_GENA_ACTCMPBU_M 0x00000300 |
| #define PWM_2_GENA_ACTCMPBU_NONE 0x00000000 |
| #define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 |
| #define PWM_2_GENA_ACTCMPBU_ZERO 0x00000200 |
| #define PWM_2_GENA_ACTLOAD_INV 0x00000004 |
| #define PWM_2_GENA_ACTLOAD_M 0x0000000C |
| #define PWM_2_GENA_ACTLOAD_NONE 0x00000000 |
| #define PWM_2_GENA_ACTLOAD_ONE 0x0000000C |
| #define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 |
| #define PWM_2_GENA_ACTZERO_INV 0x00000001 |
| #define PWM_2_GENA_ACTZERO_M 0x00000003 |
| #define PWM_2_GENA_ACTZERO_NONE 0x00000000 |
| #define PWM_2_GENA_ACTZERO_ONE 0x00000003 |
| #define PWM_2_GENA_ACTZERO_ZERO 0x00000002 |
| #define PWM_2_GENB_ACTCMPAD_INV 0x00000040 |
| #define PWM_2_GENB_ACTCMPAD_M 0x000000C0 |
| #define PWM_2_GENB_ACTCMPAD_NONE 0x00000000 |
| #define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 |
| #define PWM_2_GENB_ACTCMPAD_ZERO 0x00000080 |
| #define PWM_2_GENB_ACTCMPAU_INV 0x00000010 |
| #define PWM_2_GENB_ACTCMPAU_M 0x00000030 |
| #define PWM_2_GENB_ACTCMPAU_NONE 0x00000000 |
| #define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 |
| #define PWM_2_GENB_ACTCMPAU_ZERO 0x00000020 |
| #define PWM_2_GENB_ACTCMPBD_INV 0x00000400 |
| #define PWM_2_GENB_ACTCMPBD_M 0x00000C00 |
| #define PWM_2_GENB_ACTCMPBD_NONE 0x00000000 |
| #define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 |
| #define PWM_2_GENB_ACTCMPBD_ZERO 0x00000800 |
| #define PWM_2_GENB_ACTCMPBU_INV 0x00000100 |
| #define PWM_2_GENB_ACTCMPBU_M 0x00000300 |
| #define PWM_2_GENB_ACTCMPBU_NONE 0x00000000 |
| #define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 |
| #define PWM_2_GENB_ACTCMPBU_ZERO 0x00000200 |
| #define PWM_2_GENB_ACTLOAD_INV 0x00000004 |
| #define PWM_2_GENB_ACTLOAD_M 0x0000000C |
| #define PWM_2_GENB_ACTLOAD_NONE 0x00000000 |
| #define PWM_2_GENB_ACTLOAD_ONE 0x0000000C |
| #define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 |
| #define PWM_2_GENB_ACTZERO_INV 0x00000001 |
| #define PWM_2_GENB_ACTZERO_M 0x00000003 |
| #define PWM_2_GENB_ACTZERO_NONE 0x00000000 |
| #define PWM_2_GENB_ACTZERO_ONE 0x00000003 |
| #define PWM_2_GENB_ACTZERO_ZERO 0x00000002 |
| #define PWM_2_INTEN_INTCMPAD 0x00000008 |
| #define PWM_2_INTEN_INTCMPAU 0x00000004 |
| #define PWM_2_INTEN_INTCMPBD 0x00000020 |
| #define PWM_2_INTEN_INTCMPBU 0x00000010 |
| #define PWM_2_INTEN_INTCNTLOAD 0x00000002 |
| #define PWM_2_INTEN_INTCNTZERO 0x00000001 |
| #define PWM_2_INTEN_TRCMPAD 0x00000800 |
| #define PWM_2_INTEN_TRCMPAU 0x00000400 |
| #define PWM_2_INTEN_TRCMPBD 0x00002000 |
| #define PWM_2_INTEN_TRCMPBU 0x00001000 |
| #define PWM_2_INTEN_TRCNTLOAD 0x00000200 |
| #define PWM_2_INTEN_TRCNTZERO 0x00000100 |
| #define PWM_2_ISC_INTCMPAD 0x00000008 |
| #define PWM_2_ISC_INTCMPAU 0x00000004 |
| #define PWM_2_ISC_INTCMPBD 0x00000020 |
| #define PWM_2_ISC_INTCMPBU 0x00000010 |
| #define PWM_2_ISC_INTCNTLOAD 0x00000002 |
| #define PWM_2_ISC_INTCNTZERO 0x00000001 |
| #define PWM_2_LOAD_LOAD_M 0x0000FFFF |
| #define PWM_2_LOAD_LOAD_S 0 |
| #define PWM_2_MINFLTPER_MFP_M 0x0000FFFF |
| #define PWM_2_MINFLTPER_MFP_S 0 |
| #define PWM_2_RIS_INTCMPAD 0x00000008 |
| #define PWM_2_RIS_INTCMPAU 0x00000004 |
| #define PWM_2_RIS_INTCMPBD 0x00000020 |
| #define PWM_2_RIS_INTCMPBU 0x00000010 |
| #define PWM_2_RIS_INTCNTLOAD 0x00000002 |
| #define PWM_2_RIS_INTCNTZERO 0x00000001 |
| #define PWM_3_CMPA_COMPA_M 0x0000FFFF |
| #define PWM_3_CMPA_COMPA_S 0 |
| #define PWM_3_CMPB_COMPB_M 0x0000FFFF |
| #define PWM_3_CMPB_COMPB_S 0 |
| #define PWM_3_COUNT_COUNT_M 0x0000FFFF |
| #define PWM_3_COUNT_COUNT_S 0 |
| #define PWM_3_CTL_CMPAUPD 0x00000010 |
| #define PWM_3_CTL_CMPBUPD 0x00000020 |
| #define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 |
| #define PWM_3_CTL_DBCTLUPD_I 0x00000000 |
| #define PWM_3_CTL_DBCTLUPD_LS 0x00000800 |
| #define PWM_3_CTL_DBCTLUPD_M 0x00000C00 |
| #define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 |
| #define PWM_3_CTL_DBFALLUPD_I 0x00000000 |
| #define PWM_3_CTL_DBFALLUPD_LS 0x00008000 |
| #define PWM_3_CTL_DBFALLUPD_M 0x0000C000 |
| #define PWM_3_CTL_DBRISEUPD_GS 0x00003000 |
| #define PWM_3_CTL_DBRISEUPD_I 0x00000000 |
| #define PWM_3_CTL_DBRISEUPD_LS 0x00002000 |
| #define PWM_3_CTL_DBRISEUPD_M 0x00003000 |
| #define PWM_3_CTL_DEBUG 0x00000004 |
| #define PWM_3_CTL_ENABLE 0x00000001 |
| #define PWM_3_CTL_FLTSRC 0x00010000 |
| #define PWM_3_CTL_GENAUPD_GS 0x000000C0 |
| #define PWM_3_CTL_GENAUPD_I 0x00000000 |
| #define PWM_3_CTL_GENAUPD_LS 0x00000080 |
| #define PWM_3_CTL_GENAUPD_M 0x000000C0 |
| #define PWM_3_CTL_GENBUPD_GS 0x00000300 |
| #define PWM_3_CTL_GENBUPD_I 0x00000000 |
| #define PWM_3_CTL_GENBUPD_LS 0x00000200 |
| #define PWM_3_CTL_GENBUPD_M 0x00000300 |
| #define PWM_3_CTL_LATCH 0x00040000 |
| #define PWM_3_CTL_LOADUPD 0x00000008 |
| #define PWM_3_CTL_MINFLTPER 0x00020000 |
| #define PWM_3_CTL_MODE 0x00000002 |
| #define PWM_3_DBCTL_ENABLE 0x00000001 |
| #define PWM_3_DBFALL_FALLDELAY_M 0x00000FFF |
| #define PWM_3_DBFALL_FALLDELAY_S 0 |
| #define PWM_3_DBRISE_RISEDELAY_M 0x00000FFF |
| #define PWM_3_DBRISE_RISEDELAY_S 0 |
| #define PWM_3_FLTSEN_FAULT0 0x00000001 |
| #define PWM_3_FLTSEN_FAULT1 0x00000002 |
| #define PWM_3_FLTSEN_FAULT2 0x00000004 |
| #define PWM_3_FLTSEN_FAULT3 0x00000008 |
| #define PWM_3_FLTSRC0_FAULT0 0x00000001 |
| #define PWM_3_FLTSRC0_FAULT1 0x00000002 |
| #define PWM_3_FLTSRC0_FAULT2 0x00000004 |
| #define PWM_3_FLTSRC0_FAULT3 0x00000008 |
| #define PWM_3_FLTSRC1_DCMP0 0x00000001 |
| #define PWM_3_FLTSRC1_DCMP1 0x00000002 |
| #define PWM_3_FLTSRC1_DCMP2 0x00000004 |
| #define PWM_3_FLTSRC1_DCMP3 0x00000008 |
| #define PWM_3_FLTSRC1_DCMP4 0x00000010 |
| #define PWM_3_FLTSRC1_DCMP5 0x00000020 |
| #define PWM_3_FLTSRC1_DCMP6 0x00000040 |
| #define PWM_3_FLTSRC1_DCMP7 0x00000080 |
| #define PWM_3_FLTSTAT0_FAULT0 0x00000001 |
| #define PWM_3_FLTSTAT0_FAULT1 0x00000002 |
| #define PWM_3_FLTSTAT0_FAULT2 0x00000004 |
| #define PWM_3_FLTSTAT0_FAULT3 0x00000008 |
| #define PWM_3_FLTSTAT1_DCMP0 0x00000001 |
| #define PWM_3_FLTSTAT1_DCMP1 0x00000002 |
| #define PWM_3_FLTSTAT1_DCMP2 0x00000004 |
| #define PWM_3_FLTSTAT1_DCMP3 0x00000008 |
| #define PWM_3_FLTSTAT1_DCMP4 0x00000010 |
| #define PWM_3_FLTSTAT1_DCMP5 0x00000020 |
| #define PWM_3_FLTSTAT1_DCMP6 0x00000040 |
| #define PWM_3_FLTSTAT1_DCMP7 0x00000080 |
| #define PWM_3_GENA_ACTCMPAD_INV 0x00000040 |
| #define PWM_3_GENA_ACTCMPAD_M 0x000000C0 |
| #define PWM_3_GENA_ACTCMPAD_NONE 0x00000000 |
| #define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 |
| #define PWM_3_GENA_ACTCMPAD_ZERO 0x00000080 |
| #define PWM_3_GENA_ACTCMPAU_INV 0x00000010 |
| #define PWM_3_GENA_ACTCMPAU_M 0x00000030 |
| #define PWM_3_GENA_ACTCMPAU_NONE 0x00000000 |
| #define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 |
| #define PWM_3_GENA_ACTCMPAU_ZERO 0x00000020 |
| #define PWM_3_GENA_ACTCMPBD_INV 0x00000400 |
| #define PWM_3_GENA_ACTCMPBD_M 0x00000C00 |
| #define PWM_3_GENA_ACTCMPBD_NONE 0x00000000 |
| #define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 |
| #define PWM_3_GENA_ACTCMPBD_ZERO 0x00000800 |
| #define PWM_3_GENA_ACTCMPBU_INV 0x00000100 |
| #define PWM_3_GENA_ACTCMPBU_M 0x00000300 |
| #define PWM_3_GENA_ACTCMPBU_NONE 0x00000000 |
| #define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 |
| #define PWM_3_GENA_ACTCMPBU_ZERO 0x00000200 |
| #define PWM_3_GENA_ACTLOAD_INV 0x00000004 |
| #define PWM_3_GENA_ACTLOAD_M 0x0000000C |
| #define PWM_3_GENA_ACTLOAD_NONE 0x00000000 |
| #define PWM_3_GENA_ACTLOAD_ONE 0x0000000C |
| #define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 |
| #define PWM_3_GENA_ACTZERO_INV 0x00000001 |
| #define PWM_3_GENA_ACTZERO_M 0x00000003 |
| #define PWM_3_GENA_ACTZERO_NONE 0x00000000 |
| #define PWM_3_GENA_ACTZERO_ONE 0x00000003 |
| #define PWM_3_GENA_ACTZERO_ZERO 0x00000002 |
| #define PWM_3_GENB_ACTCMPAD_INV 0x00000040 |
| #define PWM_3_GENB_ACTCMPAD_M 0x000000C0 |
| #define PWM_3_GENB_ACTCMPAD_NONE 0x00000000 |
| #define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 |
| #define PWM_3_GENB_ACTCMPAD_ZERO 0x00000080 |
| #define PWM_3_GENB_ACTCMPAU_INV 0x00000010 |
| #define PWM_3_GENB_ACTCMPAU_M 0x00000030 |
| #define PWM_3_GENB_ACTCMPAU_NONE 0x00000000 |
| #define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 |
| #define PWM_3_GENB_ACTCMPAU_ZERO 0x00000020 |
| #define PWM_3_GENB_ACTCMPBD_INV 0x00000400 |
| #define PWM_3_GENB_ACTCMPBD_M 0x00000C00 |
| #define PWM_3_GENB_ACTCMPBD_NONE 0x00000000 |
| #define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 |
| #define PWM_3_GENB_ACTCMPBD_ZERO 0x00000800 |
| #define PWM_3_GENB_ACTCMPBU_INV 0x00000100 |
| #define PWM_3_GENB_ACTCMPBU_M 0x00000300 |
| #define PWM_3_GENB_ACTCMPBU_NONE 0x00000000 |
| #define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 |
| #define PWM_3_GENB_ACTCMPBU_ZERO 0x00000200 |
| #define PWM_3_GENB_ACTLOAD_INV 0x00000004 |
| #define PWM_3_GENB_ACTLOAD_M 0x0000000C |
| #define PWM_3_GENB_ACTLOAD_NONE 0x00000000 |
| #define PWM_3_GENB_ACTLOAD_ONE 0x0000000C |
| #define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 |
| #define PWM_3_GENB_ACTZERO_INV 0x00000001 |
| #define PWM_3_GENB_ACTZERO_M 0x00000003 |
| #define PWM_3_GENB_ACTZERO_NONE 0x00000000 |
| #define PWM_3_GENB_ACTZERO_ONE 0x00000003 |
| #define PWM_3_GENB_ACTZERO_ZERO 0x00000002 |
| #define PWM_3_INTEN_INTCMPAD 0x00000008 |
| #define PWM_3_INTEN_INTCMPAU 0x00000004 |
| #define PWM_3_INTEN_INTCMPBD 0x00000020 |
| #define PWM_3_INTEN_INTCMPBU 0x00000010 |
| #define PWM_3_INTEN_INTCNTLOAD 0x00000002 |
| #define PWM_3_INTEN_INTCNTZERO 0x00000001 |
| #define PWM_3_INTEN_TRCMPAD 0x00000800 |
| #define PWM_3_INTEN_TRCMPAU 0x00000400 |
| #define PWM_3_INTEN_TRCMPBD 0x00002000 |
| #define PWM_3_INTEN_TRCMPBU 0x00001000 |
| #define PWM_3_INTEN_TRCNTLOAD 0x00000200 |
| #define PWM_3_INTEN_TRCNTZERO 0x00000100 |
| #define PWM_3_ISC_INTCMPAD 0x00000008 |
| #define PWM_3_ISC_INTCMPAU 0x00000004 |
| #define PWM_3_ISC_INTCMPBD 0x00000020 |
| #define PWM_3_ISC_INTCMPBU 0x00000010 |
| #define PWM_3_ISC_INTCNTLOAD 0x00000002 |
| #define PWM_3_ISC_INTCNTZERO 0x00000001 |
| #define PWM_3_LOAD_LOAD_M 0x0000FFFF |
| #define PWM_3_LOAD_LOAD_S 0 |
| #define PWM_3_MINFLTPER_MFP_M 0x0000FFFF |
| #define PWM_3_MINFLTPER_MFP_S 0 |
| #define PWM_3_RIS_INTCMPAD 0x00000008 |
| #define PWM_3_RIS_INTCMPAU 0x00000004 |
| #define PWM_3_RIS_INTCMPBD 0x00000020 |
| #define PWM_3_RIS_INTCMPBU 0x00000010 |
| #define PWM_3_RIS_INTCNTLOAD 0x00000002 |
| #define PWM_3_RIS_INTCNTZERO 0x00000001 |
| #define PWM_CTL_GLOBALSYNC0 0x00000001 |
| #define PWM_CTL_GLOBALSYNC1 0x00000002 |
| #define PWM_CTL_GLOBALSYNC2 0x00000004 |
| #define PWM_CTL_GLOBALSYNC3 0x00000008 |
| #define PWM_ENABLE_PWM0EN 0x00000001 |
| #define PWM_ENABLE_PWM1EN 0x00000002 |
| #define PWM_ENABLE_PWM2EN 0x00000004 |
| #define PWM_ENABLE_PWM3EN 0x00000008 |
| #define PWM_ENABLE_PWM4EN 0x00000010 |
| #define PWM_ENABLE_PWM5EN 0x00000020 |
| #define PWM_ENABLE_PWM6EN 0x00000040 |
| #define PWM_ENABLE_PWM7EN 0x00000080 |
| #define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 |
| #define PWM_ENUPD_ENUPD0_IMM 0x00000000 |
| #define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 |
| #define PWM_ENUPD_ENUPD0_M 0x00000003 |
| #define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C |
| #define PWM_ENUPD_ENUPD1_IMM 0x00000000 |
| #define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 |
| #define PWM_ENUPD_ENUPD1_M 0x0000000C |
| #define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 |
| #define PWM_ENUPD_ENUPD2_IMM 0x00000000 |
| #define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 |
| #define PWM_ENUPD_ENUPD2_M 0x00000030 |
| #define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 |
| #define PWM_ENUPD_ENUPD3_IMM 0x00000000 |
| #define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 |
| #define PWM_ENUPD_ENUPD3_M 0x000000C0 |
| #define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 |
| #define PWM_ENUPD_ENUPD4_IMM 0x00000000 |
| #define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 |
| #define PWM_ENUPD_ENUPD4_M 0x00000300 |
| #define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 |
| #define PWM_ENUPD_ENUPD5_IMM 0x00000000 |
| #define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 |
| #define PWM_ENUPD_ENUPD5_M 0x00000C00 |
| #define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 |
| #define PWM_ENUPD_ENUPD6_IMM 0x00000000 |
| #define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 |
| #define PWM_ENUPD_ENUPD6_M 0x00003000 |
| #define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 |
| #define PWM_ENUPD_ENUPD7_IMM 0x00000000 |
| #define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 |
| #define PWM_ENUPD_ENUPD7_M 0x0000C000 |
| #define PWM_FAULT_FAULT0 0x00000001 |
| #define PWM_FAULT_FAULT1 0x00000002 |
| #define PWM_FAULT_FAULT2 0x00000004 |
| #define PWM_FAULT_FAULT3 0x00000008 |
| #define PWM_FAULT_FAULT4 0x00000010 |
| #define PWM_FAULT_FAULT5 0x00000020 |
| #define PWM_FAULT_FAULT6 0x00000040 |
| #define PWM_FAULT_FAULT7 0x00000080 |
| #define PWM_FAULTVAL_PWM0 0x00000001 |
| #define PWM_FAULTVAL_PWM1 0x00000002 |
| #define PWM_FAULTVAL_PWM2 0x00000004 |
| #define PWM_FAULTVAL_PWM3 0x00000008 |
| #define PWM_FAULTVAL_PWM4 0x00000010 |
| #define PWM_FAULTVAL_PWM5 0x00000020 |
| #define PWM_FAULTVAL_PWM6 0x00000040 |
| #define PWM_FAULTVAL_PWM7 0x00000080 |
| #define PWM_INTEN_INTFAULT0 0x00010000 |
| #define PWM_INTEN_INTFAULT1 0x00020000 |
| #define PWM_INTEN_INTFAULT2 0x00040000 |
| #define PWM_INTEN_INTFAULT3 0x00080000 |
| #define PWM_INTEN_INTPWM0 0x00000001 |
| #define PWM_INTEN_INTPWM1 0x00000002 |
| #define PWM_INTEN_INTPWM2 0x00000004 |
| #define PWM_INTEN_INTPWM3 0x00000008 |
| #define PWM_INVERT_PWM0INV 0x00000001 |
| #define PWM_INVERT_PWM1INV 0x00000002 |
| #define PWM_INVERT_PWM2INV 0x00000004 |
| #define PWM_INVERT_PWM3INV 0x00000008 |
| #define PWM_INVERT_PWM4INV 0x00000010 |
| #define PWM_INVERT_PWM5INV 0x00000020 |
| #define PWM_INVERT_PWM6INV 0x00000040 |
| #define PWM_INVERT_PWM7INV 0x00000080 |
| #define PWM_ISC_INTFAULT0 0x00010000 |
| #define PWM_ISC_INTFAULT1 0x00020000 |
| #define PWM_ISC_INTFAULT2 0x00040000 |
| #define PWM_ISC_INTFAULT3 0x00080000 |
| #define PWM_ISC_INTPWM0 0x00000001 |
| #define PWM_ISC_INTPWM1 0x00000002 |
| #define PWM_ISC_INTPWM2 0x00000004 |
| #define PWM_ISC_INTPWM3 0x00000008 |
| #define PWM_PP_EFAULT 0x00000200 |
| #define PWM_PP_ESYNC 0x00000100 |
| #define PWM_PP_FCNT_M 0x000000F0 |
| #define PWM_PP_FCNT_S 4 |
| #define PWM_PP_GCNT_M 0x0000000F |
| #define PWM_PP_GCNT_S 0 |
| #define PWM_PP_ONE 0x00000400 |
| #define PWM_RIS_INTFAULT0 0x00010000 |
| #define PWM_RIS_INTFAULT1 0x00020000 |
| #define PWM_RIS_INTFAULT2 0x00040000 |
| #define PWM_RIS_INTFAULT3 0x00080000 |
| #define PWM_RIS_INTPWM0 0x00000001 |
| #define PWM_RIS_INTPWM1 0x00000002 |
| #define PWM_RIS_INTPWM2 0x00000004 |
| #define PWM_RIS_INTPWM3 0x00000008 |
| #define PWM_STATUS_FAULT0 0x00000001 |
| #define PWM_STATUS_FAULT1 0x00000002 |
| #define PWM_STATUS_FAULT2 0x00000004 |
| #define PWM_STATUS_FAULT3 0x00000008 |
| #define PWM_SYNC_SYNC0 0x00000001 |
| #define PWM_SYNC_SYNC1 0x00000002 |
| #define PWM_SYNC_SYNC2 0x00000004 |
| #define PWM_SYNC_SYNC3 0x00000008 |
| #define QEI0_COUNT_R (*((volatile uint32_t *)0x4002C018)) |
| #define QEI0_CTL_R (*((volatile uint32_t *)0x4002C000)) |
| #define QEI0_INTEN_R (*((volatile uint32_t *)0x4002C020)) |
| #define QEI0_ISC_R (*((volatile uint32_t *)0x4002C028)) |
| #define QEI0_LOAD_R (*((volatile uint32_t *)0x4002C010)) |
| #define QEI0_MAXPOS_R (*((volatile uint32_t *)0x4002C00C)) |
| #define QEI0_POS_R (*((volatile uint32_t *)0x4002C008)) |
| #define QEI0_RIS_R (*((volatile uint32_t *)0x4002C024)) |
| #define QEI0_SPEED_R (*((volatile uint32_t *)0x4002C01C)) |
| #define QEI0_STAT_R (*((volatile uint32_t *)0x4002C004)) |
| #define QEI0_TIME_R (*((volatile uint32_t *)0x4002C014)) |
| #define QEI1_COUNT_R (*((volatile uint32_t *)0x4002D018)) |
| #define QEI1_CTL_R (*((volatile uint32_t *)0x4002D000)) |
| #define QEI1_INTEN_R (*((volatile uint32_t *)0x4002D020)) |
| #define QEI1_ISC_R (*((volatile uint32_t *)0x4002D028)) |
| #define QEI1_LOAD_R (*((volatile uint32_t *)0x4002D010)) |
| #define QEI1_MAXPOS_R (*((volatile uint32_t *)0x4002D00C)) |
| #define QEI1_POS_R (*((volatile uint32_t *)0x4002D008)) |
| #define QEI1_RIS_R (*((volatile uint32_t *)0x4002D024)) |
| #define QEI1_SPEED_R (*((volatile uint32_t *)0x4002D01C)) |
| #define QEI1_STAT_R (*((volatile uint32_t *)0x4002D004)) |
| #define QEI1_TIME_R (*((volatile uint32_t *)0x4002D014)) |
| #define QEI_COUNT_M 0xFFFFFFFF |
| #define QEI_COUNT_S 0 |
| #define QEI_CTL_CAPMODE 0x00000008 |
| #define QEI_CTL_ENABLE 0x00000001 |
| #define QEI_CTL_FILTCNT_M 0x000F0000 |
| #define QEI_CTL_FILTCNT_S 16 |
| #define QEI_CTL_FILTEN 0x00002000 |
| #define QEI_CTL_INVA 0x00000200 |
| #define QEI_CTL_INVB 0x00000400 |
| #define QEI_CTL_INVI 0x00000800 |
| #define QEI_CTL_RESMODE 0x00000010 |
| #define QEI_CTL_SIGMODE 0x00000004 |
| #define QEI_CTL_STALLEN 0x00001000 |
| #define QEI_CTL_SWAP 0x00000002 |
| #define QEI_CTL_VELDIV_1 0x00000000 |
| #define QEI_CTL_VELDIV_128 0x000001C0 |
| #define QEI_CTL_VELDIV_16 0x00000100 |
| #define QEI_CTL_VELDIV_2 0x00000040 |
| #define QEI_CTL_VELDIV_32 0x00000140 |
| #define QEI_CTL_VELDIV_4 0x00000080 |
| #define QEI_CTL_VELDIV_64 0x00000180 |
| #define QEI_CTL_VELDIV_8 0x000000C0 |
| #define QEI_CTL_VELDIV_M 0x000001C0 |
| #define QEI_CTL_VELEN 0x00000020 |
| #define QEI_INTEN_DIR 0x00000004 |
| #define QEI_INTEN_ERROR 0x00000008 |
| #define QEI_INTEN_INDEX 0x00000001 |
| #define QEI_INTEN_TIMER 0x00000002 |
| #define QEI_ISC_DIR 0x00000004 |
| #define QEI_ISC_ERROR 0x00000008 |
| #define QEI_ISC_INDEX 0x00000001 |
| #define QEI_ISC_TIMER 0x00000002 |
| #define QEI_LOAD_M 0xFFFFFFFF |
| #define QEI_LOAD_S 0 |
| #define QEI_MAXPOS_M 0xFFFFFFFF |
| #define QEI_MAXPOS_S 0 |
| #define QEI_POS_M 0xFFFFFFFF |
| #define QEI_POS_S 0 |
| #define QEI_RIS_DIR 0x00000004 |
| #define QEI_RIS_ERROR 0x00000008 |
| #define QEI_RIS_INDEX 0x00000001 |
| #define QEI_RIS_TIMER 0x00000002 |
| #define QEI_SPEED_M 0xFFFFFFFF |
| #define QEI_SPEED_S 0 |
| #define QEI_STAT_DIRECTION 0x00000002 |
| #define QEI_STAT_ERROR 0x00000001 |
| #define QEI_TIME_M 0xFFFFFFFF |
| #define QEI_TIME_S 0 |
| #define SSI0_CC_R (*((volatile uint32_t *)0x40008FC8)) |
| #define SSI0_CPSR_R (*((volatile uint32_t *)0x40008010)) |
| #define SSI0_CR0_R (*((volatile uint32_t *)0x40008000)) |
| #define SSI0_CR1_R (*((volatile uint32_t *)0x40008004)) |
| #define SSI0_DMACTL_R (*((volatile uint32_t *)0x40008024)) |
| #define SSI0_DR_R (*((volatile uint32_t *)0x40008008)) |
| #define SSI0_ICR_R (*((volatile uint32_t *)0x40008020)) |
| #define SSI0_IM_R (*((volatile uint32_t *)0x40008014)) |
| #define SSI0_MIS_R (*((volatile uint32_t *)0x4000801C)) |
| #define SSI0_RIS_R (*((volatile uint32_t *)0x40008018)) |
| #define SSI0_SR_R (*((volatile uint32_t *)0x4000800C)) |
| #define SSI1_CC_R (*((volatile uint32_t *)0x40009FC8)) |
| #define SSI1_CPSR_R (*((volatile uint32_t *)0x40009010)) |
| #define SSI1_CR0_R (*((volatile uint32_t *)0x40009000)) |
| #define SSI1_CR1_R (*((volatile uint32_t *)0x40009004)) |
| #define SSI1_DMACTL_R (*((volatile uint32_t *)0x40009024)) |
| #define SSI1_DR_R (*((volatile uint32_t *)0x40009008)) |
| #define SSI1_ICR_R (*((volatile uint32_t *)0x40009020)) |
| #define SSI1_IM_R (*((volatile uint32_t *)0x40009014)) |
| #define SSI1_MIS_R (*((volatile uint32_t *)0x4000901C)) |
| #define SSI1_RIS_R (*((volatile uint32_t *)0x40009018)) |
| #define SSI1_SR_R (*((volatile uint32_t *)0x4000900C)) |
| #define SSI2_CC_R (*((volatile uint32_t *)0x4000AFC8)) |
| #define SSI2_CPSR_R (*((volatile uint32_t *)0x4000A010)) |
| #define SSI2_CR0_R (*((volatile uint32_t *)0x4000A000)) |
| #define SSI2_CR1_R (*((volatile uint32_t *)0x4000A004)) |
| #define SSI2_DMACTL_R (*((volatile uint32_t *)0x4000A024)) |
| #define SSI2_DR_R (*((volatile uint32_t *)0x4000A008)) |
| #define SSI2_ICR_R (*((volatile uint32_t *)0x4000A020)) |
| #define SSI2_IM_R (*((volatile uint32_t *)0x4000A014)) |
| #define SSI2_MIS_R (*((volatile uint32_t *)0x4000A01C)) |
| #define SSI2_RIS_R (*((volatile uint32_t *)0x4000A018)) |
| #define SSI2_SR_R (*((volatile uint32_t *)0x4000A00C)) |
| #define SSI3_CC_R (*((volatile uint32_t *)0x4000BFC8)) |
| #define SSI3_CPSR_R (*((volatile uint32_t *)0x4000B010)) |
| #define SSI3_CR0_R (*((volatile uint32_t *)0x4000B000)) |
| #define SSI3_CR1_R (*((volatile uint32_t *)0x4000B004)) |
| #define SSI3_DMACTL_R (*((volatile uint32_t *)0x4000B024)) |
| #define SSI3_DR_R (*((volatile uint32_t *)0x4000B008)) |
| #define SSI3_ICR_R (*((volatile uint32_t *)0x4000B020)) |
| #define SSI3_IM_R (*((volatile uint32_t *)0x4000B014)) |
| #define SSI3_MIS_R (*((volatile uint32_t *)0x4000B01C)) |
| #define SSI3_RIS_R (*((volatile uint32_t *)0x4000B018)) |
| #define SSI3_SR_R (*((volatile uint32_t *)0x4000B00C)) |
| #define SSI_CC_CS_M 0x0000000F |
| #define SSI_CC_CS_PIOSC 0x00000005 |
| #define SSI_CC_CS_SYSPLL 0x00000000 |
| #define SSI_CPSR_CPSDVSR_M 0x000000FF |
| #define SSI_CPSR_CPSDVSR_S 0 |
| #define SSI_CR0_DSS_10 0x00000009 |
| #define SSI_CR0_DSS_11 0x0000000A |
| #define SSI_CR0_DSS_12 0x0000000B |
| #define SSI_CR0_DSS_13 0x0000000C |
| #define SSI_CR0_DSS_14 0x0000000D |
| #define SSI_CR0_DSS_15 0x0000000E |
| #define SSI_CR0_DSS_16 0x0000000F |
| #define SSI_CR0_DSS_4 0x00000003 |
| #define SSI_CR0_DSS_5 0x00000004 |
| #define SSI_CR0_DSS_6 0x00000005 |
| #define SSI_CR0_DSS_7 0x00000006 |
| #define SSI_CR0_DSS_8 0x00000007 |
| #define SSI_CR0_DSS_9 0x00000008 |
| #define SSI_CR0_DSS_M 0x0000000F |
| #define SSI_CR0_FRF_M 0x00000030 |
| #define SSI_CR0_FRF_MOTO 0x00000000 |
| #define SSI_CR0_FRF_NMW 0x00000020 |
| #define SSI_CR0_FRF_TI 0x00000010 |
| #define SSI_CR0_SCR_M 0x0000FF00 |
| #define SSI_CR0_SCR_S 8 |
| #define SSI_CR0_SPH 0x00000080 |
| #define SSI_CR0_SPO 0x00000040 |
| #define SSI_CR1_EOT 0x00000010 |
| #define SSI_CR1_LBM 0x00000001 |
| #define SSI_CR1_MS 0x00000004 |
| #define SSI_CR1_SSE 0x00000002 |
| #define SSI_DMACTL_RXDMAE 0x00000001 |
| #define SSI_DMACTL_TXDMAE 0x00000002 |
| #define SSI_DR_DATA_M 0x0000FFFF |
| #define SSI_DR_DATA_S 0 |
| #define SSI_ICR_RORIC 0x00000001 |
| #define SSI_ICR_RTIC 0x00000002 |
| #define SSI_IM_RORIM 0x00000001 |
| #define SSI_IM_RTIM 0x00000002 |
| #define SSI_IM_RXIM 0x00000004 |
| #define SSI_IM_TXIM 0x00000008 |
| #define SSI_MIS_RORMIS 0x00000001 |
| #define SSI_MIS_RTMIS 0x00000002 |
| #define SSI_MIS_RXMIS 0x00000004 |
| #define SSI_MIS_TXMIS 0x00000008 |
| #define SSI_RIS_RORRIS 0x00000001 |
| #define SSI_RIS_RTRIS 0x00000002 |
| #define SSI_RIS_RXRIS 0x00000004 |
| #define SSI_RIS_TXRIS 0x00000008 |
| #define SSI_SR_BSY 0x00000010 |
| #define SSI_SR_RFF 0x00000008 |
| #define SSI_SR_RNE 0x00000004 |
| #define SSI_SR_TFE 0x00000001 |
| #define SSI_SR_TNF 0x00000002 |
| #define SYSCTL_DC0_FLASHSZ_128K 0x0000003F |
| #define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 |
| #define SYSCTL_DC0_FLASHSZ_192K 0x0000005F |
| #define SYSCTL_DC0_FLASHSZ_256K 0x0000007F |
| #define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F |
| #define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F |
| #define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 |
| #define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F |
| #define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF |
| #define SYSCTL_DC0_R (*((volatile uint32_t *)0x400FE008)) |
| #define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 |
| #define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 |
| #define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 |
| #define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 |
| #define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 |
| #define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 |
| #define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 |
| #define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 |
| #define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 |
| #define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 |
| #define SYSCTL_DC1_ADC0 0x00010000 |
| #define SYSCTL_DC1_ADC0SPD_125K 0x00000000 |
| #define SYSCTL_DC1_ADC0SPD_1M 0x00000300 |
| #define SYSCTL_DC1_ADC0SPD_250K 0x00000100 |
| #define SYSCTL_DC1_ADC0SPD_500K 0x00000200 |
| #define SYSCTL_DC1_ADC0SPD_M 0x00000300 |
| #define SYSCTL_DC1_ADC1 0x00020000 |
| #define SYSCTL_DC1_ADC1SPD_125K 0x00000000 |
| #define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 |
| #define SYSCTL_DC1_ADC1SPD_250K 0x00000400 |
| #define SYSCTL_DC1_ADC1SPD_500K 0x00000800 |
| #define SYSCTL_DC1_ADC1SPD_M 0x00000C00 |
| #define SYSCTL_DC1_CAN0 0x01000000 |
| #define SYSCTL_DC1_CAN1 0x02000000 |
| #define SYSCTL_DC1_HIB 0x00000040 |
| #define SYSCTL_DC1_JTAG 0x00000001 |
| #define SYSCTL_DC1_MINSYSDIV_20 0x00009000 |
| #define SYSCTL_DC1_MINSYSDIV_25 0x00007000 |
| #define SYSCTL_DC1_MINSYSDIV_40 0x00004000 |
| #define SYSCTL_DC1_MINSYSDIV_50 0x00003000 |
| #define SYSCTL_DC1_MINSYSDIV_80 0x00002000 |
| #define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 |
| #define SYSCTL_DC1_MPU 0x00000080 |
| #define SYSCTL_DC1_PLL 0x00000010 |
| #define SYSCTL_DC1_PWM0 0x00100000 |
| #define SYSCTL_DC1_PWM1 0x00200000 |
| #define SYSCTL_DC1_R (*((volatile uint32_t *)0x400FE010)) |
| #define SYSCTL_DC1_SWD 0x00000002 |
| #define SYSCTL_DC1_SWO 0x00000004 |
| #define SYSCTL_DC1_TEMP 0x00000020 |
| #define SYSCTL_DC1_WDT0 0x00000008 |
| #define SYSCTL_DC1_WDT1 0x10000000 |
| #define SYSCTL_DC2_COMP0 0x01000000 |
| #define SYSCTL_DC2_COMP1 0x02000000 |
| #define SYSCTL_DC2_COMP2 0x04000000 |
| #define SYSCTL_DC2_EPI0 0x40000000 |
| #define SYSCTL_DC2_I2C0 0x00001000 |
| #define SYSCTL_DC2_I2C0HS 0x00002000 |
| #define SYSCTL_DC2_I2C1 0x00004000 |
| #define SYSCTL_DC2_I2C1HS 0x00008000 |
| #define SYSCTL_DC2_I2S0 0x10000000 |
| #define SYSCTL_DC2_QEI0 0x00000100 |
| #define SYSCTL_DC2_QEI1 0x00000200 |
| #define SYSCTL_DC2_R (*((volatile uint32_t *)0x400FE014)) |
| #define SYSCTL_DC2_SSI0 0x00000010 |
| #define SYSCTL_DC2_SSI1 0x00000020 |
| #define SYSCTL_DC2_TIMER0 0x00010000 |
| #define SYSCTL_DC2_TIMER1 0x00020000 |
| #define SYSCTL_DC2_TIMER2 0x00040000 |
| #define SYSCTL_DC2_TIMER3 0x00080000 |
| #define SYSCTL_DC2_UART0 0x00000001 |
| #define SYSCTL_DC2_UART1 0x00000002 |
| #define SYSCTL_DC2_UART2 0x00000004 |
| #define SYSCTL_DC3_32KHZ 0x80000000 |
| #define SYSCTL_DC3_ADC0AIN0 0x00010000 |
| #define SYSCTL_DC3_ADC0AIN1 0x00020000 |
| #define SYSCTL_DC3_ADC0AIN2 0x00040000 |
| #define SYSCTL_DC3_ADC0AIN3 0x00080000 |
| #define SYSCTL_DC3_ADC0AIN4 0x00100000 |
| #define SYSCTL_DC3_ADC0AIN5 0x00200000 |
| #define SYSCTL_DC3_ADC0AIN6 0x00400000 |
| #define SYSCTL_DC3_ADC0AIN7 0x00800000 |
| #define SYSCTL_DC3_C0MINUS 0x00000040 |
| #define SYSCTL_DC3_C0O 0x00000100 |
| #define SYSCTL_DC3_C0PLUS 0x00000080 |
| #define SYSCTL_DC3_C1MINUS 0x00000200 |
| #define SYSCTL_DC3_C1O 0x00000800 |
| #define SYSCTL_DC3_C1PLUS 0x00000400 |
| #define SYSCTL_DC3_C2MINUS 0x00001000 |
| #define SYSCTL_DC3_C2O 0x00004000 |
| #define SYSCTL_DC3_C2PLUS 0x00002000 |
| #define SYSCTL_DC3_CCP0 0x01000000 |
| #define SYSCTL_DC3_CCP1 0x02000000 |
| #define SYSCTL_DC3_CCP2 0x04000000 |
| #define SYSCTL_DC3_CCP3 0x08000000 |
| #define SYSCTL_DC3_CCP4 0x10000000 |
| #define SYSCTL_DC3_CCP5 0x20000000 |
| #define SYSCTL_DC3_PWM0 0x00000001 |
| #define SYSCTL_DC3_PWM1 0x00000002 |
| #define SYSCTL_DC3_PWM2 0x00000004 |
| #define SYSCTL_DC3_PWM3 0x00000008 |
| #define SYSCTL_DC3_PWM4 0x00000010 |
| #define SYSCTL_DC3_PWM5 0x00000020 |
| #define SYSCTL_DC3_PWMFAULT 0x00008000 |
| #define SYSCTL_DC3_R (*((volatile uint32_t *)0x400FE018)) |
| #define SYSCTL_DC4_CCP6 0x00004000 |
| #define SYSCTL_DC4_CCP7 0x00008000 |
| #define SYSCTL_DC4_E1588 0x01000000 |
| #define SYSCTL_DC4_EMAC0 0x10000000 |
| #define SYSCTL_DC4_EPHY0 0x40000000 |
| #define SYSCTL_DC4_GPIOA 0x00000001 |
| #define SYSCTL_DC4_GPIOB 0x00000002 |
| #define SYSCTL_DC4_GPIOC 0x00000004 |
| #define SYSCTL_DC4_GPIOD 0x00000008 |
| #define SYSCTL_DC4_GPIOE 0x00000010 |
| #define SYSCTL_DC4_GPIOF 0x00000020 |
| #define SYSCTL_DC4_GPIOG 0x00000040 |
| #define SYSCTL_DC4_GPIOH 0x00000080 |
| #define SYSCTL_DC4_GPIOJ 0x00000100 |
| #define SYSCTL_DC4_PICAL 0x00040000 |
| #define SYSCTL_DC4_R (*((volatile uint32_t *)0x400FE01C)) |
| #define SYSCTL_DC4_ROM 0x00001000 |
| #define SYSCTL_DC4_UDMA 0x00002000 |
| #define SYSCTL_DC5_PWM0 0x00000001 |
| #define SYSCTL_DC5_PWM1 0x00000002 |
| #define SYSCTL_DC5_PWM2 0x00000004 |
| #define SYSCTL_DC5_PWM3 0x00000008 |
| #define SYSCTL_DC5_PWM4 0x00000010 |
| #define SYSCTL_DC5_PWM5 0x00000020 |
| #define SYSCTL_DC5_PWM6 0x00000040 |
| #define SYSCTL_DC5_PWM7 0x00000080 |
| #define SYSCTL_DC5_PWMEFLT 0x00200000 |
| #define SYSCTL_DC5_PWMESYNC 0x00100000 |
| #define SYSCTL_DC5_PWMFAULT0 0x01000000 |
| #define SYSCTL_DC5_PWMFAULT1 0x02000000 |
| #define SYSCTL_DC5_PWMFAULT2 0x04000000 |
| #define SYSCTL_DC5_PWMFAULT3 0x08000000 |
| #define SYSCTL_DC5_R (*((volatile uint32_t *)0x400FE020)) |
| #define SYSCTL_DC6_R (*((volatile uint32_t *)0x400FE024)) |
| #define SYSCTL_DC6_USB0_DEV 0x00000001 |
| #define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 |
| #define SYSCTL_DC6_USB0_M 0x00000003 |
| #define SYSCTL_DC6_USB0_OTG 0x00000003 |
| #define SYSCTL_DC6_USB0PHY 0x00000010 |
| #define SYSCTL_DC7_DMACH0 0x00000001 |
| #define SYSCTL_DC7_DMACH1 0x00000002 |
| #define SYSCTL_DC7_DMACH10 0x00000400 |
| #define SYSCTL_DC7_DMACH11 0x00000800 |
| #define SYSCTL_DC7_DMACH12 0x00001000 |
| #define SYSCTL_DC7_DMACH13 0x00002000 |
| #define SYSCTL_DC7_DMACH14 0x00004000 |
| #define SYSCTL_DC7_DMACH15 0x00008000 |
| #define SYSCTL_DC7_DMACH16 0x00010000 |
| #define SYSCTL_DC7_DMACH17 0x00020000 |
| #define SYSCTL_DC7_DMACH18 0x00040000 |
| #define SYSCTL_DC7_DMACH19 0x00080000 |
| #define SYSCTL_DC7_DMACH2 0x00000004 |
| #define SYSCTL_DC7_DMACH20 0x00100000 |
| #define SYSCTL_DC7_DMACH21 0x00200000 |
| #define SYSCTL_DC7_DMACH22 0x00400000 |
| #define SYSCTL_DC7_DMACH23 0x00800000 |
| #define SYSCTL_DC7_DMACH24 0x01000000 |
| #define SYSCTL_DC7_DMACH25 0x02000000 |
| #define SYSCTL_DC7_DMACH26 0x04000000 |
| #define SYSCTL_DC7_DMACH27 0x08000000 |
| #define SYSCTL_DC7_DMACH28 0x10000000 |
| #define SYSCTL_DC7_DMACH29 0x20000000 |
| #define SYSCTL_DC7_DMACH3 0x00000008 |
| #define SYSCTL_DC7_DMACH30 0x40000000 |
| #define SYSCTL_DC7_DMACH4 0x00000010 |
| #define SYSCTL_DC7_DMACH5 0x00000020 |
| #define SYSCTL_DC7_DMACH6 0x00000040 |
| #define SYSCTL_DC7_DMACH7 0x00000080 |
| #define SYSCTL_DC7_DMACH8 0x00000100 |
| #define SYSCTL_DC7_DMACH9 0x00000200 |
| #define SYSCTL_DC7_R (*((volatile uint32_t *)0x400FE028)) |
| #define SYSCTL_DC8_ADC0AIN0 0x00000001 |
| #define SYSCTL_DC8_ADC0AIN1 0x00000002 |
| #define SYSCTL_DC8_ADC0AIN10 0x00000400 |
| #define SYSCTL_DC8_ADC0AIN11 0x00000800 |
| #define SYSCTL_DC8_ADC0AIN12 0x00001000 |
| #define SYSCTL_DC8_ADC0AIN13 0x00002000 |
| #define SYSCTL_DC8_ADC0AIN14 0x00004000 |
| #define SYSCTL_DC8_ADC0AIN15 0x00008000 |
| #define SYSCTL_DC8_ADC0AIN2 0x00000004 |
| #define SYSCTL_DC8_ADC0AIN3 0x00000008 |
| #define SYSCTL_DC8_ADC0AIN4 0x00000010 |
| #define SYSCTL_DC8_ADC0AIN5 0x00000020 |
| #define SYSCTL_DC8_ADC0AIN6 0x00000040 |
| #define SYSCTL_DC8_ADC0AIN7 0x00000080 |
| #define SYSCTL_DC8_ADC0AIN8 0x00000100 |
| #define SYSCTL_DC8_ADC0AIN9 0x00000200 |
| #define SYSCTL_DC8_ADC1AIN0 0x00010000 |
| #define SYSCTL_DC8_ADC1AIN1 0x00020000 |
| #define SYSCTL_DC8_ADC1AIN10 0x04000000 |
| #define SYSCTL_DC8_ADC1AIN11 0x08000000 |
| #define SYSCTL_DC8_ADC1AIN12 0x10000000 |
| #define SYSCTL_DC8_ADC1AIN13 0x20000000 |
| #define SYSCTL_DC8_ADC1AIN14 0x40000000 |
| #define SYSCTL_DC8_ADC1AIN15 0x80000000 |
| #define SYSCTL_DC8_ADC1AIN2 0x00040000 |
| #define SYSCTL_DC8_ADC1AIN3 0x00080000 |
| #define SYSCTL_DC8_ADC1AIN4 0x00100000 |
| #define SYSCTL_DC8_ADC1AIN5 0x00200000 |
| #define SYSCTL_DC8_ADC1AIN6 0x00400000 |
| #define SYSCTL_DC8_ADC1AIN7 0x00800000 |
| #define SYSCTL_DC8_ADC1AIN8 0x01000000 |
| #define SYSCTL_DC8_ADC1AIN9 0x02000000 |
| #define SYSCTL_DC8_R (*((volatile uint32_t *)0x400FE02C)) |
| #define SYSCTL_DC9_ADC0DC0 0x00000001 |
| #define SYSCTL_DC9_ADC0DC1 0x00000002 |
| #define SYSCTL_DC9_ADC0DC2 0x00000004 |
| #define SYSCTL_DC9_ADC0DC3 0x00000008 |
| #define SYSCTL_DC9_ADC0DC4 0x00000010 |
| #define SYSCTL_DC9_ADC0DC5 0x00000020 |
| #define SYSCTL_DC9_ADC0DC6 0x00000040 |
| #define SYSCTL_DC9_ADC0DC7 0x00000080 |
| #define SYSCTL_DC9_ADC1DC0 0x00010000 |
| #define SYSCTL_DC9_ADC1DC1 0x00020000 |
| #define SYSCTL_DC9_ADC1DC2 0x00040000 |
| #define SYSCTL_DC9_ADC1DC3 0x00080000 |
| #define SYSCTL_DC9_ADC1DC4 0x00100000 |
| #define SYSCTL_DC9_ADC1DC5 0x00200000 |
| #define SYSCTL_DC9_ADC1DC6 0x00400000 |
| #define SYSCTL_DC9_ADC1DC7 0x00800000 |
| #define SYSCTL_DC9_R (*((volatile uint32_t *)0x400FE190)) |
| #define SYSCTL_DCGC0_ADC0 0x00010000 |
| #define SYSCTL_DCGC0_ADC1 0x00020000 |
| #define SYSCTL_DCGC0_CAN0 0x01000000 |
| #define SYSCTL_DCGC0_CAN1 0x02000000 |
| #define SYSCTL_DCGC0_HIB 0x00000040 |
| #define SYSCTL_DCGC0_PWM0 0x00100000 |
| #define SYSCTL_DCGC0_R (*((volatile uint32_t *)0x400FE120)) |
| #define SYSCTL_DCGC0_WDT0 0x00000008 |
| #define SYSCTL_DCGC0_WDT1 0x10000000 |
| #define SYSCTL_DCGC1_COMP0 0x01000000 |
| #define SYSCTL_DCGC1_COMP1 0x02000000 |
| #define SYSCTL_DCGC1_COMP2 0x04000000 |
| #define SYSCTL_DCGC1_I2C0 0x00001000 |
| #define SYSCTL_DCGC1_I2C1 0x00004000 |
| #define SYSCTL_DCGC1_QEI0 0x00000100 |
| #define SYSCTL_DCGC1_QEI1 0x00000200 |
| #define SYSCTL_DCGC1_R (*((volatile uint32_t *)0x400FE124)) |
| #define SYSCTL_DCGC1_SSI0 0x00000010 |
| #define SYSCTL_DCGC1_SSI1 0x00000020 |
| #define SYSCTL_DCGC1_TIMER0 0x00010000 |
| #define SYSCTL_DCGC1_TIMER1 0x00020000 |
| #define SYSCTL_DCGC1_TIMER2 0x00040000 |
| #define SYSCTL_DCGC1_TIMER3 0x00080000 |
| #define SYSCTL_DCGC1_UART0 0x00000001 |
| #define SYSCTL_DCGC1_UART1 0x00000002 |
| #define SYSCTL_DCGC1_UART2 0x00000004 |
| #define SYSCTL_DCGC2_GPIOA 0x00000001 |
| #define SYSCTL_DCGC2_GPIOB 0x00000002 |
| #define SYSCTL_DCGC2_GPIOC 0x00000004 |
| #define SYSCTL_DCGC2_GPIOD 0x00000008 |
| #define SYSCTL_DCGC2_GPIOE 0x00000010 |
| #define SYSCTL_DCGC2_GPIOF 0x00000020 |
| #define SYSCTL_DCGC2_GPIOG 0x00000040 |
| #define SYSCTL_DCGC2_GPIOH 0x00000080 |
| #define SYSCTL_DCGC2_GPIOJ 0x00000100 |
| #define SYSCTL_DCGC2_R (*((volatile uint32_t *)0x400FE128)) |
| #define SYSCTL_DCGC2_UDMA 0x00002000 |
| #define SYSCTL_DCGC2_USB0 0x00010000 |
| #define SYSCTL_DCGCACMP_D0 0x00000001 |
| #define SYSCTL_DCGCACMP_R (*((volatile uint32_t *)0x400FE83C)) |
| #define SYSCTL_DCGCADC_D0 0x00000001 |
| #define SYSCTL_DCGCADC_D1 0x00000002 |
| #define SYSCTL_DCGCADC_R (*((volatile uint32_t *)0x400FE838)) |
| #define SYSCTL_DCGCCAN_D0 0x00000001 |
| #define SYSCTL_DCGCCAN_D1 0x00000002 |
| #define SYSCTL_DCGCCAN_R (*((volatile uint32_t *)0x400FE834)) |
| #define SYSCTL_DCGCDMA_D0 0x00000001 |
| #define SYSCTL_DCGCDMA_R (*((volatile uint32_t *)0x400FE80C)) |
| #define SYSCTL_DCGCEEPROM_D0 0x00000001 |
| #define SYSCTL_DCGCEEPROM_R (*((volatile uint32_t *)0x400FE858)) |
| #define SYSCTL_DCGCGPIO_D0 0x00000001 |
| #define SYSCTL_DCGCGPIO_D1 0x00000002 |
| #define SYSCTL_DCGCGPIO_D10 0x00000400 |
| #define SYSCTL_DCGCGPIO_D11 0x00000800 |
| #define SYSCTL_DCGCGPIO_D12 0x00001000 |
| #define SYSCTL_DCGCGPIO_D13 0x00002000 |
| #define SYSCTL_DCGCGPIO_D2 0x00000004 |
| #define SYSCTL_DCGCGPIO_D3 0x00000008 |
| #define SYSCTL_DCGCGPIO_D4 0x00000010 |
| #define SYSCTL_DCGCGPIO_D5 0x00000020 |
| #define SYSCTL_DCGCGPIO_D6 0x00000040 |
| #define SYSCTL_DCGCGPIO_D7 0x00000080 |
| #define SYSCTL_DCGCGPIO_D8 0x00000100 |
| #define SYSCTL_DCGCGPIO_D9 0x00000200 |
| #define SYSCTL_DCGCGPIO_R (*((volatile uint32_t *)0x400FE808)) |
| #define SYSCTL_DCGCHIB_D0 0x00000001 |
| #define SYSCTL_DCGCHIB_R (*((volatile uint32_t *)0x400FE814)) |
| #define SYSCTL_DCGCI2C_D0 0x00000001 |
| #define SYSCTL_DCGCI2C_D1 0x00000002 |
| #define SYSCTL_DCGCI2C_D2 0x00000004 |
| #define SYSCTL_DCGCI2C_D3 0x00000008 |
| #define SYSCTL_DCGCI2C_D4 0x00000010 |
| #define SYSCTL_DCGCI2C_D5 0x00000020 |
| #define SYSCTL_DCGCI2C_R (*((volatile uint32_t *)0x400FE820)) |
| #define SYSCTL_DCGCPWM_D0 0x00000001 |
| #define SYSCTL_DCGCPWM_D1 0x00000002 |
| #define SYSCTL_DCGCPWM_R (*((volatile uint32_t *)0x400FE840)) |
| #define SYSCTL_DCGCQEI_D0 0x00000001 |
| #define SYSCTL_DCGCQEI_D1 0x00000002 |
| #define SYSCTL_DCGCQEI_R (*((volatile uint32_t *)0x400FE844)) |
| #define SYSCTL_DCGCSSI_D0 0x00000001 |
| #define SYSCTL_DCGCSSI_D1 0x00000002 |
| #define SYSCTL_DCGCSSI_D2 0x00000004 |
| #define SYSCTL_DCGCSSI_D3 0x00000008 |
| #define SYSCTL_DCGCSSI_R (*((volatile uint32_t *)0x400FE81C)) |
| #define SYSCTL_DCGCTIMER_D0 0x00000001 |
| #define SYSCTL_DCGCTIMER_D1 0x00000002 |
| #define SYSCTL_DCGCTIMER_D2 0x00000004 |
| #define SYSCTL_DCGCTIMER_D3 0x00000008 |
| #define SYSCTL_DCGCTIMER_D4 0x00000010 |
| #define SYSCTL_DCGCTIMER_D5 0x00000020 |
| #define SYSCTL_DCGCTIMER_R (*((volatile uint32_t *)0x400FE804)) |
| #define SYSCTL_DCGCUART_D0 0x00000001 |
| #define SYSCTL_DCGCUART_D1 0x00000002 |
| #define SYSCTL_DCGCUART_D2 0x00000004 |
| #define SYSCTL_DCGCUART_D3 0x00000008 |
| #define SYSCTL_DCGCUART_D4 0x00000010 |
| #define SYSCTL_DCGCUART_D5 0x00000020 |
| #define SYSCTL_DCGCUART_D6 0x00000040 |
| #define SYSCTL_DCGCUART_D7 0x00000080 |
| #define SYSCTL_DCGCUART_R (*((volatile uint32_t *)0x400FE818)) |
| #define SYSCTL_DCGCUSB_D0 0x00000001 |
| #define SYSCTL_DCGCUSB_R (*((volatile uint32_t *)0x400FE828)) |
| #define SYSCTL_DCGCWD_D0 0x00000001 |
| #define SYSCTL_DCGCWD_D1 0x00000002 |
| #define SYSCTL_DCGCWD_R (*((volatile uint32_t *)0x400FE800)) |
| #define SYSCTL_DCGCWTIMER_D0 0x00000001 |
| #define SYSCTL_DCGCWTIMER_D1 0x00000002 |
| #define SYSCTL_DCGCWTIMER_D2 0x00000004 |
| #define SYSCTL_DCGCWTIMER_D3 0x00000008 |
| #define SYSCTL_DCGCWTIMER_D4 0x00000010 |
| #define SYSCTL_DCGCWTIMER_D5 0x00000020 |
| #define SYSCTL_DCGCWTIMER_R (*((volatile uint32_t *)0x400FE85C)) |
| #define SYSCTL_DID0_CLASS_BLIZZARD 0x00050000 |
| #define SYSCTL_DID0_CLASS_M 0x00FF0000 |
| #define SYSCTL_DID0_CLASS_TM4C123 0x00050000 |
| #define SYSCTL_DID0_MAJ_M 0x0000FF00 |
| #define SYSCTL_DID0_MAJ_REVA 0x00000000 |
| #define SYSCTL_DID0_MAJ_REVB 0x00000100 |
| #define SYSCTL_DID0_MAJ_REVC 0x00000200 |
| #define SYSCTL_DID0_MIN_0 0x00000000 |
| #define SYSCTL_DID0_MIN_1 0x00000001 |
| #define SYSCTL_DID0_MIN_2 0x00000002 |
| #define SYSCTL_DID0_MIN_M 0x000000FF |
| #define SYSCTL_DID0_R (*((volatile uint32_t *)0x400FE000)) |
| #define SYSCTL_DID0_VER_1 0x10000000 |
| #define SYSCTL_DID0_VER_M 0x70000000 |
| #define SYSCTL_DID1_FAM_M 0x0F000000 |
| #define SYSCTL_DID1_FAM_TIVA 0x00000000 |
| #define SYSCTL_DID1_PINCNT_100 0x00004000 |
| #define SYSCTL_DID1_PINCNT_128 0x0000C000 |
| #define SYSCTL_DID1_PINCNT_144 0x00008000 |
| #define SYSCTL_DID1_PINCNT_157 0x0000A000 |
| #define SYSCTL_DID1_PINCNT_64 0x00006000 |
| #define SYSCTL_DID1_PINCNT_M 0x0000E000 |
| #define SYSCTL_DID1_PKG_BGA 0x00000010 |
| #define SYSCTL_DID1_PKG_M 0x00000018 |
| #define SYSCTL_DID1_PKG_QFP 0x00000008 |
| #define SYSCTL_DID1_PRTNO_M 0x00FF0000 |
| #define SYSCTL_DID1_PRTNO_TM4C123GH6PGE 0x00C50000 |
| #define SYSCTL_DID1_QUAL_ES 0x00000000 |
| #define SYSCTL_DID1_QUAL_FQ 0x00000002 |
| #define SYSCTL_DID1_QUAL_M 0x00000003 |
| #define SYSCTL_DID1_QUAL_PP 0x00000001 |
| #define SYSCTL_DID1_R (*((volatile uint32_t *)0x400FE004)) |
| #define SYSCTL_DID1_ROHS 0x00000004 |
| #define SYSCTL_DID1_TEMP_E 0x00000040 |
| #define SYSCTL_DID1_TEMP_I 0x00000020 |
| #define SYSCTL_DID1_TEMP_IE 0x00000060 |
| #define SYSCTL_DID1_TEMP_M 0x000000E0 |
| #define SYSCTL_DID1_VER_1 0x10000000 |
| #define SYSCTL_DID1_VER_M 0xF0000000 |
| #define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 |
| #define SYSCTL_DSLPCLKCFG_D_S 23 |
| #define SYSCTL_DSLPCLKCFG_O_30 0x00000030 |
| #define SYSCTL_DSLPCLKCFG_O_32 0x00000070 |
| #define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 |
| #define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 |
| #define SYSCTL_DSLPCLKCFG_O_M 0x00000070 |
| #define SYSCTL_DSLPCLKCFG_PIOSCPD 0x00000002 |
| #define SYSCTL_DSLPCLKCFG_R (*((volatile uint32_t *)0x400FE144)) |
| #define SYSCTL_DSLPPWRCFG_FLASHPM_M 0x00000030 |
| #define SYSCTL_DSLPPWRCFG_FLASHPM_NRM 0x00000000 |
| #define SYSCTL_DSLPPWRCFG_FLASHPM_SLP 0x00000020 |
| #define SYSCTL_DSLPPWRCFG_R (*((volatile uint32_t *)0x400FE18C)) |
| #define SYSCTL_DSLPPWRCFG_SRAMPM_LP 0x00000003 |
| #define SYSCTL_DSLPPWRCFG_SRAMPM_M 0x00000003 |
| #define SYSCTL_DSLPPWRCFG_SRAMPM_NRM 0x00000000 |
| #define SYSCTL_DSLPPWRCFG_SRAMPM_SBY 0x00000001 |
| #define SYSCTL_GPIOHBCTL_PORTA 0x00000001 |
| #define SYSCTL_GPIOHBCTL_PORTB 0x00000002 |
| #define SYSCTL_GPIOHBCTL_PORTC 0x00000004 |
| #define SYSCTL_GPIOHBCTL_PORTD 0x00000008 |
| #define SYSCTL_GPIOHBCTL_PORTE 0x00000010 |
| #define SYSCTL_GPIOHBCTL_PORTF 0x00000020 |
| #define SYSCTL_GPIOHBCTL_PORTG 0x00000040 |
| #define SYSCTL_GPIOHBCTL_PORTH 0x00000080 |
| #define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 |
| #define SYSCTL_GPIOHBCTL_R (*((volatile uint32_t *)0x400FE06C)) |
| #define SYSCTL_IMC_BOR0IM 0x00000800 |
| #define SYSCTL_IMC_BOR1IM 0x00000002 |
| #define SYSCTL_IMC_MOFIM 0x00000008 |
| #define SYSCTL_IMC_MOSCPUPIM 0x00000100 |
| #define SYSCTL_IMC_PLLLIM 0x00000040 |
| #define SYSCTL_IMC_R (*((volatile uint32_t *)0x400FE054)) |
| #define SYSCTL_IMC_USBPLLLIM 0x00000080 |
| #define SYSCTL_IMC_VDDAIM 0x00000400 |
| #define SYSCTL_LDODPCTL_R (*((volatile uint32_t *)0x400FE1BC)) |
| #define SYSCTL_LDODPCTL_VADJEN 0x80000000 |
| #define SYSCTL_LDODPCTL_VLDO_0_90V 0x00000012 |
| #define SYSCTL_LDODPCTL_VLDO_0_95V 0x00000013 |
| #define SYSCTL_LDODPCTL_VLDO_1_00V 0x00000014 |
| #define SYSCTL_LDODPCTL_VLDO_1_05V 0x00000015 |
| #define SYSCTL_LDODPCTL_VLDO_1_10V 0x00000016 |
| #define SYSCTL_LDODPCTL_VLDO_1_15V 0x00000017 |
| #define SYSCTL_LDODPCTL_VLDO_1_20V 0x00000018 |
| #define SYSCTL_LDODPCTL_VLDO_M 0x000000FF |
| #define SYSCTL_LDOSPCTL_R (*((volatile uint32_t *)0x400FE1B4)) |
| #define SYSCTL_LDOSPCTL_VADJEN 0x80000000 |
| #define SYSCTL_LDOSPCTL_VLDO_0_90V 0x00000012 |
| #define SYSCTL_LDOSPCTL_VLDO_0_95V 0x00000013 |
| #define SYSCTL_LDOSPCTL_VLDO_1_00V 0x00000014 |
| #define SYSCTL_LDOSPCTL_VLDO_1_05V 0x00000015 |
| #define SYSCTL_LDOSPCTL_VLDO_1_10V 0x00000016 |
| #define SYSCTL_LDOSPCTL_VLDO_1_15V 0x00000017 |
| #define SYSCTL_LDOSPCTL_VLDO_1_20V 0x00000018 |
| #define SYSCTL_LDOSPCTL_VLDO_M 0x000000FF |
| #define SYSCTL_MISC_BOR0MIS 0x00000800 |
| #define SYSCTL_MISC_BOR1MIS 0x00000002 |
| #define SYSCTL_MISC_MOFMIS 0x00000008 |
| #define SYSCTL_MISC_MOSCPUPMIS 0x00000100 |
| #define SYSCTL_MISC_PLLLMIS 0x00000040 |
| #define SYSCTL_MISC_R (*((volatile uint32_t *)0x400FE058)) |
| #define SYSCTL_MISC_USBPLLLMIS 0x00000080 |
| #define SYSCTL_MISC_VDDAMIS 0x00000400 |
| #define SYSCTL_MOSCCTL_CVAL 0x00000001 |
| #define SYSCTL_MOSCCTL_MOSCIM 0x00000002 |
| #define SYSCTL_MOSCCTL_NOXTAL 0x00000004 |
| #define SYSCTL_MOSCCTL_R (*((volatile uint32_t *)0x400FE07C)) |
| #define SYSCTL_NVMSTAT_FWB 0x00000001 |
| #define SYSCTL_NVMSTAT_R (*((volatile uint32_t *)0x400FE1A0)) |
| #define SYSCTL_PBORCTL_BOR0 0x00000004 |
| #define SYSCTL_PBORCTL_BOR1 0x00000002 |
| #define SYSCTL_PBORCTL_R (*((volatile uint32_t *)0x400FE030)) |
| #define SYSCTL_PIOSCCAL_CAL 0x00000200 |
| #define SYSCTL_PIOSCCAL_R (*((volatile uint32_t *)0x400FE150)) |
| #define SYSCTL_PIOSCCAL_UPDATE 0x00000100 |
| #define SYSCTL_PIOSCCAL_UT_M 0x0000007F |
| #define SYSCTL_PIOSCCAL_UT_S 0 |
| #define SYSCTL_PIOSCCAL_UTEN 0x80000000 |
| #define SYSCTL_PIOSCSTAT_CR_M 0x00000300 |
| #define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 |
| #define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 |
| #define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 |
| #define SYSCTL_PIOSCSTAT_CT_M 0x0000007F |
| #define SYSCTL_PIOSCSTAT_CT_S 0 |
| #define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 |
| #define SYSCTL_PIOSCSTAT_DT_S 16 |
| #define SYSCTL_PIOSCSTAT_R (*((volatile uint32_t *)0x400FE154)) |
| #define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 |
| #define SYSCTL_PLLFREQ0_MFRAC_S 10 |
| #define SYSCTL_PLLFREQ0_MINT_M 0x000003FF |
| #define SYSCTL_PLLFREQ0_MINT_S 0 |
| #define SYSCTL_PLLFREQ0_R (*((volatile uint32_t *)0x400FE160)) |
| #define SYSCTL_PLLFREQ1_N_M 0x0000001F |
| #define SYSCTL_PLLFREQ1_N_S 0 |
| #define SYSCTL_PLLFREQ1_Q_M 0x00001F00 |
| #define SYSCTL_PLLFREQ1_Q_S 8 |
| #define SYSCTL_PLLFREQ1_R (*((volatile uint32_t *)0x400FE164)) |
| #define SYSCTL_PLLSTAT_LOCK 0x00000001 |
| #define SYSCTL_PLLSTAT_R (*((volatile uint32_t *)0x400FE168)) |
| #define SYSCTL_PPACMP_P0 0x00000001 |
| #define SYSCTL_PPACMP_R (*((volatile uint32_t *)0x400FE33C)) |
| #define SYSCTL_PPADC_P0 0x00000001 |
| #define SYSCTL_PPADC_P1 0x00000002 |
| #define SYSCTL_PPADC_R (*((volatile uint32_t *)0x400FE338)) |
| #define SYSCTL_PPCAN_P0 0x00000001 |
| #define SYSCTL_PPCAN_P1 0x00000002 |
| #define SYSCTL_PPCAN_R (*((volatile uint32_t *)0x400FE334)) |
| #define SYSCTL_PPDMA_P0 0x00000001 |
| #define SYSCTL_PPDMA_R (*((volatile uint32_t *)0x400FE30C)) |
| #define SYSCTL_PPEEPROM_P0 0x00000001 |
| #define SYSCTL_PPEEPROM_R (*((volatile uint32_t *)0x400FE358)) |
| #define SYSCTL_PPGPIO_P0 0x00000001 |
| #define SYSCTL_PPGPIO_P1 0x00000002 |
| #define SYSCTL_PPGPIO_P10 0x00000400 |
| #define SYSCTL_PPGPIO_P11 0x00000800 |
| #define SYSCTL_PPGPIO_P12 0x00001000 |
| #define SYSCTL_PPGPIO_P13 0x00002000 |
| #define SYSCTL_PPGPIO_P14 0x00004000 |
| #define SYSCTL_PPGPIO_P2 0x00000004 |
| #define SYSCTL_PPGPIO_P3 0x00000008 |
| #define SYSCTL_PPGPIO_P4 0x00000010 |
| #define SYSCTL_PPGPIO_P5 0x00000020 |
| #define SYSCTL_PPGPIO_P6 0x00000040 |
| #define SYSCTL_PPGPIO_P7 0x00000080 |
| #define SYSCTL_PPGPIO_P8 0x00000100 |
| #define SYSCTL_PPGPIO_P9 0x00000200 |
| #define SYSCTL_PPGPIO_R (*((volatile uint32_t *)0x400FE308)) |
| #define SYSCTL_PPHIB_P0 0x00000001 |
| #define SYSCTL_PPHIB_R (*((volatile uint32_t *)0x400FE314)) |
| #define SYSCTL_PPI2C_P0 0x00000001 |
| #define SYSCTL_PPI2C_P1 0x00000002 |
| #define SYSCTL_PPI2C_P2 0x00000004 |
| #define SYSCTL_PPI2C_P3 0x00000008 |
| #define SYSCTL_PPI2C_P4 0x00000010 |
| #define SYSCTL_PPI2C_P5 0x00000020 |
| #define SYSCTL_PPI2C_R (*((volatile uint32_t *)0x400FE320)) |
| #define SYSCTL_PPPWM_P0 0x00000001 |
| #define SYSCTL_PPPWM_P1 0x00000002 |
| #define SYSCTL_PPPWM_R (*((volatile uint32_t *)0x400FE340)) |
| #define SYSCTL_PPQEI_P0 0x00000001 |
| #define SYSCTL_PPQEI_P1 0x00000002 |
| #define SYSCTL_PPQEI_R (*((volatile uint32_t *)0x400FE344)) |
| #define SYSCTL_PPSSI_P0 0x00000001 |
| #define SYSCTL_PPSSI_P1 0x00000002 |
| #define SYSCTL_PPSSI_P2 0x00000004 |
| #define SYSCTL_PPSSI_P3 0x00000008 |
| #define SYSCTL_PPSSI_R (*((volatile uint32_t *)0x400FE31C)) |
| #define SYSCTL_PPTIMER_P0 0x00000001 |
| #define SYSCTL_PPTIMER_P1 0x00000002 |
| #define SYSCTL_PPTIMER_P2 0x00000004 |
| #define SYSCTL_PPTIMER_P3 0x00000008 |
| #define SYSCTL_PPTIMER_P4 0x00000010 |
| #define SYSCTL_PPTIMER_P5 0x00000020 |
| #define SYSCTL_PPTIMER_R (*((volatile uint32_t *)0x400FE304)) |
| #define SYSCTL_PPUART_P0 0x00000001 |
| #define SYSCTL_PPUART_P1 0x00000002 |
| #define SYSCTL_PPUART_P2 0x00000004 |
| #define SYSCTL_PPUART_P3 0x00000008 |
| #define SYSCTL_PPUART_P4 0x00000010 |
| #define SYSCTL_PPUART_P5 0x00000020 |
| #define SYSCTL_PPUART_P6 0x00000040 |
| #define SYSCTL_PPUART_P7 0x00000080 |
| #define SYSCTL_PPUART_R (*((volatile uint32_t *)0x400FE318)) |
| #define SYSCTL_PPUSB_P0 0x00000001 |
| #define SYSCTL_PPUSB_R (*((volatile uint32_t *)0x400FE328)) |
| #define SYSCTL_PPWD_P0 0x00000001 |
| #define SYSCTL_PPWD_P1 0x00000002 |
| #define SYSCTL_PPWD_R (*((volatile uint32_t *)0x400FE300)) |
| #define SYSCTL_PPWTIMER_P0 0x00000001 |
| #define SYSCTL_PPWTIMER_P1 0x00000002 |
| #define SYSCTL_PPWTIMER_P2 0x00000004 |
| #define SYSCTL_PPWTIMER_P3 0x00000008 |
| #define SYSCTL_PPWTIMER_P4 0x00000010 |
| #define SYSCTL_PPWTIMER_P5 0x00000020 |
| #define SYSCTL_PPWTIMER_R (*((volatile uint32_t *)0x400FE35C)) |
| #define SYSCTL_PRACMP_R (*((volatile uint32_t *)0x400FEA3C)) |
| #define SYSCTL_PRACMP_R0 0x00000001 |
| #define SYSCTL_PRADC_R (*((volatile uint32_t *)0x400FEA38)) |
| #define SYSCTL_PRADC_R0 0x00000001 |
| #define SYSCTL_PRADC_R1 0x00000002 |
| #define SYSCTL_PRCAN_R (*((volatile uint32_t *)0x400FEA34)) |
| #define SYSCTL_PRCAN_R0 0x00000001 |
| #define SYSCTL_PRCAN_R1 0x00000002 |
| #define SYSCTL_PRDMA_R (*((volatile uint32_t *)0x400FEA0C)) |
| #define SYSCTL_PRDMA_R0 0x00000001 |
| #define SYSCTL_PREEPROM_R (*((volatile uint32_t *)0x400FEA58)) |
| #define SYSCTL_PREEPROM_R0 0x00000001 |
| #define SYSCTL_PRGPIO_R (*((volatile uint32_t *)0x400FEA08)) |
| #define SYSCTL_PRGPIO_R0 0x00000001 |
| #define SYSCTL_PRGPIO_R1 0x00000002 |
| #define SYSCTL_PRGPIO_R10 0x00000400 |
| #define SYSCTL_PRGPIO_R11 0x00000800 |
| #define SYSCTL_PRGPIO_R12 0x00001000 |
| #define SYSCTL_PRGPIO_R13 0x00002000 |
| #define SYSCTL_PRGPIO_R2 0x00000004 |
| #define SYSCTL_PRGPIO_R3 0x00000008 |
| #define SYSCTL_PRGPIO_R4 0x00000010 |
| #define SYSCTL_PRGPIO_R5 0x00000020 |
| #define SYSCTL_PRGPIO_R6 0x00000040 |
| #define SYSCTL_PRGPIO_R7 0x00000080 |
| #define SYSCTL_PRGPIO_R8 0x00000100 |
| #define SYSCTL_PRGPIO_R9 0x00000200 |
| #define SYSCTL_PRHIB_R (*((volatile uint32_t *)0x400FEA14)) |
| #define SYSCTL_PRHIB_R0 0x00000001 |
| #define SYSCTL_PRI2C_R (*((volatile uint32_t *)0x400FEA20)) |
| #define SYSCTL_PRI2C_R0 0x00000001 |
| #define SYSCTL_PRI2C_R1 0x00000002 |
| #define SYSCTL_PRI2C_R2 0x00000004 |
| #define SYSCTL_PRI2C_R3 0x00000008 |
| #define SYSCTL_PRI2C_R4 0x00000010 |
| #define SYSCTL_PRI2C_R5 0x00000020 |
| #define SYSCTL_PRPWM_R (*((volatile uint32_t *)0x400FEA40)) |
| #define SYSCTL_PRPWM_R0 0x00000001 |
| #define SYSCTL_PRPWM_R1 0x00000002 |
| #define SYSCTL_PRQEI_R (*((volatile uint32_t *)0x400FEA44)) |
| #define SYSCTL_PRQEI_R0 0x00000001 |
| #define SYSCTL_PRQEI_R1 0x00000002 |
| #define SYSCTL_PRSSI_R (*((volatile uint32_t *)0x400FEA1C)) |
| #define SYSCTL_PRSSI_R0 0x00000001 |
| #define SYSCTL_PRSSI_R1 0x00000002 |
| #define SYSCTL_PRSSI_R2 0x00000004 |
| #define SYSCTL_PRSSI_R3 0x00000008 |
| #define SYSCTL_PRTIMER_R (*((volatile uint32_t *)0x400FEA04)) |
| #define SYSCTL_PRTIMER_R0 0x00000001 |
| #define SYSCTL_PRTIMER_R1 0x00000002 |
| #define SYSCTL_PRTIMER_R2 0x00000004 |
| #define SYSCTL_PRTIMER_R3 0x00000008 |
| #define SYSCTL_PRTIMER_R4 0x00000010 |
| #define SYSCTL_PRTIMER_R5 0x00000020 |
| #define SYSCTL_PRUART_R (*((volatile uint32_t *)0x400FEA18)) |
| #define SYSCTL_PRUART_R0 0x00000001 |
| #define SYSCTL_PRUART_R1 0x00000002 |
| #define SYSCTL_PRUART_R2 0x00000004 |
| #define SYSCTL_PRUART_R3 0x00000008 |
| #define SYSCTL_PRUART_R4 0x00000010 |
| #define SYSCTL_PRUART_R5 0x00000020 |
| #define SYSCTL_PRUART_R6 0x00000040 |
| #define SYSCTL_PRUART_R7 0x00000080 |
| #define SYSCTL_PRUSB_R (*((volatile uint32_t *)0x400FEA28)) |
| #define SYSCTL_PRUSB_R0 0x00000001 |
| #define SYSCTL_PRWD_R (*((volatile uint32_t *)0x400FEA00)) |
| #define SYSCTL_PRWD_R0 0x00000001 |
| #define SYSCTL_PRWD_R1 0x00000002 |
| #define SYSCTL_PRWTIMER_R (*((volatile uint32_t *)0x400FEA5C)) |
| #define SYSCTL_PRWTIMER_R0 0x00000001 |
| #define SYSCTL_PRWTIMER_R1 0x00000002 |
| #define SYSCTL_PRWTIMER_R2 0x00000004 |
| #define SYSCTL_PRWTIMER_R3 0x00000008 |
| #define SYSCTL_PRWTIMER_R4 0x00000010 |
| #define SYSCTL_PRWTIMER_R5 0x00000020 |
| #define SYSCTL_RCC2_BYPASS2 0x00000800 |
| #define SYSCTL_RCC2_DIV400 0x40000000 |
| #define SYSCTL_RCC2_OSCSRC2_30 0x00000030 |
| #define SYSCTL_RCC2_OSCSRC2_32 0x00000070 |
| #define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 |
| #define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 |
| #define SYSCTL_RCC2_OSCSRC2_M 0x00000070 |
| #define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 |
| #define SYSCTL_RCC2_PWRDN2 0x00002000 |
| #define SYSCTL_RCC2_R (*((volatile uint32_t *)0x400FE070)) |
| #define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 |
| #define SYSCTL_RCC2_SYSDIV2_S 23 |
| #define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 |
| #define SYSCTL_RCC2_USBPWRDN 0x00004000 |
| #define SYSCTL_RCC2_USERCC2 0x80000000 |
| #define SYSCTL_RCC_ACG 0x08000000 |
| #define SYSCTL_RCC_BYPASS 0x00000800 |
| #define SYSCTL_RCC_MOSCDIS 0x00000001 |
| #define SYSCTL_RCC_OSCSRC_30 0x00000030 |
| #define SYSCTL_RCC_OSCSRC_INT 0x00000010 |
| #define SYSCTL_RCC_OSCSRC_INT4 0x00000020 |
| #define SYSCTL_RCC_OSCSRC_M 0x00000030 |
| #define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 |
| #define SYSCTL_RCC_PWMDIV_16 0x00060000 |
| #define SYSCTL_RCC_PWMDIV_2 0x00000000 |
| #define SYSCTL_RCC_PWMDIV_32 0x00080000 |
| #define SYSCTL_RCC_PWMDIV_4 0x00020000 |
| #define SYSCTL_RCC_PWMDIV_64 0x000A0000 |
| #define SYSCTL_RCC_PWMDIV_8 0x00040000 |
| #define SYSCTL_RCC_PWMDIV_M 0x000E0000 |
| #define SYSCTL_RCC_PWRDN 0x00002000 |
| #define SYSCTL_RCC_R (*((volatile uint32_t *)0x400FE060)) |
| #define SYSCTL_RCC_SYSDIV_M 0x07800000 |
| #define SYSCTL_RCC_SYSDIV_S 23 |
| #define SYSCTL_RCC_USEPWMDIV 0x00100000 |
| #define SYSCTL_RCC_USESYSDIV 0x00400000 |
| #define SYSCTL_RCC_XTAL_10MHZ 0x00000400 |
| #define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 |
| #define SYSCTL_RCC_XTAL_12MHZ 0x00000440 |
| #define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 |
| #define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 |
| #define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 |
| #define SYSCTL_RCC_XTAL_16MHZ 0x00000540 |
| #define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 |
| #define SYSCTL_RCC_XTAL_20MHZ 0x00000600 |
| #define SYSCTL_RCC_XTAL_24MHZ 0x00000640 |
| #define SYSCTL_RCC_XTAL_25MHZ 0x00000680 |
| #define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 |
| #define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 |
| #define SYSCTL_RCC_XTAL_4MHZ 0x00000180 |
| #define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 |
| #define SYSCTL_RCC_XTAL_5MHZ 0x00000240 |
| #define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 |
| #define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 |
| #define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 |
| #define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 |
| #define SYSCTL_RCC_XTAL_8MHZ 0x00000380 |
| #define SYSCTL_RCC_XTAL_M 0x000007C0 |
| #define SYSCTL_RCGC0_ADC0 0x00010000 |
| #define SYSCTL_RCGC0_ADC0SPD_125K 0x00000000 |
| #define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 |
| #define SYSCTL_RCGC0_ADC0SPD_250K 0x00000100 |
| #define SYSCTL_RCGC0_ADC0SPD_500K 0x00000200 |
| #define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 |
| #define SYSCTL_RCGC0_ADC1 0x00020000 |
| #define SYSCTL_RCGC0_ADC1SPD_125K 0x00000000 |
| #define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 |
| #define SYSCTL_RCGC0_ADC1SPD_250K 0x00000400 |
| #define SYSCTL_RCGC0_ADC1SPD_500K 0x00000800 |
| #define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 |
| #define SYSCTL_RCGC0_CAN0 0x01000000 |
| #define SYSCTL_RCGC0_CAN1 0x02000000 |
| #define SYSCTL_RCGC0_HIB 0x00000040 |
| #define SYSCTL_RCGC0_PWM0 0x00100000 |
| #define SYSCTL_RCGC0_R (*((volatile uint32_t *)0x400FE100)) |
| #define SYSCTL_RCGC0_WDT0 0x00000008 |
| #define SYSCTL_RCGC0_WDT1 0x10000000 |
| #define SYSCTL_RCGC1_COMP0 0x01000000 |
| #define SYSCTL_RCGC1_COMP1 0x02000000 |
| #define SYSCTL_RCGC1_COMP2 0x04000000 |
| #define SYSCTL_RCGC1_I2C0 0x00001000 |
| #define SYSCTL_RCGC1_I2C1 0x00004000 |
| #define SYSCTL_RCGC1_QEI0 0x00000100 |
| #define SYSCTL_RCGC1_QEI1 0x00000200 |
| #define SYSCTL_RCGC1_R (*((volatile uint32_t *)0x400FE104)) |
| #define SYSCTL_RCGC1_SSI0 0x00000010 |
| #define SYSCTL_RCGC1_SSI1 0x00000020 |
| #define SYSCTL_RCGC1_TIMER0 0x00010000 |
| #define SYSCTL_RCGC1_TIMER1 0x00020000 |
| #define SYSCTL_RCGC1_TIMER2 0x00040000 |
| #define SYSCTL_RCGC1_TIMER3 0x00080000 |
| #define SYSCTL_RCGC1_UART0 0x00000001 |
| #define SYSCTL_RCGC1_UART1 0x00000002 |
| #define SYSCTL_RCGC1_UART2 0x00000004 |
| #define SYSCTL_RCGC2_GPIOA 0x00000001 |
| #define SYSCTL_RCGC2_GPIOB 0x00000002 |
| #define SYSCTL_RCGC2_GPIOC 0x00000004 |
| #define SYSCTL_RCGC2_GPIOD 0x00000008 |
| #define SYSCTL_RCGC2_GPIOE 0x00000010 |
| #define SYSCTL_RCGC2_GPIOF 0x00000020 |
| #define SYSCTL_RCGC2_GPIOG 0x00000040 |
| #define SYSCTL_RCGC2_GPIOH 0x00000080 |
| #define SYSCTL_RCGC2_GPIOJ 0x00000100 |
| #define SYSCTL_RCGC2_R (*((volatile uint32_t *)0x400FE108)) |
| #define SYSCTL_RCGC2_UDMA 0x00002000 |
| #define SYSCTL_RCGC2_USB0 0x00010000 |
| #define SYSCTL_RCGCACMP_R (*((volatile uint32_t *)0x400FE63C)) |
| #define SYSCTL_RCGCACMP_R0 0x00000001 |
| #define SYSCTL_RCGCADC_R (*((volatile uint32_t *)0x400FE638)) |
| #define SYSCTL_RCGCADC_R0 0x00000001 |
| #define SYSCTL_RCGCADC_R1 0x00000002 |
| #define SYSCTL_RCGCCAN_R (*((volatile uint32_t *)0x400FE634)) |
| #define SYSCTL_RCGCCAN_R0 0x00000001 |
| #define SYSCTL_RCGCCAN_R1 0x00000002 |
| #define SYSCTL_RCGCDMA_R (*((volatile uint32_t *)0x400FE60C)) |
| #define SYSCTL_RCGCDMA_R0 0x00000001 |
| #define SYSCTL_RCGCEEPROM_R (*((volatile uint32_t *)0x400FE658)) |
| #define SYSCTL_RCGCEEPROM_R0 0x00000001 |
| #define SYSCTL_RCGCGPIO_R (*((volatile uint32_t *)0x400FE608)) |
| #define SYSCTL_RCGCGPIO_R0 0x00000001 |
| #define SYSCTL_RCGCGPIO_R1 0x00000002 |
| #define SYSCTL_RCGCGPIO_R10 0x00000400 |
| #define SYSCTL_RCGCGPIO_R11 0x00000800 |
| #define SYSCTL_RCGCGPIO_R12 0x00001000 |
| #define SYSCTL_RCGCGPIO_R13 0x00002000 |
| #define SYSCTL_RCGCGPIO_R2 0x00000004 |
| #define SYSCTL_RCGCGPIO_R3 0x00000008 |
| #define SYSCTL_RCGCGPIO_R4 0x00000010 |
| #define SYSCTL_RCGCGPIO_R5 0x00000020 |
| #define SYSCTL_RCGCGPIO_R6 0x00000040 |
| #define SYSCTL_RCGCGPIO_R7 0x00000080 |
| #define SYSCTL_RCGCGPIO_R8 0x00000100 |
| #define SYSCTL_RCGCGPIO_R9 0x00000200 |
| #define SYSCTL_RCGCHIB_R (*((volatile uint32_t *)0x400FE614)) |
| #define SYSCTL_RCGCHIB_R0 0x00000001 |
| #define SYSCTL_RCGCI2C_R (*((volatile uint32_t *)0x400FE620)) |
| #define SYSCTL_RCGCI2C_R0 0x00000001 |
| #define SYSCTL_RCGCI2C_R1 0x00000002 |
| #define SYSCTL_RCGCI2C_R2 0x00000004 |
| #define SYSCTL_RCGCI2C_R3 0x00000008 |
| #define SYSCTL_RCGCI2C_R4 0x00000010 |
| #define SYSCTL_RCGCI2C_R5 0x00000020 |
| #define SYSCTL_RCGCPWM_R (*((volatile uint32_t *)0x400FE640)) |
| #define SYSCTL_RCGCPWM_R0 0x00000001 |
| #define SYSCTL_RCGCPWM_R1 0x00000002 |
| #define SYSCTL_RCGCQEI_R (*((volatile uint32_t *)0x400FE644)) |
| #define SYSCTL_RCGCQEI_R0 0x00000001 |
| #define SYSCTL_RCGCQEI_R1 0x00000002 |
| #define SYSCTL_RCGCSSI_R (*((volatile uint32_t *)0x400FE61C)) |
| #define SYSCTL_RCGCSSI_R0 0x00000001 |
| #define SYSCTL_RCGCSSI_R1 0x00000002 |
| #define SYSCTL_RCGCSSI_R2 0x00000004 |
| #define SYSCTL_RCGCSSI_R3 0x00000008 |
| #define SYSCTL_RCGCTIMER_R (*((volatile uint32_t *)0x400FE604)) |
| #define SYSCTL_RCGCTIMER_R0 0x00000001 |
| #define SYSCTL_RCGCTIMER_R1 0x00000002 |
| #define SYSCTL_RCGCTIMER_R2 0x00000004 |
| #define SYSCTL_RCGCTIMER_R3 0x00000008 |
| #define SYSCTL_RCGCTIMER_R4 0x00000010 |
| #define SYSCTL_RCGCTIMER_R5 0x00000020 |
| #define SYSCTL_RCGCUART_R (*((volatile uint32_t *)0x400FE618)) |
| #define SYSCTL_RCGCUART_R0 0x00000001 |
| #define SYSCTL_RCGCUART_R1 0x00000002 |
| #define SYSCTL_RCGCUART_R2 0x00000004 |
| #define SYSCTL_RCGCUART_R3 0x00000008 |
| #define SYSCTL_RCGCUART_R4 0x00000010 |
| #define SYSCTL_RCGCUART_R5 0x00000020 |
| #define SYSCTL_RCGCUART_R6 0x00000040 |
| #define SYSCTL_RCGCUART_R7 0x00000080 |
| #define SYSCTL_RCGCUSB_R (*((volatile uint32_t *)0x400FE628)) |
| #define SYSCTL_RCGCUSB_R0 0x00000001 |
| #define SYSCTL_RCGCWD_R (*((volatile uint32_t *)0x400FE600)) |
| #define SYSCTL_RCGCWD_R0 0x00000001 |
| #define SYSCTL_RCGCWD_R1 0x00000002 |
| #define SYSCTL_RCGCWTIMER_R (*((volatile uint32_t *)0x400FE65C)) |
| #define SYSCTL_RCGCWTIMER_R0 0x00000001 |
| #define SYSCTL_RCGCWTIMER_R1 0x00000002 |
| #define SYSCTL_RCGCWTIMER_R2 0x00000004 |
| #define SYSCTL_RCGCWTIMER_R3 0x00000008 |
| #define SYSCTL_RCGCWTIMER_R4 0x00000010 |
| #define SYSCTL_RCGCWTIMER_R5 0x00000020 |
| #define SYSCTL_RESC_BOR 0x00000004 |
| #define SYSCTL_RESC_EXT 0x00000001 |
| #define SYSCTL_RESC_MOSCFAIL 0x00010000 |
| #define SYSCTL_RESC_POR 0x00000002 |
| #define SYSCTL_RESC_R (*((volatile uint32_t *)0x400FE05C)) |
| #define SYSCTL_RESC_SW 0x00000010 |
| #define SYSCTL_RESC_WDT0 0x00000008 |
| #define SYSCTL_RESC_WDT1 0x00000020 |
| #define SYSCTL_RIS_BOR0RIS 0x00000800 |
| #define SYSCTL_RIS_BOR1RIS 0x00000002 |
| #define SYSCTL_RIS_MOFRIS 0x00000008 |
| #define SYSCTL_RIS_MOSCPUPRIS 0x00000100 |
| #define SYSCTL_RIS_PLLLRIS 0x00000040 |
| #define SYSCTL_RIS_R (*((volatile uint32_t *)0x400FE050)) |
| #define SYSCTL_RIS_USBPLLLRIS 0x00000080 |
| #define SYSCTL_RIS_VDDARIS 0x00000400 |
| #define SYSCTL_SCGC0_ADC0 0x00010000 |
| #define SYSCTL_SCGC0_ADC1 0x00020000 |
| #define SYSCTL_SCGC0_CAN0 0x01000000 |
| #define SYSCTL_SCGC0_CAN1 0x02000000 |
| #define SYSCTL_SCGC0_HIB 0x00000040 |
| #define SYSCTL_SCGC0_PWM0 0x00100000 |
| #define SYSCTL_SCGC0_R (*((volatile uint32_t *)0x400FE110)) |
| #define SYSCTL_SCGC0_WDT0 0x00000008 |
| #define SYSCTL_SCGC0_WDT1 0x10000000 |
| #define SYSCTL_SCGC1_COMP0 0x01000000 |
| #define SYSCTL_SCGC1_COMP1 0x02000000 |
| #define SYSCTL_SCGC1_COMP2 0x04000000 |
| #define SYSCTL_SCGC1_I2C0 0x00001000 |
| #define SYSCTL_SCGC1_I2C1 0x00004000 |
| #define SYSCTL_SCGC1_QEI0 0x00000100 |
| #define SYSCTL_SCGC1_QEI1 0x00000200 |
| #define SYSCTL_SCGC1_R (*((volatile uint32_t *)0x400FE114)) |
| #define SYSCTL_SCGC1_SSI0 0x00000010 |
| #define SYSCTL_SCGC1_SSI1 0x00000020 |
| #define SYSCTL_SCGC1_TIMER0 0x00010000 |
| #define SYSCTL_SCGC1_TIMER1 0x00020000 |
| #define SYSCTL_SCGC1_TIMER2 0x00040000 |
| #define SYSCTL_SCGC1_TIMER3 0x00080000 |
| #define SYSCTL_SCGC1_UART0 0x00000001 |
| #define SYSCTL_SCGC1_UART1 0x00000002 |
| #define SYSCTL_SCGC1_UART2 0x00000004 |
| #define SYSCTL_SCGC2_GPIOA 0x00000001 |
| #define SYSCTL_SCGC2_GPIOB 0x00000002 |
| #define SYSCTL_SCGC2_GPIOC 0x00000004 |
| #define SYSCTL_SCGC2_GPIOD 0x00000008 |
| #define SYSCTL_SCGC2_GPIOE 0x00000010 |
| #define SYSCTL_SCGC2_GPIOF 0x00000020 |
| #define SYSCTL_SCGC2_GPIOG 0x00000040 |
| #define SYSCTL_SCGC2_GPIOH 0x00000080 |
| #define SYSCTL_SCGC2_GPIOJ 0x00000100 |
| #define SYSCTL_SCGC2_R (*((volatile uint32_t *)0x400FE118)) |
| #define SYSCTL_SCGC2_UDMA 0x00002000 |
| #define SYSCTL_SCGC2_USB0 0x00010000 |
| #define SYSCTL_SCGCACMP_R (*((volatile uint32_t *)0x400FE73C)) |
| #define SYSCTL_SCGCACMP_S0 0x00000001 |
| #define SYSCTL_SCGCADC_R (*((volatile uint32_t *)0x400FE738)) |
| #define SYSCTL_SCGCADC_S0 0x00000001 |
| #define SYSCTL_SCGCADC_S1 0x00000002 |
| #define SYSCTL_SCGCCAN_R (*((volatile uint32_t *)0x400FE734)) |
| #define SYSCTL_SCGCCAN_S0 0x00000001 |
| #define SYSCTL_SCGCCAN_S1 0x00000002 |
| #define SYSCTL_SCGCDMA_R (*((volatile uint32_t *)0x400FE70C)) |
| #define SYSCTL_SCGCDMA_S0 0x00000001 |
| #define SYSCTL_SCGCEEPROM_R (*((volatile uint32_t *)0x400FE758)) |
| #define SYSCTL_SCGCEEPROM_S0 0x00000001 |
| #define SYSCTL_SCGCGPIO_R (*((volatile uint32_t *)0x400FE708)) |
| #define SYSCTL_SCGCGPIO_S0 0x00000001 |
| #define SYSCTL_SCGCGPIO_S1 0x00000002 |
| #define SYSCTL_SCGCGPIO_S10 0x00000400 |
| #define SYSCTL_SCGCGPIO_S11 0x00000800 |
| #define SYSCTL_SCGCGPIO_S12 0x00001000 |
| #define SYSCTL_SCGCGPIO_S13 0x00002000 |
| #define SYSCTL_SCGCGPIO_S2 0x00000004 |
| #define SYSCTL_SCGCGPIO_S3 0x00000008 |
| #define SYSCTL_SCGCGPIO_S4 0x00000010 |
| #define SYSCTL_SCGCGPIO_S5 0x00000020 |
| #define SYSCTL_SCGCGPIO_S6 0x00000040 |
| #define SYSCTL_SCGCGPIO_S7 0x00000080 |
| #define SYSCTL_SCGCGPIO_S8 0x00000100 |
| #define SYSCTL_SCGCGPIO_S9 0x00000200 |
| #define SYSCTL_SCGCHIB_R (*((volatile uint32_t *)0x400FE714)) |
| #define SYSCTL_SCGCHIB_S0 0x00000001 |
| #define SYSCTL_SCGCI2C_R (*((volatile uint32_t *)0x400FE720)) |
| #define SYSCTL_SCGCI2C_S0 0x00000001 |
| #define SYSCTL_SCGCI2C_S1 0x00000002 |
| #define SYSCTL_SCGCI2C_S2 0x00000004 |
| #define SYSCTL_SCGCI2C_S3 0x00000008 |
| #define SYSCTL_SCGCI2C_S4 0x00000010 |
| #define SYSCTL_SCGCI2C_S5 0x00000020 |
| #define SYSCTL_SCGCPWM_R (*((volatile uint32_t *)0x400FE740)) |
| #define SYSCTL_SCGCPWM_S0 0x00000001 |
| #define SYSCTL_SCGCPWM_S1 0x00000002 |
| #define SYSCTL_SCGCQEI_R (*((volatile uint32_t *)0x400FE744)) |
| #define SYSCTL_SCGCQEI_S0 0x00000001 |
| #define SYSCTL_SCGCQEI_S1 0x00000002 |
| #define SYSCTL_SCGCSSI_R (*((volatile uint32_t *)0x400FE71C)) |
| #define SYSCTL_SCGCSSI_S0 0x00000001 |
| #define SYSCTL_SCGCSSI_S1 0x00000002 |
| #define SYSCTL_SCGCSSI_S2 0x00000004 |
| #define SYSCTL_SCGCSSI_S3 0x00000008 |
| #define SYSCTL_SCGCTIMER_R (*((volatile uint32_t *)0x400FE704)) |
| #define SYSCTL_SCGCTIMER_S0 0x00000001 |
| #define SYSCTL_SCGCTIMER_S1 0x00000002 |
| #define SYSCTL_SCGCTIMER_S2 0x00000004 |
| #define SYSCTL_SCGCTIMER_S3 0x00000008 |
| #define SYSCTL_SCGCTIMER_S4 0x00000010 |
| #define SYSCTL_SCGCTIMER_S5 0x00000020 |
| #define SYSCTL_SCGCUART_R (*((volatile uint32_t *)0x400FE718)) |
| #define SYSCTL_SCGCUART_S0 0x00000001 |
| #define SYSCTL_SCGCUART_S1 0x00000002 |
| #define SYSCTL_SCGCUART_S2 0x00000004 |
| #define SYSCTL_SCGCUART_S3 0x00000008 |
| #define SYSCTL_SCGCUART_S4 0x00000010 |
| #define SYSCTL_SCGCUART_S5 0x00000020 |
| #define SYSCTL_SCGCUART_S6 0x00000040 |
| #define SYSCTL_SCGCUART_S7 0x00000080 |
| #define SYSCTL_SCGCUSB_R (*((volatile uint32_t *)0x400FE728)) |
| #define SYSCTL_SCGCUSB_S0 0x00000001 |
| #define SYSCTL_SCGCWD_R (*((volatile uint32_t *)0x400FE700)) |
| #define SYSCTL_SCGCWD_S0 0x00000001 |
| #define SYSCTL_SCGCWD_S1 0x00000002 |
| #define SYSCTL_SCGCWTIMER_R (*((volatile uint32_t *)0x400FE75C)) |
| #define SYSCTL_SCGCWTIMER_S0 0x00000001 |
| #define SYSCTL_SCGCWTIMER_S1 0x00000002 |
| #define SYSCTL_SCGCWTIMER_S2 0x00000004 |
| #define SYSCTL_SCGCWTIMER_S3 0x00000008 |
| #define SYSCTL_SCGCWTIMER_S4 0x00000010 |
| #define SYSCTL_SCGCWTIMER_S5 0x00000020 |
| #define SYSCTL_SLPPWRCFG_FLASHPM_M 0x00000030 |
| #define SYSCTL_SLPPWRCFG_FLASHPM_NRM 0x00000000 |
| #define SYSCTL_SLPPWRCFG_FLASHPM_SLP 0x00000020 |
| #define SYSCTL_SLPPWRCFG_R (*((volatile uint32_t *)0x400FE188)) |
| #define SYSCTL_SLPPWRCFG_SRAMPM_LP 0x00000003 |
| #define SYSCTL_SLPPWRCFG_SRAMPM_M 0x00000003 |
| #define SYSCTL_SLPPWRCFG_SRAMPM_NRM 0x00000000 |
| #define SYSCTL_SLPPWRCFG_SRAMPM_SBY 0x00000001 |
| #define SYSCTL_SRACMP_R (*((volatile uint32_t *)0x400FE53C)) |
| #define SYSCTL_SRACMP_R0 0x00000001 |
| #define SYSCTL_SRADC_R (*((volatile uint32_t *)0x400FE538)) |
| #define SYSCTL_SRADC_R0 0x00000001 |
| #define SYSCTL_SRADC_R1 0x00000002 |
| #define SYSCTL_SRCAN_R (*((volatile uint32_t *)0x400FE534)) |
| #define SYSCTL_SRCAN_R0 0x00000001 |
| #define SYSCTL_SRCAN_R1 0x00000002 |
| #define SYSCTL_SRCR0_ADC0 0x00010000 |
| #define SYSCTL_SRCR0_ADC1 0x00020000 |
| #define SYSCTL_SRCR0_CAN0 0x01000000 |
| #define SYSCTL_SRCR0_CAN1 0x02000000 |
| #define SYSCTL_SRCR0_HIB 0x00000040 |
| #define SYSCTL_SRCR0_PWM0 0x00100000 |
| #define SYSCTL_SRCR0_R (*((volatile uint32_t *)0x400FE040)) |
| #define SYSCTL_SRCR0_WDT0 0x00000008 |
| #define SYSCTL_SRCR0_WDT1 0x10000000 |
| #define SYSCTL_SRCR1_COMP0 0x01000000 |
| #define SYSCTL_SRCR1_COMP1 0x02000000 |
| #define SYSCTL_SRCR1_COMP2 0x04000000 |
| #define SYSCTL_SRCR1_I2C0 0x00001000 |
| #define SYSCTL_SRCR1_I2C1 0x00004000 |
| #define SYSCTL_SRCR1_QEI0 0x00000100 |
| #define SYSCTL_SRCR1_QEI1 0x00000200 |
| #define SYSCTL_SRCR1_R (*((volatile uint32_t *)0x400FE044)) |
| #define SYSCTL_SRCR1_SSI0 0x00000010 |
| #define SYSCTL_SRCR1_SSI1 0x00000020 |
| #define SYSCTL_SRCR1_TIMER0 0x00010000 |
| #define SYSCTL_SRCR1_TIMER1 0x00020000 |
| #define SYSCTL_SRCR1_TIMER2 0x00040000 |
| #define SYSCTL_SRCR1_TIMER3 0x00080000 |
| #define SYSCTL_SRCR1_UART0 0x00000001 |
| #define SYSCTL_SRCR1_UART1 0x00000002 |
| #define SYSCTL_SRCR1_UART2 0x00000004 |
| #define SYSCTL_SRCR2_GPIOA 0x00000001 |
| #define SYSCTL_SRCR2_GPIOB 0x00000002 |
| #define SYSCTL_SRCR2_GPIOC 0x00000004 |
| #define SYSCTL_SRCR2_GPIOD 0x00000008 |
| #define SYSCTL_SRCR2_GPIOE 0x00000010 |
| #define SYSCTL_SRCR2_GPIOF 0x00000020 |
| #define SYSCTL_SRCR2_GPIOG 0x00000040 |
| #define SYSCTL_SRCR2_GPIOH 0x00000080 |
| #define SYSCTL_SRCR2_GPIOJ 0x00000100 |
| #define SYSCTL_SRCR2_R (*((volatile uint32_t *)0x400FE048)) |
| #define SYSCTL_SRCR2_UDMA 0x00002000 |
| #define SYSCTL_SRCR2_USB0 0x00010000 |
| #define SYSCTL_SRDMA_R (*((volatile uint32_t *)0x400FE50C)) |
| #define SYSCTL_SRDMA_R0 0x00000001 |
| #define SYSCTL_SREEPROM_R (*((volatile uint32_t *)0x400FE558)) |
| #define SYSCTL_SREEPROM_R0 0x00000001 |
| #define SYSCTL_SRGPIO_R (*((volatile uint32_t *)0x400FE508)) |
| #define SYSCTL_SRGPIO_R0 0x00000001 |
| #define SYSCTL_SRGPIO_R1 0x00000002 |
| #define SYSCTL_SRGPIO_R10 0x00000400 |
| #define SYSCTL_SRGPIO_R11 0x00000800 |
| #define SYSCTL_SRGPIO_R12 0x00001000 |
| #define SYSCTL_SRGPIO_R13 0x00002000 |
| #define SYSCTL_SRGPIO_R2 0x00000004 |
| #define SYSCTL_SRGPIO_R3 0x00000008 |
| #define SYSCTL_SRGPIO_R4 0x00000010 |
| #define SYSCTL_SRGPIO_R5 0x00000020 |
| #define SYSCTL_SRGPIO_R6 0x00000040 |
| #define SYSCTL_SRGPIO_R7 0x00000080 |
| #define SYSCTL_SRGPIO_R8 0x00000100 |
| #define SYSCTL_SRGPIO_R9 0x00000200 |
| #define SYSCTL_SRHIB_R (*((volatile uint32_t *)0x400FE514)) |
| #define SYSCTL_SRHIB_R0 0x00000001 |
| #define SYSCTL_SRI2C_R (*((volatile uint32_t *)0x400FE520)) |
| #define SYSCTL_SRI2C_R0 0x00000001 |
| #define SYSCTL_SRI2C_R1 0x00000002 |
| #define SYSCTL_SRI2C_R2 0x00000004 |
| #define SYSCTL_SRI2C_R3 0x00000008 |
| #define SYSCTL_SRI2C_R4 0x00000010 |
| #define SYSCTL_SRI2C_R5 0x00000020 |
| #define SYSCTL_SRPWM_R (*((volatile uint32_t *)0x400FE540)) |
| #define SYSCTL_SRPWM_R0 0x00000001 |
| #define SYSCTL_SRPWM_R1 0x00000002 |
| #define SYSCTL_SRQEI_R (*((volatile uint32_t *)0x400FE544)) |
| #define SYSCTL_SRQEI_R0 0x00000001 |
| #define SYSCTL_SRQEI_R1 0x00000002 |
| #define SYSCTL_SRSSI_R (*((volatile uint32_t *)0x400FE51C)) |
| #define SYSCTL_SRSSI_R0 0x00000001 |
| #define SYSCTL_SRSSI_R1 0x00000002 |
| #define SYSCTL_SRSSI_R2 0x00000004 |
| #define SYSCTL_SRSSI_R3 0x00000008 |
| #define SYSCTL_SRTIMER_R (*((volatile uint32_t *)0x400FE504)) |
| #define SYSCTL_SRTIMER_R0 0x00000001 |
| #define SYSCTL_SRTIMER_R1 0x00000002 |
| #define SYSCTL_SRTIMER_R2 0x00000004 |
| #define SYSCTL_SRTIMER_R3 0x00000008 |
| #define SYSCTL_SRTIMER_R4 0x00000010 |
| #define SYSCTL_SRTIMER_R5 0x00000020 |
| #define SYSCTL_SRUART_R (*((volatile uint32_t *)0x400FE518)) |
| #define SYSCTL_SRUART_R0 0x00000001 |
| #define SYSCTL_SRUART_R1 0x00000002 |
| #define SYSCTL_SRUART_R2 0x00000004 |
| #define SYSCTL_SRUART_R3 0x00000008 |
| #define SYSCTL_SRUART_R4 0x00000010 |
| #define SYSCTL_SRUART_R5 0x00000020 |
| #define SYSCTL_SRUART_R6 0x00000040 |
| #define SYSCTL_SRUART_R7 0x00000080 |
| #define SYSCTL_SRUSB_R (*((volatile uint32_t *)0x400FE528)) |
| #define SYSCTL_SRUSB_R0 0x00000001 |
| #define SYSCTL_SRWD_R (*((volatile uint32_t *)0x400FE500)) |
| #define SYSCTL_SRWD_R0 0x00000001 |
| #define SYSCTL_SRWD_R1 0x00000002 |
| #define SYSCTL_SRWTIMER_R (*((volatile uint32_t *)0x400FE55C)) |
| #define SYSCTL_SRWTIMER_R0 0x00000001 |
| #define SYSCTL_SRWTIMER_R1 0x00000002 |
| #define SYSCTL_SRWTIMER_R2 0x00000004 |
| #define SYSCTL_SRWTIMER_R3 0x00000008 |
| #define SYSCTL_SRWTIMER_R4 0x00000010 |
| #define SYSCTL_SRWTIMER_R5 0x00000020 |
| #define SYSCTL_SYSPROP_FPU 0x00000001 |
| #define SYSCTL_SYSPROP_R (*((volatile uint32_t *)0x400FE14C)) |
| #define SYSEXC_IC_FPDZCIC 0x00000002 |
| #define SYSEXC_IC_FPIDCIC 0x00000001 |
| #define SYSEXC_IC_FPIOCIC 0x00000004 |
| #define SYSEXC_IC_FPIXCIC 0x00000020 |
| #define SYSEXC_IC_FPOFCIC 0x00000010 |
| #define SYSEXC_IC_FPUFCIC 0x00000008 |
| #define SYSEXC_IC_R (*((volatile uint32_t *)0x400F900C)) |
| #define SYSEXC_IM_FPDZCIM 0x00000002 |
| #define SYSEXC_IM_FPIDCIM 0x00000001 |
| #define SYSEXC_IM_FPIOCIM 0x00000004 |
| #define SYSEXC_IM_FPIXCIM 0x00000020 |
| #define SYSEXC_IM_FPOFCIM 0x00000010 |
| #define SYSEXC_IM_FPUFCIM 0x00000008 |
| #define SYSEXC_IM_R (*((volatile uint32_t *)0x400F9004)) |
| #define SYSEXC_MIS_FPDZCMIS 0x00000002 |
| #define SYSEXC_MIS_FPIDCMIS 0x00000001 |
| #define SYSEXC_MIS_FPIOCMIS 0x00000004 |
| #define SYSEXC_MIS_FPIXCMIS 0x00000020 |
| #define SYSEXC_MIS_FPOFCMIS 0x00000010 |
| #define SYSEXC_MIS_FPUFCMIS 0x00000008 |
| #define SYSEXC_MIS_R (*((volatile uint32_t *)0x400F9008)) |
| #define SYSEXC_RIS_FPDZCRIS 0x00000002 |
| #define SYSEXC_RIS_FPIDCRIS 0x00000001 |
| #define SYSEXC_RIS_FPIOCRIS 0x00000004 |
| #define SYSEXC_RIS_FPIXCRIS 0x00000020 |
| #define SYSEXC_RIS_FPOFCRIS 0x00000010 |
| #define SYSEXC_RIS_FPUFCRIS 0x00000008 |
| #define SYSEXC_RIS_R (*((volatile uint32_t *)0x400F9000)) |
| #define TIMER0_CFG_R (*((volatile uint32_t *)0x40030000)) |
| #define TIMER0_CTL_R (*((volatile uint32_t *)0x4003000C)) |
| #define TIMER0_ICR_R (*((volatile uint32_t *)0x40030024)) |
| #define TIMER0_IMR_R (*((volatile uint32_t *)0x40030018)) |
| #define TIMER0_MIS_R (*((volatile uint32_t *)0x40030020)) |
| #define TIMER0_PP_R (*((volatile uint32_t *)0x40030FC0)) |
| #define TIMER0_RIS_R (*((volatile uint32_t *)0x4003001C)) |
| #define TIMER0_RTCPD_R (*((volatile uint32_t *)0x40030058)) |
| #define TIMER0_SYNC_R (*((volatile uint32_t *)0x40030010)) |
| #define TIMER0_TAILR_R (*((volatile uint32_t *)0x40030028)) |
| #define TIMER0_TAMATCHR_R (*((volatile uint32_t *)0x40030030)) |
| #define TIMER0_TAMR_R (*((volatile uint32_t *)0x40030004)) |
| #define TIMER0_TAPMR_R (*((volatile uint32_t *)0x40030040)) |
| #define TIMER0_TAPR_R (*((volatile uint32_t *)0x40030038)) |
| #define TIMER0_TAPS_R (*((volatile uint32_t *)0x4003005C)) |
| #define TIMER0_TAPV_R (*((volatile uint32_t *)0x40030064)) |
| #define TIMER0_TAR_R (*((volatile uint32_t *)0x40030048)) |
| #define TIMER0_TAV_R (*((volatile uint32_t *)0x40030050)) |
| #define TIMER0_TBILR_R (*((volatile uint32_t *)0x4003002C)) |
| #define TIMER0_TBMATCHR_R (*((volatile uint32_t *)0x40030034)) |
| #define TIMER0_TBMR_R (*((volatile uint32_t *)0x40030008)) |
| #define TIMER0_TBPMR_R (*((volatile uint32_t *)0x40030044)) |
| #define TIMER0_TBPR_R (*((volatile uint32_t *)0x4003003C)) |
| #define TIMER0_TBPS_R (*((volatile uint32_t *)0x40030060)) |
| #define TIMER0_TBPV_R (*((volatile uint32_t *)0x40030068)) |
| #define TIMER0_TBR_R (*((volatile uint32_t *)0x4003004C)) |
| #define TIMER0_TBV_R (*((volatile uint32_t *)0x40030054)) |
| #define TIMER1_CFG_R (*((volatile uint32_t *)0x40031000)) |
| #define TIMER1_CTL_R (*((volatile uint32_t *)0x4003100C)) |
| #define TIMER1_ICR_R (*((volatile uint32_t *)0x40031024)) |
| #define TIMER1_IMR_R (*((volatile uint32_t *)0x40031018)) |
| #define TIMER1_MIS_R (*((volatile uint32_t *)0x40031020)) |
| #define TIMER1_PP_R (*((volatile uint32_t *)0x40031FC0)) |
| #define TIMER1_RIS_R (*((volatile uint32_t *)0x4003101C)) |
| #define TIMER1_RTCPD_R (*((volatile uint32_t *)0x40031058)) |
| #define TIMER1_SYNC_R (*((volatile uint32_t *)0x40031010)) |
| #define TIMER1_TAILR_R (*((volatile uint32_t *)0x40031028)) |
| #define TIMER1_TAMATCHR_R (*((volatile uint32_t *)0x40031030)) |
| #define TIMER1_TAMR_R (*((volatile uint32_t *)0x40031004)) |
| #define TIMER1_TAPMR_R (*((volatile uint32_t *)0x40031040)) |
| #define TIMER1_TAPR_R (*((volatile uint32_t *)0x40031038)) |
| #define TIMER1_TAPS_R (*((volatile uint32_t *)0x4003105C)) |
| #define TIMER1_TAPV_R (*((volatile uint32_t *)0x40031064)) |
| #define TIMER1_TAR_R (*((volatile uint32_t *)0x40031048)) |
| #define TIMER1_TAV_R (*((volatile uint32_t *)0x40031050)) |
| #define TIMER1_TBILR_R (*((volatile uint32_t *)0x4003102C)) |
| #define TIMER1_TBMATCHR_R (*((volatile uint32_t *)0x40031034)) |
| #define TIMER1_TBMR_R (*((volatile uint32_t *)0x40031008)) |
| #define TIMER1_TBPMR_R (*((volatile uint32_t *)0x40031044)) |
| #define TIMER1_TBPR_R (*((volatile uint32_t *)0x4003103C)) |
| #define TIMER1_TBPS_R (*((volatile uint32_t *)0x40031060)) |
| #define TIMER1_TBPV_R (*((volatile uint32_t *)0x40031068)) |
| #define TIMER1_TBR_R (*((volatile uint32_t *)0x4003104C)) |
| #define TIMER1_TBV_R (*((volatile uint32_t *)0x40031054)) |
| #define TIMER2_CFG_R (*((volatile uint32_t *)0x40032000)) |
| #define TIMER2_CTL_R (*((volatile uint32_t *)0x4003200C)) |
| #define TIMER2_ICR_R (*((volatile uint32_t *)0x40032024)) |
| #define TIMER2_IMR_R (*((volatile uint32_t *)0x40032018)) |
| #define TIMER2_MIS_R (*((volatile uint32_t *)0x40032020)) |
| #define TIMER2_PP_R (*((volatile uint32_t *)0x40032FC0)) |
| #define TIMER2_RIS_R (*((volatile uint32_t *)0x4003201C)) |
| #define TIMER2_RTCPD_R (*((volatile uint32_t *)0x40032058)) |
| #define TIMER2_SYNC_R (*((volatile uint32_t *)0x40032010)) |
| #define TIMER2_TAILR_R (*((volatile uint32_t *)0x40032028)) |
| #define TIMER2_TAMATCHR_R (*((volatile uint32_t *)0x40032030)) |
| #define TIMER2_TAMR_R (*((volatile uint32_t *)0x40032004)) |
| #define TIMER2_TAPMR_R (*((volatile uint32_t *)0x40032040)) |
| #define TIMER2_TAPR_R (*((volatile uint32_t *)0x40032038)) |
| #define TIMER2_TAPS_R (*((volatile uint32_t *)0x4003205C)) |
| #define TIMER2_TAPV_R (*((volatile uint32_t *)0x40032064)) |
| #define TIMER2_TAR_R (*((volatile uint32_t *)0x40032048)) |
| #define TIMER2_TAV_R (*((volatile uint32_t *)0x40032050)) |
| #define TIMER2_TBILR_R (*((volatile uint32_t *)0x4003202C)) |
| #define TIMER2_TBMATCHR_R (*((volatile uint32_t *)0x40032034)) |
| #define TIMER2_TBMR_R (*((volatile uint32_t *)0x40032008)) |
| #define TIMER2_TBPMR_R (*((volatile uint32_t *)0x40032044)) |
| #define TIMER2_TBPR_R (*((volatile uint32_t *)0x4003203C)) |
| #define TIMER2_TBPS_R (*((volatile uint32_t *)0x40032060)) |
| #define TIMER2_TBPV_R (*((volatile uint32_t *)0x40032068)) |
| #define TIMER2_TBR_R (*((volatile uint32_t *)0x4003204C)) |
| #define TIMER2_TBV_R (*((volatile uint32_t *)0x40032054)) |
| #define TIMER3_CFG_R (*((volatile uint32_t *)0x40033000)) |
| #define TIMER3_CTL_R (*((volatile uint32_t *)0x4003300C)) |
| #define TIMER3_ICR_R (*((volatile uint32_t *)0x40033024)) |
| #define TIMER3_IMR_R (*((volatile uint32_t *)0x40033018)) |
| #define TIMER3_MIS_R (*((volatile uint32_t *)0x40033020)) |
| #define TIMER3_PP_R (*((volatile uint32_t *)0x40033FC0)) |
| #define TIMER3_RIS_R (*((volatile uint32_t *)0x4003301C)) |
| #define TIMER3_RTCPD_R (*((volatile uint32_t *)0x40033058)) |
| #define TIMER3_SYNC_R (*((volatile uint32_t *)0x40033010)) |
| #define TIMER3_TAILR_R (*((volatile uint32_t *)0x40033028)) |
| #define TIMER3_TAMATCHR_R (*((volatile uint32_t *)0x40033030)) |
| #define TIMER3_TAMR_R (*((volatile uint32_t *)0x40033004)) |
| #define TIMER3_TAPMR_R (*((volatile uint32_t *)0x40033040)) |
| #define TIMER3_TAPR_R (*((volatile uint32_t *)0x40033038)) |
| #define TIMER3_TAPS_R (*((volatile uint32_t *)0x4003305C)) |
| #define TIMER3_TAPV_R (*((volatile uint32_t *)0x40033064)) |
| #define TIMER3_TAR_R (*((volatile uint32_t *)0x40033048)) |
| #define TIMER3_TAV_R (*((volatile uint32_t *)0x40033050)) |
| #define TIMER3_TBILR_R (*((volatile uint32_t *)0x4003302C)) |
| #define TIMER3_TBMATCHR_R (*((volatile uint32_t *)0x40033034)) |
| #define TIMER3_TBMR_R (*((volatile uint32_t *)0x40033008)) |
| #define TIMER3_TBPMR_R (*((volatile uint32_t *)0x40033044)) |
| #define TIMER3_TBPR_R (*((volatile uint32_t *)0x4003303C)) |
| #define TIMER3_TBPS_R (*((volatile uint32_t *)0x40033060)) |
| #define TIMER3_TBPV_R (*((volatile uint32_t *)0x40033068)) |
| #define TIMER3_TBR_R (*((volatile uint32_t *)0x4003304C)) |
| #define TIMER3_TBV_R (*((volatile uint32_t *)0x40033054)) |
| #define TIMER4_CFG_R (*((volatile uint32_t *)0x40034000)) |
| #define TIMER4_CTL_R (*((volatile uint32_t *)0x4003400C)) |
| #define TIMER4_ICR_R (*((volatile uint32_t *)0x40034024)) |
| #define TIMER4_IMR_R (*((volatile uint32_t *)0x40034018)) |
| #define TIMER4_MIS_R (*((volatile uint32_t *)0x40034020)) |
| #define TIMER4_PP_R (*((volatile uint32_t *)0x40034FC0)) |
| #define TIMER4_RIS_R (*((volatile uint32_t *)0x4003401C)) |
| #define TIMER4_RTCPD_R (*((volatile uint32_t *)0x40034058)) |
| #define TIMER4_SYNC_R (*((volatile uint32_t *)0x40034010)) |
| #define TIMER4_TAILR_R (*((volatile uint32_t *)0x40034028)) |
| #define TIMER4_TAMATCHR_R (*((volatile uint32_t *)0x40034030)) |
| #define TIMER4_TAMR_R (*((volatile uint32_t *)0x40034004)) |
| #define TIMER4_TAPMR_R (*((volatile uint32_t *)0x40034040)) |
| #define TIMER4_TAPR_R (*((volatile uint32_t *)0x40034038)) |
| #define TIMER4_TAPS_R (*((volatile uint32_t *)0x4003405C)) |
| #define TIMER4_TAPV_R (*((volatile uint32_t *)0x40034064)) |
| #define TIMER4_TAR_R (*((volatile uint32_t *)0x40034048)) |
| #define TIMER4_TAV_R (*((volatile uint32_t *)0x40034050)) |
| #define TIMER4_TBILR_R (*((volatile uint32_t *)0x4003402C)) |
| #define TIMER4_TBMATCHR_R (*((volatile uint32_t *)0x40034034)) |
| #define TIMER4_TBMR_R (*((volatile uint32_t *)0x40034008)) |
| #define TIMER4_TBPMR_R (*((volatile uint32_t *)0x40034044)) |
| #define TIMER4_TBPR_R (*((volatile uint32_t *)0x4003403C)) |
| #define TIMER4_TBPS_R (*((volatile uint32_t *)0x40034060)) |
| #define TIMER4_TBPV_R (*((volatile uint32_t *)0x40034068)) |
| #define TIMER4_TBR_R (*((volatile uint32_t *)0x4003404C)) |
| #define TIMER4_TBV_R (*((volatile uint32_t *)0x40034054)) |
| #define TIMER5_CFG_R (*((volatile uint32_t *)0x40035000)) |
| #define TIMER5_CTL_R (*((volatile uint32_t *)0x4003500C)) |
| #define TIMER5_ICR_R (*((volatile uint32_t *)0x40035024)) |
| #define TIMER5_IMR_R (*((volatile uint32_t *)0x40035018)) |
| #define TIMER5_MIS_R (*((volatile uint32_t *)0x40035020)) |
| #define TIMER5_PP_R (*((volatile uint32_t *)0x40035FC0)) |
| #define TIMER5_RIS_R (*((volatile uint32_t *)0x4003501C)) |
| #define TIMER5_RTCPD_R (*((volatile uint32_t *)0x40035058)) |
| #define TIMER5_SYNC_R (*((volatile uint32_t *)0x40035010)) |
| #define TIMER5_TAILR_R (*((volatile uint32_t *)0x40035028)) |
| #define TIMER5_TAMATCHR_R (*((volatile uint32_t *)0x40035030)) |
| #define TIMER5_TAMR_R (*((volatile uint32_t *)0x40035004)) |
| #define TIMER5_TAPMR_R (*((volatile uint32_t *)0x40035040)) |
| #define TIMER5_TAPR_R (*((volatile uint32_t *)0x40035038)) |
| #define TIMER5_TAPS_R (*((volatile uint32_t *)0x4003505C)) |
| #define TIMER5_TAPV_R (*((volatile uint32_t *)0x40035064)) |
| #define TIMER5_TAR_R (*((volatile uint32_t *)0x40035048)) |
| #define TIMER5_TAV_R (*((volatile uint32_t *)0x40035050)) |
| #define TIMER5_TBILR_R (*((volatile uint32_t *)0x4003502C)) |
| #define TIMER5_TBMATCHR_R (*((volatile uint32_t *)0x40035034)) |
| #define TIMER5_TBMR_R (*((volatile uint32_t *)0x40035008)) |
| #define TIMER5_TBPMR_R (*((volatile uint32_t *)0x40035044)) |
| #define TIMER5_TBPR_R (*((volatile uint32_t *)0x4003503C)) |
| #define TIMER5_TBPS_R (*((volatile uint32_t *)0x40035060)) |
| #define TIMER5_TBPV_R (*((volatile uint32_t *)0x40035068)) |
| #define TIMER5_TBR_R (*((volatile uint32_t *)0x4003504C)) |
| #define TIMER5_TBV_R (*((volatile uint32_t *)0x40035054)) |
| #define TIMER_CFG_16_BIT 0x00000004 |
| #define TIMER_CFG_32_BIT_RTC 0x00000001 |
| #define TIMER_CFG_32_BIT_TIMER 0x00000000 |
| #define TIMER_CFG_M 0x00000007 |
| #define TIMER_CTL_RTCEN 0x00000010 |
| #define TIMER_CTL_TAEN 0x00000001 |
| #define TIMER_CTL_TAEVENT_BOTH 0x0000000C |
| #define TIMER_CTL_TAEVENT_M 0x0000000C |
| #define TIMER_CTL_TAEVENT_NEG 0x00000004 |
| #define TIMER_CTL_TAEVENT_POS 0x00000000 |
| #define TIMER_CTL_TAOTE 0x00000020 |
| #define TIMER_CTL_TAPWML 0x00000040 |
| #define TIMER_CTL_TASTALL 0x00000002 |
| #define TIMER_CTL_TBEN 0x00000100 |
| #define TIMER_CTL_TBEVENT_BOTH 0x00000C00 |
| #define TIMER_CTL_TBEVENT_M 0x00000C00 |
| #define TIMER_CTL_TBEVENT_NEG 0x00000400 |
| #define TIMER_CTL_TBEVENT_POS 0x00000000 |
| #define TIMER_CTL_TBOTE 0x00002000 |
| #define TIMER_CTL_TBPWML 0x00004000 |
| #define TIMER_CTL_TBSTALL 0x00000200 |
| #define TIMER_ICR_CAECINT 0x00000004 |
| #define TIMER_ICR_CAMCINT 0x00000002 |
| #define TIMER_ICR_CBECINT 0x00000400 |
| #define TIMER_ICR_CBMCINT 0x00000200 |
| #define TIMER_ICR_RTCCINT 0x00000008 |
| #define TIMER_ICR_TAMCINT 0x00000010 |
| #define TIMER_ICR_TATOCINT 0x00000001 |
| #define TIMER_ICR_TBMCINT 0x00000800 |
| #define TIMER_ICR_TBTOCINT 0x00000100 |
| #define TIMER_ICR_WUECINT 0x00010000 |
| #define TIMER_IMR_CAEIM 0x00000004 |
| #define TIMER_IMR_CAMIM 0x00000002 |
| #define TIMER_IMR_CBEIM 0x00000400 |
| #define TIMER_IMR_CBMIM 0x00000200 |
| #define TIMER_IMR_RTCIM 0x00000008 |
| #define TIMER_IMR_TAMIM 0x00000010 |
| #define TIMER_IMR_TATOIM 0x00000001 |
| #define TIMER_IMR_TBMIM 0x00000800 |
| #define TIMER_IMR_TBTOIM 0x00000100 |
| #define TIMER_IMR_WUEIM 0x00010000 |
| #define TIMER_MIS_CAEMIS 0x00000004 |
| #define TIMER_MIS_CAMMIS 0x00000002 |
| #define TIMER_MIS_CBEMIS 0x00000400 |
| #define TIMER_MIS_CBMMIS 0x00000200 |
| #define TIMER_MIS_RTCMIS 0x00000008 |
| #define TIMER_MIS_TAMMIS 0x00000010 |
| #define TIMER_MIS_TATOMIS 0x00000001 |
| #define TIMER_MIS_TBMMIS 0x00000800 |
| #define TIMER_MIS_TBTOMIS 0x00000100 |
| #define TIMER_MIS_WUEMIS 0x00010000 |
| #define TIMER_PP_SIZE_16 0x00000000 |
| #define TIMER_PP_SIZE_32 0x00000001 |
| #define TIMER_PP_SIZE_M 0x0000000F |
| #define TIMER_RIS_CAERIS 0x00000004 |
| #define TIMER_RIS_CAMRIS 0x00000002 |
| #define TIMER_RIS_CBERIS 0x00000400 |
| #define TIMER_RIS_CBMRIS 0x00000200 |
| #define TIMER_RIS_RTCRIS 0x00000008 |
| #define TIMER_RIS_TAMRIS 0x00000010 |
| #define TIMER_RIS_TATORIS 0x00000001 |
| #define TIMER_RIS_TBMRIS 0x00000800 |
| #define TIMER_RIS_TBTORIS 0x00000100 |
| #define TIMER_RIS_WUERIS 0x00010000 |
| #define TIMER_RTCPD_RTCPD_M 0x0000FFFF |
| #define TIMER_RTCPD_RTCPD_S 0 |
| #define TIMER_SYNC_SYNCT0_M 0x00000003 |
| #define TIMER_SYNC_SYNCT0_NONE 0x00000000 |
| #define TIMER_SYNC_SYNCT0_TA 0x00000001 |
| #define TIMER_SYNC_SYNCT0_TATB 0x00000003 |
| #define TIMER_SYNC_SYNCT0_TB 0x00000002 |
| #define TIMER_SYNC_SYNCT1_M 0x0000000C |
| #define TIMER_SYNC_SYNCT1_NONE 0x00000000 |
| #define TIMER_SYNC_SYNCT1_TA 0x00000004 |
| #define TIMER_SYNC_SYNCT1_TATB 0x0000000C |
| #define TIMER_SYNC_SYNCT1_TB 0x00000008 |
| #define TIMER_SYNC_SYNCT2_M 0x00000030 |
| #define TIMER_SYNC_SYNCT2_NONE 0x00000000 |
| #define TIMER_SYNC_SYNCT2_TA 0x00000010 |
| #define TIMER_SYNC_SYNCT2_TATB 0x00000030 |
| #define TIMER_SYNC_SYNCT2_TB 0x00000020 |
| #define TIMER_SYNC_SYNCT3_M 0x000000C0 |
| #define TIMER_SYNC_SYNCT3_NONE 0x00000000 |
| #define TIMER_SYNC_SYNCT3_TA 0x00000040 |
| #define TIMER_SYNC_SYNCT3_TATB 0x000000C0 |
| #define TIMER_SYNC_SYNCT3_TB 0x00000080 |
| #define TIMER_SYNC_SYNCT4_M 0x00000300 |
| #define TIMER_SYNC_SYNCT4_NONE 0x00000000 |
| #define TIMER_SYNC_SYNCT4_TA 0x00000100 |
| #define TIMER_SYNC_SYNCT4_TATB 0x00000300 |
| #define TIMER_SYNC_SYNCT4_TB 0x00000200 |
| #define TIMER_SYNC_SYNCT5_M 0x00000C00 |
| #define TIMER_SYNC_SYNCT5_NONE 0x00000000 |
| #define TIMER_SYNC_SYNCT5_TA 0x00000400 |
| #define TIMER_SYNC_SYNCT5_TATB 0x00000C00 |
| #define TIMER_SYNC_SYNCT5_TB 0x00000800 |
| #define TIMER_SYNC_SYNCWT0_M 0x00003000 |
| #define TIMER_SYNC_SYNCWT0_NONE 0x00000000 |
| #define TIMER_SYNC_SYNCWT0_TA 0x00001000 |
| #define TIMER_SYNC_SYNCWT0_TATB 0x00003000 |
| #define TIMER_SYNC_SYNCWT0_TB 0x00002000 |
| #define TIMER_SYNC_SYNCWT1_M 0x0000C000 |
| #define TIMER_SYNC_SYNCWT1_NONE 0x00000000 |
| #define TIMER_SYNC_SYNCWT1_TA 0x00004000 |
| #define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 |
| #define TIMER_SYNC_SYNCWT1_TB 0x00008000 |
| #define TIMER_SYNC_SYNCWT2_M 0x00030000 |
| #define TIMER_SYNC_SYNCWT2_NONE 0x00000000 |
| #define TIMER_SYNC_SYNCWT2_TA 0x00010000 |
| #define TIMER_SYNC_SYNCWT2_TATB 0x00030000 |
| #define TIMER_SYNC_SYNCWT2_TB 0x00020000 |
| #define TIMER_SYNC_SYNCWT3_M 0x000C0000 |
| #define TIMER_SYNC_SYNCWT3_NONE 0x00000000 |
| #define TIMER_SYNC_SYNCWT3_TA 0x00040000 |
| #define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 |
| #define TIMER_SYNC_SYNCWT3_TB 0x00080000 |
| #define TIMER_SYNC_SYNCWT4_M 0x00300000 |
| #define TIMER_SYNC_SYNCWT4_NONE 0x00000000 |
| #define TIMER_SYNC_SYNCWT4_TA 0x00100000 |
| #define TIMER_SYNC_SYNCWT4_TATB 0x00300000 |
| #define TIMER_SYNC_SYNCWT4_TB 0x00200000 |
| #define TIMER_SYNC_SYNCWT5_M 0x00C00000 |
| #define TIMER_SYNC_SYNCWT5_NONE 0x00000000 |
| #define TIMER_SYNC_SYNCWT5_TA 0x00400000 |
| #define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 |
| #define TIMER_SYNC_SYNCWT5_TB 0x00800000 |
| #define TIMER_TAILR_M 0xFFFFFFFF |
| #define TIMER_TAILR_S 0 |
| #define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF |
| #define TIMER_TAMATCHR_TAMR_S 0 |
| #define TIMER_TAMR_TAAMS 0x00000008 |
| #define TIMER_TAMR_TACDIR 0x00000010 |
| #define TIMER_TAMR_TACMR 0x00000004 |
| #define TIMER_TAMR_TAILD 0x00000100 |
| #define TIMER_TAMR_TAMIE 0x00000020 |
| #define TIMER_TAMR_TAMR_1_SHOT 0x00000001 |
| #define TIMER_TAMR_TAMR_CAP 0x00000003 |
| #define TIMER_TAMR_TAMR_M 0x00000003 |
| #define TIMER_TAMR_TAMR_PERIOD 0x00000002 |
| #define TIMER_TAMR_TAMRSU 0x00000400 |
| #define TIMER_TAMR_TAPLO 0x00000800 |
| #define TIMER_TAMR_TAPWMIE 0x00000200 |
| #define TIMER_TAMR_TASNAPS 0x00000080 |
| #define TIMER_TAMR_TAWOT 0x00000040 |
| #define TIMER_TAPMR_TAPSMR_M 0x000000FF |
| #define TIMER_TAPMR_TAPSMR_S 0 |
| #define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 |
| #define TIMER_TAPMR_TAPSMRH_S 8 |
| #define TIMER_TAPR_TAPSR_M 0x000000FF |
| #define TIMER_TAPR_TAPSR_S 0 |
| #define TIMER_TAPR_TAPSRH_M 0x0000FF00 |
| #define TIMER_TAPR_TAPSRH_S 8 |
| #define TIMER_TAPS_PSS_M 0x0000FFFF |
| #define TIMER_TAPS_PSS_S 0 |
| #define TIMER_TAPV_PSV_M 0x0000FFFF |
| #define TIMER_TAPV_PSV_S 0 |
| #define TIMER_TAR_M 0xFFFFFFFF |
| #define TIMER_TAR_S 0 |
| #define TIMER_TAV_M 0xFFFFFFFF |
| #define TIMER_TAV_S 0 |
| #define TIMER_TBILR_M 0xFFFFFFFF |
| #define TIMER_TBILR_S 0 |
| #define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF |
| #define TIMER_TBMATCHR_TBMR_S 0 |
| #define TIMER_TBMR_TBAMS 0x00000008 |
| #define TIMER_TBMR_TBCDIR 0x00000010 |
| #define TIMER_TBMR_TBCMR 0x00000004 |
| #define TIMER_TBMR_TBILD 0x00000100 |
| #define TIMER_TBMR_TBMIE 0x00000020 |
| #define TIMER_TBMR_TBMR_1_SHOT 0x00000001 |
| #define TIMER_TBMR_TBMR_CAP 0x00000003 |
| #define TIMER_TBMR_TBMR_M 0x00000003 |
| #define TIMER_TBMR_TBMR_PERIOD 0x00000002 |
| #define TIMER_TBMR_TBMRSU 0x00000400 |
| #define TIMER_TBMR_TBPLO 0x00000800 |
| #define TIMER_TBMR_TBPWMIE 0x00000200 |
| #define TIMER_TBMR_TBSNAPS 0x00000080 |
| #define TIMER_TBMR_TBWOT 0x00000040 |
| #define TIMER_TBPMR_TBPSMR_M 0x000000FF |
| #define TIMER_TBPMR_TBPSMR_S 0 |
| #define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 |
| #define TIMER_TBPMR_TBPSMRH_S 8 |
| #define TIMER_TBPR_TBPSR_M 0x000000FF |
| #define TIMER_TBPR_TBPSR_S 0 |
| #define TIMER_TBPR_TBPSRH_M 0x0000FF00 |
| #define TIMER_TBPR_TBPSRH_S 8 |
| #define TIMER_TBPS_PSS_M 0x0000FFFF |
| #define TIMER_TBPS_PSS_S 0 |
| #define TIMER_TBPV_PSV_M 0x0000FFFF |
| #define TIMER_TBPV_PSV_S 0 |
| #define TIMER_TBR_M 0xFFFFFFFF |
| #define TIMER_TBR_S 0 |
| #define TIMER_TBV_M 0xFFFFFFFF |
| #define TIMER_TBV_S 0 |
| #define UART0_9BITADDR_R (*((volatile uint32_t *)0x4000C0A4)) |
| #define UART0_9BITAMASK_R (*((volatile uint32_t *)0x4000C0A8)) |
| #define UART0_CC_R (*((volatile uint32_t *)0x4000CFC8)) |
| #define UART0_CTL_R (*((volatile uint32_t *)0x4000C030)) |
| #define UART0_DMACTL_R (*((volatile uint32_t *)0x4000C048)) |
| #define UART0_DR_R (*((volatile uint32_t *)0x4000C000)) |
| #define UART0_ECR_R (*((volatile uint32_t *)0x4000C004)) |
| #define UART0_FBRD_R (*((volatile uint32_t *)0x4000C028)) |
| #define UART0_FR_R (*((volatile uint32_t *)0x4000C018)) |
| #define UART0_IBRD_R (*((volatile uint32_t *)0x4000C024)) |
| #define UART0_ICR_R (*((volatile uint32_t *)0x4000C044)) |
| #define UART0_IFLS_R (*((volatile uint32_t *)0x4000C034)) |
| #define UART0_ILPR_R (*((volatile uint32_t *)0x4000C020)) |
| #define UART0_IM_R (*((volatile uint32_t *)0x4000C038)) |
| #define UART0_LCRH_R (*((volatile uint32_t *)0x4000C02C)) |
| #define UART0_MIS_R (*((volatile uint32_t *)0x4000C040)) |
| #define UART0_PP_R (*((volatile uint32_t *)0x4000CFC0)) |
| #define UART0_RIS_R (*((volatile uint32_t *)0x4000C03C)) |
| #define UART0_RSR_R (*((volatile uint32_t *)0x4000C004)) |
| #define UART1_9BITADDR_R (*((volatile uint32_t *)0x4000D0A4)) |
| #define UART1_9BITAMASK_R (*((volatile uint32_t *)0x4000D0A8)) |
| #define UART1_CC_R (*((volatile uint32_t *)0x4000DFC8)) |
| #define UART1_CTL_R (*((volatile uint32_t *)0x4000D030)) |
| #define UART1_DMACTL_R (*((volatile uint32_t *)0x4000D048)) |
| #define UART1_DR_R (*((volatile uint32_t *)0x4000D000)) |
| #define UART1_ECR_R (*((volatile uint32_t *)0x4000D004)) |
| #define UART1_FBRD_R (*((volatile uint32_t *)0x4000D028)) |
| #define UART1_FR_R (*((volatile uint32_t *)0x4000D018)) |
| #define UART1_IBRD_R (*((volatile uint32_t *)0x4000D024)) |
| #define UART1_ICR_R (*((volatile uint32_t *)0x4000D044)) |
| #define UART1_IFLS_R (*((volatile uint32_t *)0x4000D034)) |
| #define UART1_ILPR_R (*((volatile uint32_t *)0x4000D020)) |
| #define UART1_IM_R (*((volatile uint32_t *)0x4000D038)) |
| #define UART1_LCRH_R (*((volatile uint32_t *)0x4000D02C)) |
| #define UART1_MIS_R (*((volatile uint32_t *)0x4000D040)) |
| #define UART1_PP_R (*((volatile uint32_t *)0x4000DFC0)) |
| #define UART1_RIS_R (*((volatile uint32_t *)0x4000D03C)) |
| #define UART1_RSR_R (*((volatile uint32_t *)0x4000D004)) |
| #define UART2_9BITADDR_R (*((volatile uint32_t *)0x4000E0A4)) |
| #define UART2_9BITAMASK_R (*((volatile uint32_t *)0x4000E0A8)) |
| #define UART2_CC_R (*((volatile uint32_t *)0x4000EFC8)) |
| #define UART2_CTL_R (*((volatile uint32_t *)0x4000E030)) |
| #define UART2_DMACTL_R (*((volatile uint32_t *)0x4000E048)) |
| #define UART2_DR_R (*((volatile uint32_t *)0x4000E000)) |
| #define UART2_ECR_R (*((volatile uint32_t *)0x4000E004)) |
| #define UART2_FBRD_R (*((volatile uint32_t *)0x4000E028)) |
| #define UART2_FR_R (*((volatile uint32_t *)0x4000E018)) |
| #define UART2_IBRD_R (*((volatile uint32_t *)0x4000E024)) |
| #define UART2_ICR_R (*((volatile uint32_t *)0x4000E044)) |
| #define UART2_IFLS_R (*((volatile uint32_t *)0x4000E034)) |
| #define UART2_ILPR_R (*((volatile uint32_t *)0x4000E020)) |
| #define UART2_IM_R (*((volatile uint32_t *)0x4000E038)) |
| #define UART2_LCRH_R (*((volatile uint32_t *)0x4000E02C)) |
| #define UART2_MIS_R (*((volatile uint32_t *)0x4000E040)) |
| #define UART2_PP_R (*((volatile uint32_t *)0x4000EFC0)) |
| #define UART2_RIS_R (*((volatile uint32_t *)0x4000E03C)) |
| #define UART2_RSR_R (*((volatile uint32_t *)0x4000E004)) |
| #define UART3_9BITADDR_R (*((volatile uint32_t *)0x4000F0A4)) |
| #define UART3_9BITAMASK_R (*((volatile uint32_t *)0x4000F0A8)) |
| #define UART3_CC_R (*((volatile uint32_t *)0x4000FFC8)) |
| #define UART3_CTL_R (*((volatile uint32_t *)0x4000F030)) |
| #define UART3_DMACTL_R (*((volatile uint32_t *)0x4000F048)) |
| #define UART3_DR_R (*((volatile uint32_t *)0x4000F000)) |
| #define UART3_ECR_R (*((volatile uint32_t *)0x4000F004)) |
| #define UART3_FBRD_R (*((volatile uint32_t *)0x4000F028)) |
| #define UART3_FR_R (*((volatile uint32_t *)0x4000F018)) |
| #define UART3_IBRD_R (*((volatile uint32_t *)0x4000F024)) |
| #define UART3_ICR_R (*((volatile uint32_t *)0x4000F044)) |
| #define UART3_IFLS_R (*((volatile uint32_t *)0x4000F034)) |
| #define UART3_ILPR_R (*((volatile uint32_t *)0x4000F020)) |
| #define UART3_IM_R (*((volatile uint32_t *)0x4000F038)) |
| #define UART3_LCRH_R (*((volatile uint32_t *)0x4000F02C)) |
| #define UART3_MIS_R (*((volatile uint32_t *)0x4000F040)) |
| #define UART3_PP_R (*((volatile uint32_t *)0x4000FFC0)) |
| #define UART3_RIS_R (*((volatile uint32_t *)0x4000F03C)) |
| #define UART3_RSR_R (*((volatile uint32_t *)0x4000F004)) |
| #define UART4_9BITADDR_R (*((volatile uint32_t *)0x400100A4)) |
| #define UART4_9BITAMASK_R (*((volatile uint32_t *)0x400100A8)) |
| #define UART4_CC_R (*((volatile uint32_t *)0x40010FC8)) |
| #define UART4_CTL_R (*((volatile uint32_t *)0x40010030)) |
| #define UART4_DMACTL_R (*((volatile uint32_t *)0x40010048)) |
| #define UART4_DR_R (*((volatile uint32_t *)0x40010000)) |
| #define UART4_ECR_R (*((volatile uint32_t *)0x40010004)) |
| #define UART4_FBRD_R (*((volatile uint32_t *)0x40010028)) |
| #define UART4_FR_R (*((volatile uint32_t *)0x40010018)) |
| #define UART4_IBRD_R (*((volatile uint32_t *)0x40010024)) |
| #define UART4_ICR_R (*((volatile uint32_t *)0x40010044)) |
| #define UART4_IFLS_R (*((volatile uint32_t *)0x40010034)) |
| #define UART4_ILPR_R (*((volatile uint32_t *)0x40010020)) |
| #define UART4_IM_R (*((volatile uint32_t *)0x40010038)) |
| #define UART4_LCRH_R (*((volatile uint32_t *)0x4001002C)) |
| #define UART4_MIS_R (*((volatile uint32_t *)0x40010040)) |
| #define UART4_PP_R (*((volatile uint32_t *)0x40010FC0)) |
| #define UART4_RIS_R (*((volatile uint32_t *)0x4001003C)) |
| #define UART4_RSR_R (*((volatile uint32_t *)0x40010004)) |
| #define UART5_9BITADDR_R (*((volatile uint32_t *)0x400110A4)) |
| #define UART5_9BITAMASK_R (*((volatile uint32_t *)0x400110A8)) |
| #define UART5_CC_R (*((volatile uint32_t *)0x40011FC8)) |
| #define UART5_CTL_R (*((volatile uint32_t *)0x40011030)) |
| #define UART5_DMACTL_R (*((volatile uint32_t *)0x40011048)) |
| #define UART5_DR_R (*((volatile uint32_t *)0x40011000)) |
| #define UART5_ECR_R (*((volatile uint32_t *)0x40011004)) |
| #define UART5_FBRD_R (*((volatile uint32_t *)0x40011028)) |
| #define UART5_FR_R (*((volatile uint32_t *)0x40011018)) |
| #define UART5_IBRD_R (*((volatile uint32_t *)0x40011024)) |
| #define UART5_ICR_R (*((volatile uint32_t *)0x40011044)) |
| #define UART5_IFLS_R (*((volatile uint32_t *)0x40011034)) |
| #define UART5_ILPR_R (*((volatile uint32_t *)0x40011020)) |
| #define UART5_IM_R (*((volatile uint32_t *)0x40011038)) |
| #define UART5_LCRH_R (*((volatile uint32_t *)0x4001102C)) |
| #define UART5_MIS_R (*((volatile uint32_t *)0x40011040)) |
| #define UART5_PP_R (*((volatile uint32_t *)0x40011FC0)) |
| #define UART5_RIS_R (*((volatile uint32_t *)0x4001103C)) |
| #define UART5_RSR_R (*((volatile uint32_t *)0x40011004)) |
| #define UART6_9BITADDR_R (*((volatile uint32_t *)0x400120A4)) |
| #define UART6_9BITAMASK_R (*((volatile uint32_t *)0x400120A8)) |
| #define UART6_CC_R (*((volatile uint32_t *)0x40012FC8)) |
| #define UART6_CTL_R (*((volatile uint32_t *)0x40012030)) |
| #define UART6_DMACTL_R (*((volatile uint32_t *)0x40012048)) |
| #define UART6_DR_R (*((volatile uint32_t *)0x40012000)) |
| #define UART6_ECR_R (*((volatile uint32_t *)0x40012004)) |
| #define UART6_FBRD_R (*((volatile uint32_t *)0x40012028)) |
| #define UART6_FR_R (*((volatile uint32_t *)0x40012018)) |
| #define UART6_IBRD_R (*((volatile uint32_t *)0x40012024)) |
| #define UART6_ICR_R (*((volatile uint32_t *)0x40012044)) |
| #define UART6_IFLS_R (*((volatile uint32_t *)0x40012034)) |
| #define UART6_ILPR_R (*((volatile uint32_t *)0x40012020)) |
| #define UART6_IM_R (*((volatile uint32_t *)0x40012038)) |
| #define UART6_LCRH_R (*((volatile uint32_t *)0x4001202C)) |
| #define UART6_MIS_R (*((volatile uint32_t *)0x40012040)) |
| #define UART6_PP_R (*((volatile uint32_t *)0x40012FC0)) |
| #define UART6_RIS_R (*((volatile uint32_t *)0x4001203C)) |
| #define UART6_RSR_R (*((volatile uint32_t *)0x40012004)) |
| #define UART7_9BITADDR_R (*((volatile uint32_t *)0x400130A4)) |
| #define UART7_9BITAMASK_R (*((volatile uint32_t *)0x400130A8)) |
| #define UART7_CC_R (*((volatile uint32_t *)0x40013FC8)) |
| #define UART7_CTL_R (*((volatile uint32_t *)0x40013030)) |
| #define UART7_DMACTL_R (*((volatile uint32_t *)0x40013048)) |
| #define UART7_DR_R (*((volatile uint32_t *)0x40013000)) |
| #define UART7_ECR_R (*((volatile uint32_t *)0x40013004)) |
| #define UART7_FBRD_R (*((volatile uint32_t *)0x40013028)) |
| #define UART7_FR_R (*((volatile uint32_t *)0x40013018)) |
| #define UART7_IBRD_R (*((volatile uint32_t *)0x40013024)) |
| #define UART7_ICR_R (*((volatile uint32_t *)0x40013044)) |
| #define UART7_IFLS_R (*((volatile uint32_t *)0x40013034)) |
| #define UART7_ILPR_R (*((volatile uint32_t *)0x40013020)) |
| #define UART7_IM_R (*((volatile uint32_t *)0x40013038)) |
| #define UART7_LCRH_R (*((volatile uint32_t *)0x4001302C)) |
| #define UART7_MIS_R (*((volatile uint32_t *)0x40013040)) |
| #define UART7_PP_R (*((volatile uint32_t *)0x40013FC0)) |
| #define UART7_RIS_R (*((volatile uint32_t *)0x4001303C)) |
| #define UART7_RSR_R (*((volatile uint32_t *)0x40013004)) |
| #define UART_9BITADDR_9BITEN 0x00008000 |
| #define UART_9BITADDR_ADDR_M 0x000000FF |
| #define UART_9BITADDR_ADDR_S 0 |
| #define UART_9BITAMASK_MASK_M 0x000000FF |
| #define UART_9BITAMASK_MASK_S 0 |
| #define UART_CC_CS_M 0x0000000F |
| #define UART_CC_CS_PIOSC 0x00000005 |
| #define UART_CC_CS_SYSCLK 0x00000000 |
| #define UART_CTL_CTSEN 0x00008000 |
| #define UART_CTL_DTR 0x00000400 |
| #define UART_CTL_EOT 0x00000010 |
| #define UART_CTL_HSE 0x00000020 |
| #define UART_CTL_LBE 0x00000080 |
| #define UART_CTL_RTS 0x00000800 |
| #define UART_CTL_RTSEN 0x00004000 |
| #define UART_CTL_RXE 0x00000200 |
| #define UART_CTL_SIREN 0x00000002 |
| #define UART_CTL_SIRLP 0x00000004 |
| #define UART_CTL_SMART 0x00000008 |
| #define UART_CTL_TXE 0x00000100 |
| #define UART_CTL_UARTEN 0x00000001 |
| #define UART_DMACTL_DMAERR 0x00000004 |
| #define UART_DMACTL_RXDMAE 0x00000001 |
| #define UART_DMACTL_TXDMAE 0x00000002 |
| #define UART_DR_BE 0x00000400 |
| #define UART_DR_DATA_M 0x000000FF |
| #define UART_DR_DATA_S 0 |
| #define UART_DR_FE 0x00000100 |
| #define UART_DR_OE 0x00000800 |
| #define UART_DR_PE 0x00000200 |
| #define UART_ECR_DATA_M 0x000000FF |
| #define UART_ECR_DATA_S 0 |
| #define UART_FBRD_DIVFRAC_M 0x0000003F |
| #define UART_FBRD_DIVFRAC_S 0 |
| #define UART_FR_BUSY 0x00000008 |
| #define UART_FR_CTS 0x00000001 |
| #define UART_FR_DCD 0x00000004 |
| #define UART_FR_DSR 0x00000002 |
| #define UART_FR_RI 0x00000100 |
| #define UART_FR_RXFE 0x00000010 |
| #define UART_FR_RXFF 0x00000040 |
| #define UART_FR_TXFE 0x00000080 |
| #define UART_FR_TXFF 0x00000020 |
| #define UART_IBRD_DIVINT_M 0x0000FFFF |
| #define UART_IBRD_DIVINT_S 0 |
| #define UART_ICR_9BITIC 0x00001000 |
| #define UART_ICR_BEIC 0x00000200 |
| #define UART_ICR_CTSMIC 0x00000002 |
| #define UART_ICR_DCDMIC 0x00000004 |
| #define UART_ICR_DSRMIC 0x00000008 |
| #define UART_ICR_FEIC 0x00000080 |
| #define UART_ICR_OEIC 0x00000400 |
| #define UART_ICR_PEIC 0x00000100 |
| #define UART_ICR_RIMIC 0x00000001 |
| #define UART_ICR_RTIC 0x00000040 |
| #define UART_ICR_RXIC 0x00000010 |
| #define UART_ICR_TXIC 0x00000020 |
| #define UART_IFLS_RX1_8 0x00000000 |
| #define UART_IFLS_RX2_8 0x00000008 |
| #define UART_IFLS_RX4_8 0x00000010 |
| #define UART_IFLS_RX6_8 0x00000018 |
| #define UART_IFLS_RX7_8 0x00000020 |
| #define UART_IFLS_RX_M 0x00000038 |
| #define UART_IFLS_TX1_8 0x00000000 |
| #define UART_IFLS_TX2_8 0x00000001 |
| #define UART_IFLS_TX4_8 0x00000002 |
| #define UART_IFLS_TX6_8 0x00000003 |
| #define UART_IFLS_TX7_8 0x00000004 |
| #define UART_IFLS_TX_M 0x00000007 |
| #define UART_ILPR_ILPDVSR_M 0x000000FF |
| #define UART_ILPR_ILPDVSR_S 0 |
| #define UART_IM_9BITIM 0x00001000 |
| #define UART_IM_BEIM 0x00000200 |
| #define UART_IM_CTSMIM 0x00000002 |
| #define UART_IM_DCDMIM 0x00000004 |
| #define UART_IM_DSRMIM 0x00000008 |
| #define UART_IM_FEIM 0x00000080 |
| #define UART_IM_OEIM 0x00000400 |
| #define UART_IM_PEIM 0x00000100 |
| #define UART_IM_RIMIM 0x00000001 |
| #define UART_IM_RTIM 0x00000040 |
| #define UART_IM_RXIM 0x00000010 |
| #define UART_IM_TXIM 0x00000020 |
| #define UART_LCRH_BRK 0x00000001 |
| #define UART_LCRH_EPS 0x00000004 |
| #define UART_LCRH_FEN 0x00000010 |
| #define UART_LCRH_PEN 0x00000002 |
| #define UART_LCRH_SPS 0x00000080 |
| #define UART_LCRH_STP2 0x00000008 |
| #define UART_LCRH_WLEN_5 0x00000000 |
| #define UART_LCRH_WLEN_6 0x00000020 |
| #define UART_LCRH_WLEN_7 0x00000040 |
| #define UART_LCRH_WLEN_8 0x00000060 |
| #define UART_LCRH_WLEN_M 0x00000060 |
| #define UART_MIS_9BITMIS 0x00001000 |
| #define UART_MIS_BEMIS 0x00000200 |
| #define UART_MIS_CTSMIS 0x00000002 |
| #define UART_MIS_DCDMIS 0x00000004 |
| #define UART_MIS_DSRMIS 0x00000008 |
| #define UART_MIS_FEMIS 0x00000080 |
| #define UART_MIS_OEMIS 0x00000400 |
| #define UART_MIS_PEMIS 0x00000100 |
| #define UART_MIS_RIMIS 0x00000001 |
| #define UART_MIS_RTMIS 0x00000040 |
| #define UART_MIS_RXMIS 0x00000010 |
| #define UART_MIS_TXMIS 0x00000020 |
| #define UART_PP_NB 0x00000002 |
| #define UART_PP_SC 0x00000001 |
| #define UART_RIS_9BITRIS 0x00001000 |
| #define UART_RIS_BERIS 0x00000200 |
| #define UART_RIS_CTSRIS 0x00000002 |
| #define UART_RIS_DCDRIS 0x00000004 |
| #define UART_RIS_DSRRIS 0x00000008 |
| #define UART_RIS_FERIS 0x00000080 |
| #define UART_RIS_OERIS 0x00000400 |
| #define UART_RIS_PERIS 0x00000100 |
| #define UART_RIS_RIRIS 0x00000001 |
| #define UART_RIS_RTRIS 0x00000040 |
| #define UART_RIS_RXRIS 0x00000010 |
| #define UART_RIS_TXRIS 0x00000020 |
| #define UART_RSR_BE 0x00000004 |
| #define UART_RSR_FE 0x00000001 |
| #define UART_RSR_OE 0x00000008 |
| #define UART_RSR_PE 0x00000002 |
| #define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF |
| #define UDMA_ALTBASE_ADDR_S 0 |
| #define UDMA_ALTBASE_R (*((volatile uint32_t *)0x400FF00C)) |
| #define UDMA_ALTCLR_CLR_M 0xFFFFFFFF |
| #define UDMA_ALTCLR_R (*((volatile uint32_t *)0x400FF034)) |
| #define UDMA_ALTSET_R (*((volatile uint32_t *)0x400FF030)) |
| #define UDMA_ALTSET_SET_M 0xFFFFFFFF |
| #define UDMA_CFG_MASTEN 0x00000001 |
| #define UDMA_CFG_R (*((volatile uint32_t *)0x400FF004)) |
| #define UDMA_CHASGN_M 0xFFFFFFFF |
| #define UDMA_CHASGN_PRIMARY 0x00000000 |
| #define UDMA_CHASGN_R (*((volatile uint32_t *)0x400FF500)) |
| #define UDMA_CHASGN_SECONDARY 0x00000001 |
| #define UDMA_CHCTL 0x00000008 |
| #define UDMA_CHCTL_ARBSIZE_1 0x00000000 |
| #define UDMA_CHCTL_ARBSIZE_1024 0x00028000 |
| #define UDMA_CHCTL_ARBSIZE_128 0x0001C000 |
| #define UDMA_CHCTL_ARBSIZE_16 0x00010000 |
| #define UDMA_CHCTL_ARBSIZE_2 0x00004000 |
| #define UDMA_CHCTL_ARBSIZE_256 0x00020000 |
| #define UDMA_CHCTL_ARBSIZE_32 0x00014000 |
| #define UDMA_CHCTL_ARBSIZE_4 0x00008000 |
| #define UDMA_CHCTL_ARBSIZE_512 0x00024000 |
| #define UDMA_CHCTL_ARBSIZE_64 0x00018000 |
| #define UDMA_CHCTL_ARBSIZE_8 0x0000C000 |
| #define UDMA_CHCTL_ARBSIZE_M 0x0003C000 |
| #define UDMA_CHCTL_DSTINC_16 0x40000000 |
| #define UDMA_CHCTL_DSTINC_32 0x80000000 |
| #define UDMA_CHCTL_DSTINC_8 0x00000000 |
| #define UDMA_CHCTL_DSTINC_M 0xC0000000 |
| #define UDMA_CHCTL_DSTINC_NONE 0xC0000000 |
| #define UDMA_CHCTL_DSTSIZE_16 0x10000000 |
| #define UDMA_CHCTL_DSTSIZE_32 0x20000000 |
| #define UDMA_CHCTL_DSTSIZE_8 0x00000000 |
| #define UDMA_CHCTL_DSTSIZE_M 0x30000000 |
| #define UDMA_CHCTL_NXTUSEBURST 0x00000008 |
| #define UDMA_CHCTL_SRCINC_16 0x04000000 |
| #define UDMA_CHCTL_SRCINC_32 0x08000000 |
| #define UDMA_CHCTL_SRCINC_8 0x00000000 |
| #define UDMA_CHCTL_SRCINC_M 0x0C000000 |
| #define UDMA_CHCTL_SRCINC_NONE 0x0C000000 |
| #define UDMA_CHCTL_SRCSIZE_16 0x01000000 |
| #define UDMA_CHCTL_SRCSIZE_32 0x02000000 |
| #define UDMA_CHCTL_SRCSIZE_8 0x00000000 |
| #define UDMA_CHCTL_SRCSIZE_M 0x03000000 |
| #define UDMA_CHCTL_XFERMODE_AUTO 0x00000002 |
| #define UDMA_CHCTL_XFERMODE_BASIC 0x00000001 |
| #define UDMA_CHCTL_XFERMODE_M 0x00000007 |
| #define UDMA_CHCTL_XFERMODE_MEM_SG 0x00000004 |
| #define UDMA_CHCTL_XFERMODE_MEM_SGA 0x00000005 |
| #define UDMA_CHCTL_XFERMODE_PER_SG 0x00000006 |
| #define UDMA_CHCTL_XFERMODE_PER_SGA 0x00000007 |
| #define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 |
| #define UDMA_CHCTL_XFERMODE_STOP 0x00000000 |
| #define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 |
| #define UDMA_CHCTL_XFERSIZE_S 4 |
| #define UDMA_CHIS_M 0xFFFFFFFF |
| #define UDMA_CHIS_R (*((volatile uint32_t *)0x400FF504)) |
| #define UDMA_CHMAP0_CH0SEL_M 0x0000000F |
| #define UDMA_CHMAP0_CH0SEL_S 0 |
| #define UDMA_CHMAP0_CH1SEL_M 0x000000F0 |
| #define UDMA_CHMAP0_CH1SEL_S 4 |
| #define UDMA_CHMAP0_CH2SEL_M 0x00000F00 |
| #define UDMA_CHMAP0_CH2SEL_S 8 |
| #define UDMA_CHMAP0_CH3SEL_M 0x0000F000 |
| #define UDMA_CHMAP0_CH3SEL_S 12 |
| #define UDMA_CHMAP0_CH4SEL_M 0x000F0000 |
| #define UDMA_CHMAP0_CH4SEL_S 16 |
| #define UDMA_CHMAP0_CH5SEL_M 0x00F00000 |
| #define UDMA_CHMAP0_CH5SEL_S 20 |
| #define UDMA_CHMAP0_CH6SEL_M 0x0F000000 |
| #define UDMA_CHMAP0_CH6SEL_S 24 |
| #define UDMA_CHMAP0_CH7SEL_M 0xF0000000 |
| #define UDMA_CHMAP0_CH7SEL_S 28 |
| #define UDMA_CHMAP0_R (*((volatile uint32_t *)0x400FF510)) |
| #define UDMA_CHMAP1_CH10SEL_M 0x00000F00 |
| #define UDMA_CHMAP1_CH10SEL_S 8 |
| #define UDMA_CHMAP1_CH11SEL_M 0x0000F000 |
| #define UDMA_CHMAP1_CH11SEL_S 12 |
| #define UDMA_CHMAP1_CH12SEL_M 0x000F0000 |
| #define UDMA_CHMAP1_CH12SEL_S 16 |
| #define UDMA_CHMAP1_CH13SEL_M 0x00F00000 |
| #define UDMA_CHMAP1_CH13SEL_S 20 |
| #define UDMA_CHMAP1_CH14SEL_M 0x0F000000 |
| #define UDMA_CHMAP1_CH14SEL_S 24 |
| #define UDMA_CHMAP1_CH15SEL_M 0xF0000000 |
| #define UDMA_CHMAP1_CH15SEL_S 28 |
| #define UDMA_CHMAP1_CH8SEL_M 0x0000000F |
| #define UDMA_CHMAP1_CH8SEL_S 0 |
| #define UDMA_CHMAP1_CH9SEL_M 0x000000F0 |
| #define UDMA_CHMAP1_CH9SEL_S 4 |
| #define UDMA_CHMAP1_R (*((volatile uint32_t *)0x400FF514)) |
| #define UDMA_CHMAP2_CH16SEL_M 0x0000000F |
| #define UDMA_CHMAP2_CH16SEL_S 0 |
| #define UDMA_CHMAP2_CH17SEL_M 0x000000F0 |
| #define UDMA_CHMAP2_CH17SEL_S 4 |
| #define UDMA_CHMAP2_CH18SEL_M 0x00000F00 |
| #define UDMA_CHMAP2_CH18SEL_S 8 |
| #define UDMA_CHMAP2_CH19SEL_M 0x0000F000 |
| #define UDMA_CHMAP2_CH19SEL_S 12 |
| #define UDMA_CHMAP2_CH20SEL_M 0x000F0000 |
| #define UDMA_CHMAP2_CH20SEL_S 16 |
| #define UDMA_CHMAP2_CH21SEL_M 0x00F00000 |
| #define UDMA_CHMAP2_CH21SEL_S 20 |
| #define UDMA_CHMAP2_CH22SEL_M 0x0F000000 |
| #define UDMA_CHMAP2_CH22SEL_S 24 |
| #define UDMA_CHMAP2_CH23SEL_M 0xF0000000 |
| #define UDMA_CHMAP2_CH23SEL_S 28 |
| #define UDMA_CHMAP2_R (*((volatile uint32_t *)0x400FF518)) |
| #define UDMA_CHMAP3_CH24SEL_M 0x0000000F |
| #define UDMA_CHMAP3_CH24SEL_S 0 |
| #define UDMA_CHMAP3_CH25SEL_M 0x000000F0 |
| #define UDMA_CHMAP3_CH25SEL_S 4 |
| #define UDMA_CHMAP3_CH26SEL_M 0x00000F00 |
| #define UDMA_CHMAP3_CH26SEL_S 8 |
| #define UDMA_CHMAP3_CH27SEL_M 0x0000F000 |
| #define UDMA_CHMAP3_CH27SEL_S 12 |
| #define UDMA_CHMAP3_CH28SEL_M 0x000F0000 |
| #define UDMA_CHMAP3_CH28SEL_S 16 |
| #define UDMA_CHMAP3_CH29SEL_M 0x00F00000 |
| #define UDMA_CHMAP3_CH29SEL_S 20 |
| #define UDMA_CHMAP3_CH30SEL_M 0x0F000000 |
| #define UDMA_CHMAP3_CH30SEL_S 24 |
| #define UDMA_CHMAP3_CH31SEL_M 0xF0000000 |
| #define UDMA_CHMAP3_CH31SEL_S 28 |
| #define UDMA_CHMAP3_R (*((volatile uint32_t *)0x400FF51C)) |
| #define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 |
| #define UDMA_CTLBASE_ADDR_S 10 |
| #define UDMA_CTLBASE_R (*((volatile uint32_t *)0x400FF008)) |
| #define UDMA_DSTENDP 0x00000004 |
| #define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF |
| #define UDMA_DSTENDP_ADDR_S 0 |
| #define UDMA_ENACLR_CLR_M 0xFFFFFFFF |
| #define UDMA_ENACLR_R (*((volatile uint32_t *)0x400FF02C)) |
| #define UDMA_ENASET_R (*((volatile uint32_t *)0x400FF028)) |
| #define UDMA_ENASET_SET_M 0xFFFFFFFF |
| #define UDMA_ERRCLR_ERRCLR 0x00000001 |
| #define UDMA_ERRCLR_R (*((volatile uint32_t *)0x400FF04C)) |
| #define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF |
| #define UDMA_PRIOCLR_R (*((volatile uint32_t *)0x400FF03C)) |
| #define UDMA_PRIOSET_R (*((volatile uint32_t *)0x400FF038)) |
| #define UDMA_PRIOSET_SET_M 0xFFFFFFFF |
| #define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF |
| #define UDMA_REQMASKCLR_R (*((volatile uint32_t *)0x400FF024)) |
| #define UDMA_REQMASKSET_R (*((volatile uint32_t *)0x400FF020)) |
| #define UDMA_REQMASKSET_SET_M 0xFFFFFFFF |
| #define UDMA_SRCENDP 0x00000000 |
| #define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF |
| #define UDMA_SRCENDP_ADDR_S 0 |
| #define UDMA_STAT_DMACHANS_M 0x001F0000 |
| #define UDMA_STAT_DMACHANS_S 16 |
| #define UDMA_STAT_MASTEN 0x00000001 |
| #define UDMA_STAT_R (*((volatile uint32_t *)0x400FF000)) |
| #define UDMA_STAT_STATE_DONE 0x00000090 |
| #define UDMA_STAT_STATE_IDLE 0x00000000 |
| #define UDMA_STAT_STATE_M 0x000000F0 |
| #define UDMA_STAT_STATE_RD_CTRL 0x00000010 |
| #define UDMA_STAT_STATE_RD_DSTENDP 0x00000030 |
| #define UDMA_STAT_STATE_RD_SRCDAT 0x00000040 |
| #define UDMA_STAT_STATE_RD_SRCENDP 0x00000020 |
| #define UDMA_STAT_STATE_STALL 0x00000080 |
| #define UDMA_STAT_STATE_UNDEF 0x000000A0 |
| #define UDMA_STAT_STATE_WAIT 0x00000060 |
| #define UDMA_STAT_STATE_WR_CTRL 0x00000070 |
| #define UDMA_STAT_STATE_WR_DSTDAT 0x00000050 |
| #define UDMA_SWREQ_M 0xFFFFFFFF |
| #define UDMA_SWREQ_R (*((volatile uint32_t *)0x400FF014)) |
| #define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF |
| #define UDMA_USEBURSTCLR_R (*((volatile uint32_t *)0x400FF01C)) |
| #define UDMA_USEBURSTSET_R (*((volatile uint32_t *)0x400FF018)) |
| #define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF |
| #define UDMA_WAITSTAT_R (*((volatile uint32_t *)0x400FF010)) |
| #define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF |
| #define USB0_CONTIM_R (*((volatile uint8_t *)0x4005007A)) |
| #define USB0_COUNT0_R (*((volatile uint8_t *)0x40050108)) |
| #define USB0_CSRH0_R (*((volatile uint8_t *)0x40050103)) |
| #define USB0_CSRL0_R (*((volatile uint8_t *)0x40050102)) |
| #define USB0_DEVCTL_R (*((volatile uint8_t *)0x40050060)) |
| #define USB0_DMASEL_R (*((volatile uint32_t *)0x40050450)) |
| #define USB0_DRIM_R (*((volatile uint32_t *)0x40050414)) |
| #define USB0_DRISC_R (*((volatile uint32_t *)0x40050418)) |
| #define USB0_DRRIS_R (*((volatile uint32_t *)0x40050410)) |
| #define USB0_EPC_R (*((volatile uint32_t *)0x40050400)) |
| #define USB0_EPCIM_R (*((volatile uint32_t *)0x40050408)) |
| #define USB0_EPCISC_R (*((volatile uint32_t *)0x4005040C)) |
| #define USB0_EPCRIS_R (*((volatile uint32_t *)0x40050404)) |
| #define USB0_EPIDX_R (*((volatile uint8_t *)0x4005000E)) |
| #define USB0_FADDR_R (*((volatile uint8_t *)0x40050000)) |
| #define USB0_FIFO0_R (*((volatile uint32_t *)0x40050020)) |
| #define USB0_FIFO1_R (*((volatile uint32_t *)0x40050024)) |
| #define USB0_FIFO2_R (*((volatile uint32_t *)0x40050028)) |
| #define USB0_FIFO3_R (*((volatile uint32_t *)0x4005002C)) |
| #define USB0_FIFO4_R (*((volatile uint32_t *)0x40050030)) |
| #define USB0_FIFO5_R (*((volatile uint32_t *)0x40050034)) |
| #define USB0_FIFO6_R (*((volatile uint32_t *)0x40050038)) |
| #define USB0_FIFO7_R (*((volatile uint32_t *)0x4005003C)) |
| #define USB0_FRAME_R (*((volatile uint16_t *)0x4005000C)) |
| #define USB0_FSEOF_R (*((volatile uint8_t *)0x4005007D)) |
| #define USB0_GPCS_R (*((volatile uint32_t *)0x4005041C)) |
| #define USB0_IDVIM_R (*((volatile uint32_t *)0x40050448)) |
| #define USB0_IDVISC_R (*((volatile uint32_t *)0x4005044C)) |
| #define USB0_IDVRIS_R (*((volatile uint32_t *)0x40050444)) |
| #define USB0_IE_R (*((volatile uint8_t *)0x4005000B)) |
| #define USB0_IS_R (*((volatile uint8_t *)0x4005000A)) |
| #define USB0_LSEOF_R (*((volatile uint8_t *)0x4005007E)) |
| #define USB0_NAKLMT_R (*((volatile uint8_t *)0x4005010B)) |
| #define USB0_POWER_R (*((volatile uint8_t *)0x40050001)) |
| #define USB0_PP_R (*((volatile uint32_t *)0x40050FC0)) |
| #define USB0_RQPKTCOUNT1_R (*((volatile uint16_t *)0x40050304)) |
| #define USB0_RQPKTCOUNT2_R (*((volatile uint16_t *)0x40050308)) |
| #define USB0_RQPKTCOUNT3_R (*((volatile uint16_t *)0x4005030C)) |
| #define USB0_RQPKTCOUNT4_R (*((volatile uint16_t *)0x40050310)) |
| #define USB0_RQPKTCOUNT5_R (*((volatile uint16_t *)0x40050314)) |
| #define USB0_RQPKTCOUNT6_R (*((volatile uint16_t *)0x40050318)) |
| #define USB0_RQPKTCOUNT7_R (*((volatile uint16_t *)0x4005031C)) |
| #define USB0_RXCOUNT1_R (*((volatile uint16_t *)0x40050118)) |
| #define USB0_RXCOUNT2_R (*((volatile uint16_t *)0x40050128)) |
| #define USB0_RXCOUNT3_R (*((volatile uint16_t *)0x40050138)) |
| #define USB0_RXCOUNT4_R (*((volatile uint16_t *)0x40050148)) |
| #define USB0_RXCOUNT5_R (*((volatile uint16_t *)0x40050158)) |
| #define USB0_RXCOUNT6_R (*((volatile uint16_t *)0x40050168)) |
| #define USB0_RXCOUNT7_R (*((volatile uint16_t *)0x40050178)) |
| #define USB0_RXCSRH1_R (*((volatile uint8_t *)0x40050117)) |
| #define USB0_RXCSRH2_R (*((volatile uint8_t *)0x40050127)) |
| #define USB0_RXCSRH3_R (*((volatile uint8_t *)0x40050137)) |
| #define USB0_RXCSRH4_R (*((volatile uint8_t *)0x40050147)) |
| #define USB0_RXCSRH5_R (*((volatile uint8_t *)0x40050157)) |
| #define USB0_RXCSRH6_R (*((volatile uint8_t *)0x40050167)) |
| #define USB0_RXCSRH7_R (*((volatile uint8_t *)0x40050177)) |
| #define USB0_RXCSRL1_R (*((volatile uint8_t *)0x40050116)) |
| #define USB0_RXCSRL2_R (*((volatile uint8_t *)0x40050126)) |
| #define USB0_RXCSRL3_R (*((volatile uint8_t *)0x40050136)) |
| #define USB0_RXCSRL4_R (*((volatile uint8_t *)0x40050146)) |
| #define USB0_RXCSRL5_R (*((volatile uint8_t *)0x40050156)) |
| #define USB0_RXCSRL6_R (*((volatile uint8_t *)0x40050166)) |
| #define USB0_RXCSRL7_R (*((volatile uint8_t *)0x40050176)) |
| #define USB0_RXDPKTBUFDIS_R (*((volatile uint16_t *)0x40050340)) |
| #define USB0_RXFIFOADD_R (*((volatile uint16_t *)0x40050066)) |
| #define USB0_RXFIFOSZ_R (*((volatile uint8_t *)0x40050063)) |
| #define USB0_RXFUNCADDR1_R (*((volatile uint8_t *)0x4005008C)) |
| #define USB0_RXFUNCADDR2_R (*((volatile uint8_t *)0x40050094)) |
| #define USB0_RXFUNCADDR3_R (*((volatile uint8_t *)0x4005009C)) |
| #define USB0_RXFUNCADDR4_R (*((volatile uint8_t *)0x400500A4)) |
| #define USB0_RXFUNCADDR5_R (*((volatile uint8_t *)0x400500AC)) |
| #define USB0_RXFUNCADDR6_R (*((volatile uint8_t *)0x400500B4)) |
| #define USB0_RXFUNCADDR7_R (*((volatile uint8_t *)0x400500BC)) |
| #define USB0_RXHUBADDR1_R (*((volatile uint8_t *)0x4005008E)) |
| #define USB0_RXHUBADDR2_R (*((volatile uint8_t *)0x40050096)) |
| #define USB0_RXHUBADDR3_R (*((volatile uint8_t *)0x4005009E)) |
| #define USB0_RXHUBADDR4_R (*((volatile uint8_t *)0x400500A6)) |
| #define USB0_RXHUBADDR5_R (*((volatile uint8_t *)0x400500AE)) |
| #define USB0_RXHUBADDR6_R (*((volatile uint8_t *)0x400500B6)) |
| #define USB0_RXHUBADDR7_R (*((volatile uint8_t *)0x400500BE)) |
| #define USB0_RXHUBPORT1_R (*((volatile uint8_t *)0x4005008F)) |
| #define USB0_RXHUBPORT2_R (*((volatile uint8_t *)0x40050097)) |
| #define USB0_RXHUBPORT3_R (*((volatile uint8_t *)0x4005009F)) |
| #define USB0_RXHUBPORT4_R (*((volatile uint8_t *)0x400500A7)) |
| #define USB0_RXHUBPORT5_R (*((volatile uint8_t *)0x400500AF)) |
| #define USB0_RXHUBPORT6_R (*((volatile uint8_t *)0x400500B7)) |
| #define USB0_RXHUBPORT7_R (*((volatile uint8_t *)0x400500BF)) |
| #define USB0_RXIE_R (*((volatile uint16_t *)0x40050008)) |
| #define USB0_RXINTERVAL1_R (*((volatile uint8_t *)0x4005011D)) |
| #define USB0_RXINTERVAL2_R (*((volatile uint8_t *)0x4005012D)) |
| #define USB0_RXINTERVAL3_R (*((volatile uint8_t *)0x4005013D)) |
| #define USB0_RXINTERVAL4_R (*((volatile uint8_t *)0x4005014D)) |
| #define USB0_RXINTERVAL5_R (*((volatile uint8_t *)0x4005015D)) |
| #define USB0_RXINTERVAL6_R (*((volatile uint8_t *)0x4005016D)) |
| #define USB0_RXINTERVAL7_R (*((volatile uint8_t *)0x4005017D)) |
| #define USB0_RXIS_R (*((volatile uint16_t *)0x40050004)) |
| #define USB0_RXMAXP1_R (*((volatile uint16_t *)0x40050114)) |
| #define USB0_RXMAXP2_R (*((volatile uint16_t *)0x40050124)) |
| #define USB0_RXMAXP3_R (*((volatile uint16_t *)0x40050134)) |
| #define USB0_RXMAXP4_R (*((volatile uint16_t *)0x40050144)) |
| #define USB0_RXMAXP5_R (*((volatile uint16_t *)0x40050154)) |
| #define USB0_RXMAXP6_R (*((volatile uint16_t *)0x40050164)) |
| #define USB0_RXMAXP7_R (*((volatile uint16_t *)0x40050174)) |
| #define USB0_RXTYPE1_R (*((volatile uint8_t *)0x4005011C)) |
| #define USB0_RXTYPE2_R (*((volatile uint8_t *)0x4005012C)) |
| #define USB0_RXTYPE3_R (*((volatile uint8_t *)0x4005013C)) |
| #define USB0_RXTYPE4_R (*((volatile uint8_t *)0x4005014C)) |
| #define USB0_RXTYPE5_R (*((volatile uint8_t *)0x4005015C)) |
| #define USB0_RXTYPE6_R (*((volatile uint8_t *)0x4005016C)) |
| #define USB0_RXTYPE7_R (*((volatile uint8_t *)0x4005017C)) |
| #define USB0_TEST_R (*((volatile uint8_t *)0x4005000F)) |
| #define USB0_TXCSRH1_R (*((volatile uint8_t *)0x40050113)) |
| #define USB0_TXCSRH2_R (*((volatile uint8_t *)0x40050123)) |
| #define USB0_TXCSRH3_R (*((volatile uint8_t *)0x40050133)) |
| #define USB0_TXCSRH4_R (*((volatile uint8_t *)0x40050143)) |
| #define USB0_TXCSRH5_R (*((volatile uint8_t *)0x40050153)) |
| #define USB0_TXCSRH6_R (*((volatile uint8_t *)0x40050163)) |
| #define USB0_TXCSRH7_R (*((volatile uint8_t *)0x40050173)) |
| #define USB0_TXCSRL1_R (*((volatile uint8_t *)0x40050112)) |
| #define USB0_TXCSRL2_R (*((volatile uint8_t *)0x40050122)) |
| #define USB0_TXCSRL3_R (*((volatile uint8_t *)0x40050132)) |
| #define USB0_TXCSRL4_R (*((volatile uint8_t *)0x40050142)) |
| #define USB0_TXCSRL5_R (*((volatile uint8_t *)0x40050152)) |
| #define USB0_TXCSRL6_R (*((volatile uint8_t *)0x40050162)) |
| #define USB0_TXCSRL7_R (*((volatile uint8_t *)0x40050172)) |
| #define USB0_TXDPKTBUFDIS_R (*((volatile uint16_t *)0x40050342)) |
| #define USB0_TXFIFOADD_R (*((volatile uint16_t *)0x40050064)) |
| #define USB0_TXFIFOSZ_R (*((volatile uint8_t *)0x40050062)) |
| #define USB0_TXFUNCADDR0_R (*((volatile uint8_t *)0x40050080)) |
| #define USB0_TXFUNCADDR1_R (*((volatile uint8_t *)0x40050088)) |
| #define USB0_TXFUNCADDR2_R (*((volatile uint8_t *)0x40050090)) |
| #define USB0_TXFUNCADDR3_R (*((volatile uint8_t *)0x40050098)) |
| #define USB0_TXFUNCADDR4_R (*((volatile uint8_t *)0x400500A0)) |
| #define USB0_TXFUNCADDR5_R (*((volatile uint8_t *)0x400500A8)) |
| #define USB0_TXFUNCADDR6_R (*((volatile uint8_t *)0x400500B0)) |
| #define USB0_TXFUNCADDR7_R (*((volatile uint8_t *)0x400500B8)) |
| #define USB0_TXHUBADDR0_R (*((volatile uint8_t *)0x40050082)) |
| #define USB0_TXHUBADDR1_R (*((volatile uint8_t *)0x4005008A)) |
| #define USB0_TXHUBADDR2_R (*((volatile uint8_t *)0x40050092)) |
| #define USB0_TXHUBADDR3_R (*((volatile uint8_t *)0x4005009A)) |
| #define USB0_TXHUBADDR4_R (*((volatile uint8_t *)0x400500A2)) |
| #define USB0_TXHUBADDR5_R (*((volatile uint8_t *)0x400500AA)) |
| #define USB0_TXHUBADDR6_R (*((volatile uint8_t *)0x400500B2)) |
| #define USB0_TXHUBADDR7_R (*((volatile uint8_t *)0x400500BA)) |
| #define USB0_TXHUBPORT0_R (*((volatile uint8_t *)0x40050083)) |
| #define USB0_TXHUBPORT1_R (*((volatile uint8_t *)0x4005008B)) |
| #define USB0_TXHUBPORT2_R (*((volatile uint8_t *)0x40050093)) |
| #define USB0_TXHUBPORT3_R (*((volatile uint8_t *)0x4005009B)) |
| #define USB0_TXHUBPORT4_R (*((volatile uint8_t *)0x400500A3)) |
| #define USB0_TXHUBPORT5_R (*((volatile uint8_t *)0x400500AB)) |
| #define USB0_TXHUBPORT6_R (*((volatile uint8_t *)0x400500B3)) |
| #define USB0_TXHUBPORT7_R (*((volatile uint8_t *)0x400500BB)) |
| #define USB0_TXIE_R (*((volatile uint16_t *)0x40050006)) |
| #define USB0_TXINTERVAL1_R (*((volatile uint8_t *)0x4005011B)) |
| #define USB0_TXINTERVAL2_R (*((volatile uint8_t *)0x4005012B)) |
| #define USB0_TXINTERVAL3_R (*((volatile uint8_t *)0x4005013B)) |
| #define USB0_TXINTERVAL4_R (*((volatile uint8_t *)0x4005014B)) |
| #define USB0_TXINTERVAL5_R (*((volatile uint8_t *)0x4005015B)) |
| #define USB0_TXINTERVAL6_R (*((volatile uint8_t *)0x4005016B)) |
| #define USB0_TXINTERVAL7_R (*((volatile uint8_t *)0x4005017B)) |
| #define USB0_TXIS_R (*((volatile uint16_t *)0x40050002)) |
| #define USB0_TXMAXP1_R (*((volatile uint16_t *)0x40050110)) |
| #define USB0_TXMAXP2_R (*((volatile uint16_t *)0x40050120)) |
| #define USB0_TXMAXP3_R (*((volatile uint16_t *)0x40050130)) |
| #define USB0_TXMAXP4_R (*((volatile uint16_t *)0x40050140)) |
| #define USB0_TXMAXP5_R (*((volatile uint16_t *)0x40050150)) |
| #define USB0_TXMAXP6_R (*((volatile uint16_t *)0x40050160)) |
| #define USB0_TXMAXP7_R (*((volatile uint16_t *)0x40050170)) |
| #define USB0_TXTYPE1_R (*((volatile uint8_t *)0x4005011A)) |
| #define USB0_TXTYPE2_R (*((volatile uint8_t *)0x4005012A)) |
| #define USB0_TXTYPE3_R (*((volatile uint8_t *)0x4005013A)) |
| #define USB0_TXTYPE4_R (*((volatile uint8_t *)0x4005014A)) |
| #define USB0_TXTYPE5_R (*((volatile uint8_t *)0x4005015A)) |
| #define USB0_TXTYPE6_R (*((volatile uint8_t *)0x4005016A)) |
| #define USB0_TXTYPE7_R (*((volatile uint8_t *)0x4005017A)) |
| #define USB0_TYPE0_R (*((volatile uint8_t *)0x4005010A)) |
| #define USB0_VDC_R (*((volatile uint32_t *)0x40050430)) |
| #define USB0_VDCIM_R (*((volatile uint32_t *)0x40050438)) |
| #define USB0_VDCISC_R (*((volatile uint32_t *)0x4005043C)) |
| #define USB0_VDCRIS_R (*((volatile uint32_t *)0x40050434)) |
| #define USB0_VPLEN_R (*((volatile uint8_t *)0x4005007B)) |
| #define USB_CONTIM_WTCON_M 0x000000F0 |
| #define USB_CONTIM_WTCON_S 4 |
| #define USB_CONTIM_WTID_M 0x0000000F |
| #define USB_CONTIM_WTID_S 0 |
| #define USB_COUNT0_COUNT_M 0x0000007F |
| #define USB_COUNT0_COUNT_S 0 |
| #define USB_CSRH0_DT 0x00000002 |
| #define USB_CSRH0_DTWE 0x00000004 |
| #define USB_CSRH0_FLUSH 0x00000001 |
| #define USB_CSRL0_DATAEND 0x00000008 |
| #define USB_CSRL0_ERROR 0x00000010 |
| #define USB_CSRL0_NAKTO 0x00000080 |
| #define USB_CSRL0_REQPKT 0x00000020 |
| #define USB_CSRL0_RXRDY 0x00000001 |
| #define USB_CSRL0_RXRDYC 0x00000040 |
| #define USB_CSRL0_SETEND 0x00000010 |
| #define USB_CSRL0_SETENDC 0x00000080 |
| #define USB_CSRL0_SETUP 0x00000008 |
| #define USB_CSRL0_STALL 0x00000020 |
| #define USB_CSRL0_STALLED 0x00000004 |
| #define USB_CSRL0_STATUS 0x00000040 |
| #define USB_CSRL0_TXRDY 0x00000002 |
| #define USB_DEVCTL_DEV 0x00000080 |
| #define USB_DEVCTL_FSDEV 0x00000040 |
| #define USB_DEVCTL_HOST 0x00000004 |
| #define USB_DEVCTL_HOSTREQ 0x00000002 |
| #define USB_DEVCTL_LSDEV 0x00000020 |
| #define USB_DEVCTL_SESSION 0x00000001 |
| #define USB_DEVCTL_VBUS_AVALID 0x00000010 |
| #define USB_DEVCTL_VBUS_M 0x00000018 |
| #define USB_DEVCTL_VBUS_NONE 0x00000000 |
| #define USB_DEVCTL_VBUS_SEND 0x00000008 |
| #define USB_DEVCTL_VBUS_VALID 0x00000018 |
| #define USB_DMASEL_DMAARX_M 0x0000000F |
| #define USB_DMASEL_DMAARX_S 0 |
| #define USB_DMASEL_DMAATX_M 0x000000F0 |
| #define USB_DMASEL_DMAATX_S 4 |
| #define USB_DMASEL_DMABRX_M 0x00000F00 |
| #define USB_DMASEL_DMABRX_S 8 |
| #define USB_DMASEL_DMABTX_M 0x0000F000 |
| #define USB_DMASEL_DMABTX_S 12 |
| #define USB_DMASEL_DMACRX_M 0x000F0000 |
| #define USB_DMASEL_DMACRX_S 16 |
| #define USB_DMASEL_DMACTX_M 0x00F00000 |
| #define USB_DMASEL_DMACTX_S 20 |
| #define USB_DRIM_RESUME 0x00000001 |
| #define USB_DRISC_RESUME 0x00000001 |
| #define USB_DRRIS_RESUME 0x00000001 |
| #define USB_EPC_EPEN_HIGH 0x00000001 |
| #define USB_EPC_EPEN_LOW 0x00000000 |
| #define USB_EPC_EPEN_M 0x00000003 |
| #define USB_EPC_EPEN_VBHIGH 0x00000003 |
| #define USB_EPC_EPEN_VBLOW 0x00000002 |
| #define USB_EPC_EPENDE 0x00000004 |
| #define USB_EPC_PFLTACT_HIGH 0x00000300 |
| #define USB_EPC_PFLTACT_LOW 0x00000200 |
| #define USB_EPC_PFLTACT_M 0x00000300 |
| #define USB_EPC_PFLTACT_TRIS 0x00000100 |
| #define USB_EPC_PFLTACT_UNCHG 0x00000000 |
| #define USB_EPC_PFLTAEN 0x00000040 |
| #define USB_EPC_PFLTEN 0x00000010 |
| #define USB_EPC_PFLTSEN_HIGH 0x00000020 |
| #define USB_EPCIM_PF 0x00000001 |
| #define USB_EPCISC_PF 0x00000001 |
| #define USB_EPCRIS_PF 0x00000001 |
| #define USB_EPIDX_EPIDX_M 0x0000000F |
| #define USB_EPIDX_EPIDX_S 0 |
| #define USB_FADDR_M 0x0000007F |
| #define USB_FADDR_S 0 |
| #define USB_FIFO0_EPDATA_M 0xFFFFFFFF |
| #define USB_FIFO0_EPDATA_S 0 |
| #define USB_FIFO1_EPDATA_M 0xFFFFFFFF |
| #define USB_FIFO1_EPDATA_S 0 |
| #define USB_FIFO2_EPDATA_M 0xFFFFFFFF |
| #define USB_FIFO2_EPDATA_S 0 |
| #define USB_FIFO3_EPDATA_M 0xFFFFFFFF |
| #define USB_FIFO3_EPDATA_S 0 |
| #define USB_FIFO4_EPDATA_M 0xFFFFFFFF |
| #define USB_FIFO4_EPDATA_S 0 |
| #define USB_FIFO5_EPDATA_M 0xFFFFFFFF |
| #define USB_FIFO5_EPDATA_S 0 |
| #define USB_FIFO6_EPDATA_M 0xFFFFFFFF |
| #define USB_FIFO6_EPDATA_S 0 |
| #define USB_FIFO7_EPDATA_M 0xFFFFFFFF |
| #define USB_FIFO7_EPDATA_S 0 |
| #define USB_FRAME_M 0x000007FF |
| #define USB_FRAME_S 0 |
| #define USB_FSEOF_FSEOFG_M 0x000000FF |
| #define USB_FSEOF_FSEOFG_S 0 |
| #define USB_GPCS_DEVMOD 0x00000001 |
| #define USB_GPCS_DEVMODOTG 0x00000002 |
| #define USB_IDVIM_ID 0x00000001 |
| #define USB_IDVISC_ID 0x00000001 |
| #define USB_IDVRIS_ID 0x00000001 |
| #define USB_IE_BABBLE 0x00000004 |
| #define USB_IE_CONN 0x00000010 |
| #define USB_IE_DISCON 0x00000020 |
| #define USB_IE_RESET 0x00000004 |
| #define USB_IE_RESUME 0x00000002 |
| #define USB_IE_SESREQ 0x00000040 |
| #define USB_IE_SOF 0x00000008 |
| #define USB_IE_SUSPND 0x00000001 |
| #define USB_IE_VBUSERR 0x00000080 |
| #define USB_IS_BABBLE 0x00000004 |
| #define USB_IS_CONN 0x00000010 |
| #define USB_IS_DISCON 0x00000020 |
| #define USB_IS_RESET 0x00000004 |
| #define USB_IS_RESUME 0x00000002 |
| #define USB_IS_SESREQ 0x00000040 |
| #define USB_IS_SOF 0x00000008 |
| #define USB_IS_SUSPEND 0x00000001 |
| #define USB_IS_VBUSERR 0x00000080 |
| #define USB_LSEOF_LSEOFG_M 0x000000FF |
| #define USB_LSEOF_LSEOFG_S 0 |
| #define USB_NAKLMT_NAKLMT_M 0x0000001F |
| #define USB_NAKLMT_NAKLMT_S 0 |
| #define USB_POWER_ISOUP 0x00000080 |
| #define USB_POWER_PWRDNPHY 0x00000001 |
| #define USB_POWER_RESET 0x00000008 |
| #define USB_POWER_RESUME 0x00000004 |
| #define USB_POWER_SOFTCONN 0x00000040 |
| #define USB_POWER_SUSPEND 0x00000002 |
| #define USB_PP_ECNT_M 0x0000FF00 |
| #define USB_PP_ECNT_S 8 |
| #define USB_PP_PHY 0x00000010 |
| #define USB_PP_TYPE_0 0x00000000 |
| #define USB_PP_TYPE_M 0x0000000F |
| #define USB_PP_USB_DEVICE 0x00000040 |
| #define USB_PP_USB_HOSTDEVICE 0x00000080 |
| #define USB_PP_USB_M 0x000000C0 |
| #define USB_PP_USB_OTG 0x000000C0 |
| #define USB_RQPKTCOUNT1_M 0x0000FFFF |
| #define USB_RQPKTCOUNT1_S 0 |
| #define USB_RQPKTCOUNT2_M 0x0000FFFF |
| #define USB_RQPKTCOUNT2_S 0 |
| #define USB_RQPKTCOUNT3_M 0x0000FFFF |
| #define USB_RQPKTCOUNT3_S 0 |
| #define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF |
| #define USB_RQPKTCOUNT4_COUNT_S 0 |
| #define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF |
| #define USB_RQPKTCOUNT5_COUNT_S 0 |
| #define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF |
| #define USB_RQPKTCOUNT6_COUNT_S 0 |
| #define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF |
| #define USB_RQPKTCOUNT7_COUNT_S 0 |
| #define USB_RXCOUNT1_COUNT_M 0x00001FFF |
| #define USB_RXCOUNT1_COUNT_S 0 |
| #define USB_RXCOUNT2_COUNT_M 0x00001FFF |
| #define USB_RXCOUNT2_COUNT_S 0 |
| #define USB_RXCOUNT3_COUNT_M 0x00001FFF |
| #define USB_RXCOUNT3_COUNT_S 0 |
| #define USB_RXCOUNT4_COUNT_M 0x00001FFF |
| #define USB_RXCOUNT4_COUNT_S 0 |
| #define USB_RXCOUNT5_COUNT_M 0x00001FFF |
| #define USB_RXCOUNT5_COUNT_S 0 |
| #define USB_RXCOUNT6_COUNT_M 0x00001FFF |
| #define USB_RXCOUNT6_COUNT_S 0 |
| #define USB_RXCOUNT7_COUNT_M 0x00001FFF |
| #define USB_RXCOUNT7_COUNT_S 0 |
| #define USB_RXCSRH1_AUTOCL 0x00000080 |
| #define USB_RXCSRH1_AUTORQ 0x00000040 |
| #define USB_RXCSRH1_DISNYET 0x00000010 |
| #define USB_RXCSRH1_DMAEN 0x00000020 |
| #define USB_RXCSRH1_DMAMOD 0x00000008 |
| #define USB_RXCSRH1_DT 0x00000002 |
| #define USB_RXCSRH1_DTWE 0x00000004 |
| #define USB_RXCSRH1_ISO 0x00000040 |
| #define USB_RXCSRH1_PIDERR 0x00000010 |
| #define USB_RXCSRH2_AUTOCL 0x00000080 |
| #define USB_RXCSRH2_AUTORQ 0x00000040 |
| #define USB_RXCSRH2_DISNYET 0x00000010 |
| #define USB_RXCSRH2_DMAEN 0x00000020 |
| #define USB_RXCSRH2_DMAMOD 0x00000008 |
| #define USB_RXCSRH2_DT 0x00000002 |
| #define USB_RXCSRH2_DTWE 0x00000004 |
| #define USB_RXCSRH2_ISO 0x00000040 |
| #define USB_RXCSRH2_PIDERR 0x00000010 |
| #define USB_RXCSRH3_AUTOCL 0x00000080 |
| #define USB_RXCSRH3_AUTORQ 0x00000040 |
| #define USB_RXCSRH3_DISNYET 0x00000010 |
| #define USB_RXCSRH3_DMAEN 0x00000020 |
| #define USB_RXCSRH3_DMAMOD 0x00000008 |
| #define USB_RXCSRH3_DT 0x00000002 |
| #define USB_RXCSRH3_DTWE 0x00000004 |
| #define USB_RXCSRH3_ISO 0x00000040 |
| #define USB_RXCSRH3_PIDERR 0x00000010 |
| #define USB_RXCSRH4_AUTOCL 0x00000080 |
| #define USB_RXCSRH4_AUTORQ 0x00000040 |
| #define USB_RXCSRH4_DISNYET 0x00000010 |
| #define USB_RXCSRH4_DMAEN 0x00000020 |
| #define USB_RXCSRH4_DMAMOD 0x00000008 |
| #define USB_RXCSRH4_DT 0x00000002 |
| #define USB_RXCSRH4_DTWE 0x00000004 |
| #define USB_RXCSRH4_ISO 0x00000040 |
| #define USB_RXCSRH4_PIDERR 0x00000010 |
| #define USB_RXCSRH5_AUTOCL 0x00000080 |
| #define USB_RXCSRH5_AUTORQ 0x00000040 |
| #define USB_RXCSRH5_DISNYET 0x00000010 |
| #define USB_RXCSRH5_DMAEN 0x00000020 |
| #define USB_RXCSRH5_DMAMOD 0x00000008 |
| #define USB_RXCSRH5_DT 0x00000002 |
| #define USB_RXCSRH5_DTWE 0x00000004 |
| #define USB_RXCSRH5_ISO 0x00000040 |
| #define USB_RXCSRH5_PIDERR 0x00000010 |
| #define USB_RXCSRH6_AUTOCL 0x00000080 |
| #define USB_RXCSRH6_AUTORQ 0x00000040 |
| #define USB_RXCSRH6_DISNYET 0x00000010 |
| #define USB_RXCSRH6_DMAEN 0x00000020 |
| #define USB_RXCSRH6_DMAMOD 0x00000008 |
| #define USB_RXCSRH6_DT 0x00000002 |
| #define USB_RXCSRH6_DTWE 0x00000004 |
| #define USB_RXCSRH6_ISO 0x00000040 |
| #define USB_RXCSRH6_PIDERR 0x00000010 |
| #define USB_RXCSRH7_AUTOCL 0x00000080 |
| #define USB_RXCSRH7_AUTORQ 0x00000040 |
| #define USB_RXCSRH7_DISNYET 0x00000010 |
| #define USB_RXCSRH7_DMAEN 0x00000020 |
| #define USB_RXCSRH7_DMAMOD 0x00000008 |
| #define USB_RXCSRH7_DT 0x00000002 |
| #define USB_RXCSRH7_DTWE 0x00000004 |
| #define USB_RXCSRH7_ISO 0x00000040 |
| #define USB_RXCSRH7_PIDERR 0x00000010 |
| #define USB_RXCSRL1_CLRDT 0x00000080 |
| #define USB_RXCSRL1_DATAERR 0x00000008 |
| #define USB_RXCSRL1_ERROR 0x00000004 |
| #define USB_RXCSRL1_FLUSH 0x00000010 |
| #define USB_RXCSRL1_FULL 0x00000002 |
| #define USB_RXCSRL1_NAKTO 0x00000008 |
| #define USB_RXCSRL1_OVER 0x00000004 |
| #define USB_RXCSRL1_REQPKT 0x00000020 |
| #define USB_RXCSRL1_RXRDY 0x00000001 |
| #define USB_RXCSRL1_STALL 0x00000020 |
| #define USB_RXCSRL1_STALLED 0x00000040 |
| #define USB_RXCSRL2_CLRDT 0x00000080 |
| #define USB_RXCSRL2_DATAERR 0x00000008 |
| #define USB_RXCSRL2_ERROR 0x00000004 |
| #define USB_RXCSRL2_FLUSH 0x00000010 |
| #define USB_RXCSRL2_FULL 0x00000002 |
| #define USB_RXCSRL2_NAKTO 0x00000008 |
| #define USB_RXCSRL2_OVER 0x00000004 |
| #define USB_RXCSRL2_REQPKT 0x00000020 |
| #define USB_RXCSRL2_RXRDY 0x00000001 |
| #define USB_RXCSRL2_STALL 0x00000020 |
| #define USB_RXCSRL2_STALLED 0x00000040 |
| #define USB_RXCSRL3_CLRDT 0x00000080 |
| #define USB_RXCSRL3_DATAERR 0x00000008 |
| #define USB_RXCSRL3_ERROR 0x00000004 |
| #define USB_RXCSRL3_FLUSH 0x00000010 |
| #define USB_RXCSRL3_FULL 0x00000002 |
| #define USB_RXCSRL3_NAKTO 0x00000008 |
| #define USB_RXCSRL3_OVER 0x00000004 |
| #define USB_RXCSRL3_REQPKT 0x00000020 |
| #define USB_RXCSRL3_RXRDY 0x00000001 |
| #define USB_RXCSRL3_STALL 0x00000020 |
| #define USB_RXCSRL3_STALLED 0x00000040 |
| #define USB_RXCSRL4_CLRDT 0x00000080 |
| #define USB_RXCSRL4_DATAERR 0x00000008 |
| #define USB_RXCSRL4_ERROR 0x00000004 |
| #define USB_RXCSRL4_FLUSH 0x00000010 |
| #define USB_RXCSRL4_FULL 0x00000002 |
| #define USB_RXCSRL4_NAKTO 0x00000008 |
| #define USB_RXCSRL4_OVER 0x00000004 |
| #define USB_RXCSRL4_REQPKT 0x00000020 |
| #define USB_RXCSRL4_RXRDY 0x00000001 |
| #define USB_RXCSRL4_STALL 0x00000020 |
| #define USB_RXCSRL4_STALLED 0x00000040 |
| #define USB_RXCSRL5_CLRDT 0x00000080 |
| #define USB_RXCSRL5_DATAERR 0x00000008 |
| #define USB_RXCSRL5_ERROR 0x00000004 |
| #define USB_RXCSRL5_FLUSH 0x00000010 |
| #define USB_RXCSRL5_FULL 0x00000002 |
| #define USB_RXCSRL5_NAKTO 0x00000008 |
| #define USB_RXCSRL5_OVER 0x00000004 |
| #define USB_RXCSRL5_REQPKT 0x00000020 |
| #define USB_RXCSRL5_RXRDY 0x00000001 |
| #define USB_RXCSRL5_STALL 0x00000020 |
| #define USB_RXCSRL5_STALLED 0x00000040 |
| #define USB_RXCSRL6_CLRDT 0x00000080 |
| #define USB_RXCSRL6_DATAERR 0x00000008 |
| #define USB_RXCSRL6_ERROR 0x00000004 |
| #define USB_RXCSRL6_FLUSH 0x00000010 |
| #define USB_RXCSRL6_FULL 0x00000002 |
| #define USB_RXCSRL6_NAKTO 0x00000008 |
| #define USB_RXCSRL6_OVER 0x00000004 |
| #define USB_RXCSRL6_REQPKT 0x00000020 |
| #define USB_RXCSRL6_RXRDY 0x00000001 |
| #define USB_RXCSRL6_STALL 0x00000020 |
| #define USB_RXCSRL6_STALLED 0x00000040 |
| #define USB_RXCSRL7_CLRDT 0x00000080 |
| #define USB_RXCSRL7_DATAERR 0x00000008 |
| #define USB_RXCSRL7_ERROR 0x00000004 |
| #define USB_RXCSRL7_FLUSH 0x00000010 |
| #define USB_RXCSRL7_FULL 0x00000002 |
| #define USB_RXCSRL7_NAKTO 0x00000008 |
| #define USB_RXCSRL7_OVER 0x00000004 |
| #define USB_RXCSRL7_REQPKT 0x00000020 |
| #define USB_RXCSRL7_RXRDY 0x00000001 |
| #define USB_RXCSRL7_STALL 0x00000020 |
| #define USB_RXCSRL7_STALLED 0x00000040 |
| #define USB_RXDPKTBUFDIS_EP1 0x00000002 |
| #define USB_RXDPKTBUFDIS_EP2 0x00000004 |
| #define USB_RXDPKTBUFDIS_EP3 0x00000008 |
| #define USB_RXDPKTBUFDIS_EP4 0x00000010 |
| #define USB_RXDPKTBUFDIS_EP5 0x00000020 |
| #define USB_RXDPKTBUFDIS_EP6 0x00000040 |
| #define USB_RXDPKTBUFDIS_EP7 0x00000080 |
| #define USB_RXFIFOADD_ADDR_M 0x000001FF |
| #define USB_RXFIFOADD_ADDR_S 0 |
| #define USB_RXFIFOSZ_DPB 0x00000010 |
| #define USB_RXFIFOSZ_SIZE_1024 0x00000007 |
| #define USB_RXFIFOSZ_SIZE_128 0x00000004 |
| #define USB_RXFIFOSZ_SIZE_16 0x00000001 |
| #define USB_RXFIFOSZ_SIZE_2048 0x00000008 |
| #define USB_RXFIFOSZ_SIZE_256 0x00000005 |
| #define USB_RXFIFOSZ_SIZE_32 0x00000002 |
| #define USB_RXFIFOSZ_SIZE_512 0x00000006 |
| #define USB_RXFIFOSZ_SIZE_64 0x00000003 |
| #define USB_RXFIFOSZ_SIZE_8 0x00000000 |
| #define USB_RXFIFOSZ_SIZE_M 0x0000000F |
| #define USB_RXFUNCADDR1_ADDR_M 0x0000007F |
| #define USB_RXFUNCADDR1_ADDR_S 0 |
| #define USB_RXFUNCADDR2_ADDR_M 0x0000007F |
| #define USB_RXFUNCADDR2_ADDR_S 0 |
| #define USB_RXFUNCADDR3_ADDR_M 0x0000007F |
| #define USB_RXFUNCADDR3_ADDR_S 0 |
| #define USB_RXFUNCADDR4_ADDR_M 0x0000007F |
| #define USB_RXFUNCADDR4_ADDR_S 0 |
| #define USB_RXFUNCADDR5_ADDR_M 0x0000007F |
| #define USB_RXFUNCADDR5_ADDR_S 0 |
| #define USB_RXFUNCADDR6_ADDR_M 0x0000007F |
| #define USB_RXFUNCADDR6_ADDR_S 0 |
| #define USB_RXFUNCADDR7_ADDR_M 0x0000007F |
| #define USB_RXFUNCADDR7_ADDR_S 0 |
| #define USB_RXHUBADDR1_ADDR_M 0x0000007F |
| #define USB_RXHUBADDR1_ADDR_S 0 |
| #define USB_RXHUBADDR2_ADDR_M 0x0000007F |
| #define USB_RXHUBADDR2_ADDR_S 0 |
| #define USB_RXHUBADDR3_ADDR_M 0x0000007F |
| #define USB_RXHUBADDR3_ADDR_S 0 |
| #define USB_RXHUBADDR4_ADDR_M 0x0000007F |
| #define USB_RXHUBADDR4_ADDR_S 0 |
| #define USB_RXHUBADDR5_ADDR_M 0x0000007F |
| #define USB_RXHUBADDR5_ADDR_S 0 |
| #define USB_RXHUBADDR6_ADDR_M 0x0000007F |
| #define USB_RXHUBADDR6_ADDR_S 0 |
| #define USB_RXHUBADDR7_ADDR_M 0x0000007F |
| #define USB_RXHUBADDR7_ADDR_S 0 |
| #define USB_RXHUBPORT1_PORT_M 0x0000007F |
| #define USB_RXHUBPORT1_PORT_S 0 |
| #define USB_RXHUBPORT2_PORT_M 0x0000007F |
| #define USB_RXHUBPORT2_PORT_S 0 |
| #define USB_RXHUBPORT3_PORT_M 0x0000007F |
| #define USB_RXHUBPORT3_PORT_S 0 |
| #define USB_RXHUBPORT4_PORT_M 0x0000007F |
| #define USB_RXHUBPORT4_PORT_S 0 |
| #define USB_RXHUBPORT5_PORT_M 0x0000007F |
| #define USB_RXHUBPORT5_PORT_S 0 |
| #define USB_RXHUBPORT6_PORT_M 0x0000007F |
| #define USB_RXHUBPORT6_PORT_S 0 |
| #define USB_RXHUBPORT7_PORT_M 0x0000007F |
| #define USB_RXHUBPORT7_PORT_S 0 |
| #define USB_RXIE_EP1 0x00000002 |
| #define USB_RXIE_EP2 0x00000004 |
| #define USB_RXIE_EP3 0x00000008 |
| #define USB_RXIE_EP4 0x00000010 |
| #define USB_RXIE_EP5 0x00000020 |
| #define USB_RXIE_EP6 0x00000040 |
| #define USB_RXIE_EP7 0x00000080 |
| #define USB_RXINTERVAL1_NAKLMT_M 0x000000FF |
| #define USB_RXINTERVAL1_NAKLMT_S 0 |
| #define USB_RXINTERVAL1_TXPOLL_M 0x000000FF |
| #define USB_RXINTERVAL1_TXPOLL_S 0 |
| #define USB_RXINTERVAL2_NAKLMT_M 0x000000FF |
| #define USB_RXINTERVAL2_NAKLMT_S 0 |
| #define USB_RXINTERVAL2_TXPOLL_M 0x000000FF |
| #define USB_RXINTERVAL2_TXPOLL_S 0 |
| #define USB_RXINTERVAL3_NAKLMT_M 0x000000FF |
| #define USB_RXINTERVAL3_NAKLMT_S 0 |
| #define USB_RXINTERVAL3_TXPOLL_M 0x000000FF |
| #define USB_RXINTERVAL3_TXPOLL_S 0 |
| #define USB_RXINTERVAL4_NAKLMT_M 0x000000FF |
| #define USB_RXINTERVAL4_NAKLMT_S 0 |
| #define USB_RXINTERVAL4_TXPOLL_M 0x000000FF |
| #define USB_RXINTERVAL4_TXPOLL_S 0 |
| #define USB_RXINTERVAL5_NAKLMT_M 0x000000FF |
| #define USB_RXINTERVAL5_NAKLMT_S 0 |
| #define USB_RXINTERVAL5_TXPOLL_M 0x000000FF |
| #define USB_RXINTERVAL5_TXPOLL_S 0 |
| #define USB_RXINTERVAL6_NAKLMT_M 0x000000FF |
| #define USB_RXINTERVAL6_NAKLMT_S 0 |
| #define USB_RXINTERVAL6_TXPOLL_M 0x000000FF |
| #define USB_RXINTERVAL6_TXPOLL_S 0 |
| #define USB_RXINTERVAL7_NAKLMT_M 0x000000FF |
| #define USB_RXINTERVAL7_NAKLMT_S 0 |
| #define USB_RXINTERVAL7_TXPOLL_M 0x000000FF |
| #define USB_RXINTERVAL7_TXPOLL_S 0 |
| #define USB_RXIS_EP1 0x00000002 |
| #define USB_RXIS_EP2 0x00000004 |
| #define USB_RXIS_EP3 0x00000008 |
| #define USB_RXIS_EP4 0x00000010 |
| #define USB_RXIS_EP5 0x00000020 |
| #define USB_RXIS_EP6 0x00000040 |
| #define USB_RXIS_EP7 0x00000080 |
| #define USB_RXMAXP1_MAXLOAD_M 0x000007FF |
| #define USB_RXMAXP1_MAXLOAD_S 0 |
| #define USB_RXMAXP2_MAXLOAD_M 0x000007FF |
| #define USB_RXMAXP2_MAXLOAD_S 0 |
| #define USB_RXMAXP3_MAXLOAD_M 0x000007FF |
| #define USB_RXMAXP3_MAXLOAD_S 0 |
| #define USB_RXMAXP4_MAXLOAD_M 0x000007FF |
| #define USB_RXMAXP4_MAXLOAD_S 0 |
| #define USB_RXMAXP5_MAXLOAD_M 0x000007FF |
| #define USB_RXMAXP5_MAXLOAD_S 0 |
| #define USB_RXMAXP6_MAXLOAD_M 0x000007FF |
| #define USB_RXMAXP6_MAXLOAD_S 0 |
| #define USB_RXMAXP7_MAXLOAD_M 0x000007FF |
| #define USB_RXMAXP7_MAXLOAD_S 0 |
| #define USB_RXTYPE1_PROTO_BULK 0x00000020 |
| #define USB_RXTYPE1_PROTO_CTRL 0x00000000 |
| #define USB_RXTYPE1_PROTO_INT 0x00000030 |
| #define USB_RXTYPE1_PROTO_ISOC 0x00000010 |
| #define USB_RXTYPE1_PROTO_M 0x00000030 |
| #define USB_RXTYPE1_SPEED_DFLT 0x00000000 |
| #define USB_RXTYPE1_SPEED_FULL 0x00000080 |
| #define USB_RXTYPE1_SPEED_LOW 0x000000C0 |
| #define USB_RXTYPE1_SPEED_M 0x000000C0 |
| #define USB_RXTYPE1_TEP_M 0x0000000F |
| #define USB_RXTYPE1_TEP_S 0 |
| #define USB_RXTYPE2_PROTO_BULK 0x00000020 |
| #define USB_RXTYPE2_PROTO_CTRL 0x00000000 |
| #define USB_RXTYPE2_PROTO_INT 0x00000030 |
| #define USB_RXTYPE2_PROTO_ISOC 0x00000010 |
| #define USB_RXTYPE2_PROTO_M 0x00000030 |
| #define USB_RXTYPE2_SPEED_DFLT 0x00000000 |
| #define USB_RXTYPE2_SPEED_FULL 0x00000080 |
| #define USB_RXTYPE2_SPEED_LOW 0x000000C0 |
| #define USB_RXTYPE2_SPEED_M 0x000000C0 |
| #define USB_RXTYPE2_TEP_M 0x0000000F |
| #define USB_RXTYPE2_TEP_S 0 |
| #define USB_RXTYPE3_PROTO_BULK 0x00000020 |
| #define USB_RXTYPE3_PROTO_CTRL 0x00000000 |
| #define USB_RXTYPE3_PROTO_INT 0x00000030 |
| #define USB_RXTYPE3_PROTO_ISOC 0x00000010 |
| #define USB_RXTYPE3_PROTO_M 0x00000030 |
| #define USB_RXTYPE3_SPEED_DFLT 0x00000000 |
| #define USB_RXTYPE3_SPEED_FULL 0x00000080 |
| #define USB_RXTYPE3_SPEED_LOW 0x000000C0 |
| #define USB_RXTYPE3_SPEED_M 0x000000C0 |
| #define USB_RXTYPE3_TEP_M 0x0000000F |
| #define USB_RXTYPE3_TEP_S 0 |
| #define USB_RXTYPE4_PROTO_BULK 0x00000020 |
| #define USB_RXTYPE4_PROTO_CTRL 0x00000000 |
| #define USB_RXTYPE4_PROTO_INT 0x00000030 |
| #define USB_RXTYPE4_PROTO_ISOC 0x00000010 |
| #define USB_RXTYPE4_PROTO_M 0x00000030 |
| #define USB_RXTYPE4_SPEED_DFLT 0x00000000 |
| #define USB_RXTYPE4_SPEED_FULL 0x00000080 |
| #define USB_RXTYPE4_SPEED_LOW 0x000000C0 |
| #define USB_RXTYPE4_SPEED_M 0x000000C0 |
| #define USB_RXTYPE4_TEP_M 0x0000000F |
| #define USB_RXTYPE4_TEP_S 0 |
| #define USB_RXTYPE5_PROTO_BULK 0x00000020 |
| #define USB_RXTYPE5_PROTO_CTRL 0x00000000 |
| #define USB_RXTYPE5_PROTO_INT 0x00000030 |
| #define USB_RXTYPE5_PROTO_ISOC 0x00000010 |
| #define USB_RXTYPE5_PROTO_M 0x00000030 |
| #define USB_RXTYPE5_SPEED_DFLT 0x00000000 |
| #define USB_RXTYPE5_SPEED_FULL 0x00000080 |
| #define USB_RXTYPE5_SPEED_LOW 0x000000C0 |
| #define USB_RXTYPE5_SPEED_M 0x000000C0 |
| #define USB_RXTYPE5_TEP_M 0x0000000F |
| #define USB_RXTYPE5_TEP_S 0 |
| #define USB_RXTYPE6_PROTO_BULK 0x00000020 |
| #define USB_RXTYPE6_PROTO_CTRL 0x00000000 |
| #define USB_RXTYPE6_PROTO_INT 0x00000030 |
| #define USB_RXTYPE6_PROTO_ISOC 0x00000010 |
| #define USB_RXTYPE6_PROTO_M 0x00000030 |
| #define USB_RXTYPE6_SPEED_DFLT 0x00000000 |
| #define USB_RXTYPE6_SPEED_FULL 0x00000080 |
| #define USB_RXTYPE6_SPEED_LOW 0x000000C0 |
| #define USB_RXTYPE6_SPEED_M 0x000000C0 |
| #define USB_RXTYPE6_TEP_M 0x0000000F |
| #define USB_RXTYPE6_TEP_S 0 |
| #define USB_RXTYPE7_PROTO_BULK 0x00000020 |
| #define USB_RXTYPE7_PROTO_CTRL 0x00000000 |
| #define USB_RXTYPE7_PROTO_INT 0x00000030 |
| #define USB_RXTYPE7_PROTO_ISOC 0x00000010 |
| #define USB_RXTYPE7_PROTO_M 0x00000030 |
| #define USB_RXTYPE7_SPEED_DFLT 0x00000000 |
| #define USB_RXTYPE7_SPEED_FULL 0x00000080 |
| #define USB_RXTYPE7_SPEED_LOW 0x000000C0 |
| #define USB_RXTYPE7_SPEED_M 0x000000C0 |
| #define USB_RXTYPE7_TEP_M 0x0000000F |
| #define USB_RXTYPE7_TEP_S 0 |
| #define USB_TEST_FIFOACC 0x00000040 |
| #define USB_TEST_FORCEFS 0x00000020 |
| #define USB_TEST_FORCEH 0x00000080 |
| #define USB_TXCSRH1_AUTOSET 0x00000080 |
| #define USB_TXCSRH1_DMAEN 0x00000010 |
| #define USB_TXCSRH1_DMAMOD 0x00000004 |
| #define USB_TXCSRH1_DT 0x00000001 |
| #define USB_TXCSRH1_DTWE 0x00000002 |
| #define USB_TXCSRH1_FDT 0x00000008 |
| #define USB_TXCSRH1_ISO 0x00000040 |
| #define USB_TXCSRH1_MODE 0x00000020 |
| #define USB_TXCSRH2_AUTOSET 0x00000080 |
| #define USB_TXCSRH2_DMAEN 0x00000010 |
| #define USB_TXCSRH2_DMAMOD 0x00000004 |
| #define USB_TXCSRH2_DT 0x00000001 |
| #define USB_TXCSRH2_DTWE 0x00000002 |
| #define USB_TXCSRH2_FDT 0x00000008 |
| #define USB_TXCSRH2_ISO 0x00000040 |
| #define USB_TXCSRH2_MODE 0x00000020 |
| #define USB_TXCSRH3_AUTOSET 0x00000080 |
| #define USB_TXCSRH3_DMAEN 0x00000010 |
| #define USB_TXCSRH3_DMAMOD 0x00000004 |
| #define USB_TXCSRH3_DT 0x00000001 |
| #define USB_TXCSRH3_DTWE 0x00000002 |
| #define USB_TXCSRH3_FDT 0x00000008 |
| #define USB_TXCSRH3_ISO 0x00000040 |
| #define USB_TXCSRH3_MODE 0x00000020 |
| #define USB_TXCSRH4_AUTOSET 0x00000080 |
| #define USB_TXCSRH4_DMAEN 0x00000010 |
| #define USB_TXCSRH4_DMAMOD 0x00000004 |
| #define USB_TXCSRH4_DT 0x00000001 |
| #define USB_TXCSRH4_DTWE 0x00000002 |
| #define USB_TXCSRH4_FDT 0x00000008 |
| #define USB_TXCSRH4_ISO 0x00000040 |
| #define USB_TXCSRH4_MODE 0x00000020 |
| #define USB_TXCSRH5_AUTOSET 0x00000080 |
| #define USB_TXCSRH5_DMAEN 0x00000010 |
| #define USB_TXCSRH5_DMAMOD 0x00000004 |
| #define USB_TXCSRH5_DT 0x00000001 |
| #define USB_TXCSRH5_DTWE 0x00000002 |
| #define USB_TXCSRH5_FDT 0x00000008 |
| #define USB_TXCSRH5_ISO 0x00000040 |
| #define USB_TXCSRH5_MODE 0x00000020 |
| #define USB_TXCSRH6_AUTOSET 0x00000080 |
| #define USB_TXCSRH6_DMAEN 0x00000010 |
| #define USB_TXCSRH6_DMAMOD 0x00000004 |
| #define USB_TXCSRH6_DT 0x00000001 |
| #define USB_TXCSRH6_DTWE 0x00000002 |
| #define USB_TXCSRH6_FDT 0x00000008 |
| #define USB_TXCSRH6_ISO 0x00000040 |
| #define USB_TXCSRH6_MODE 0x00000020 |
| #define USB_TXCSRH7_AUTOSET 0x00000080 |
| #define USB_TXCSRH7_DMAEN 0x00000010 |
| #define USB_TXCSRH7_DMAMOD 0x00000004 |
| #define USB_TXCSRH7_DT 0x00000001 |
| #define USB_TXCSRH7_DTWE 0x00000002 |
| #define USB_TXCSRH7_FDT 0x00000008 |
| #define USB_TXCSRH7_ISO 0x00000040 |
| #define USB_TXCSRH7_MODE 0x00000020 |
| #define USB_TXCSRL1_CLRDT 0x00000040 |
| #define USB_TXCSRL1_ERROR 0x00000004 |
| #define USB_TXCSRL1_FIFONE 0x00000002 |
| #define USB_TXCSRL1_FLUSH 0x00000008 |
| #define USB_TXCSRL1_NAKTO 0x00000080 |
| #define USB_TXCSRL1_SETUP 0x00000010 |
| #define USB_TXCSRL1_STALL 0x00000010 |
| #define USB_TXCSRL1_STALLED 0x00000020 |
| #define USB_TXCSRL1_TXRDY 0x00000001 |
| #define USB_TXCSRL1_UNDRN 0x00000004 |
| #define USB_TXCSRL2_CLRDT 0x00000040 |
| #define USB_TXCSRL2_ERROR 0x00000004 |
| #define USB_TXCSRL2_FIFONE 0x00000002 |
| #define USB_TXCSRL2_FLUSH 0x00000008 |
| #define USB_TXCSRL2_NAKTO 0x00000080 |
| #define USB_TXCSRL2_SETUP 0x00000010 |
| #define USB_TXCSRL2_STALL 0x00000010 |
| #define USB_TXCSRL2_STALLED 0x00000020 |
| #define USB_TXCSRL2_TXRDY 0x00000001 |
| #define USB_TXCSRL2_UNDRN 0x00000004 |
| #define USB_TXCSRL3_CLRDT 0x00000040 |
| #define USB_TXCSRL3_ERROR 0x00000004 |
| #define USB_TXCSRL3_FIFONE 0x00000002 |
| #define USB_TXCSRL3_FLUSH 0x00000008 |
| #define USB_TXCSRL3_NAKTO 0x00000080 |
| #define USB_TXCSRL3_SETUP 0x00000010 |
| #define USB_TXCSRL3_STALL 0x00000010 |
| #define USB_TXCSRL3_STALLED 0x00000020 |
| #define USB_TXCSRL3_TXRDY 0x00000001 |
| #define USB_TXCSRL3_UNDRN 0x00000004 |
| #define USB_TXCSRL4_CLRDT 0x00000040 |
| #define USB_TXCSRL4_ERROR 0x00000004 |
| #define USB_TXCSRL4_FIFONE 0x00000002 |
| #define USB_TXCSRL4_FLUSH 0x00000008 |
| #define USB_TXCSRL4_NAKTO 0x00000080 |
| #define USB_TXCSRL4_SETUP 0x00000010 |
| #define USB_TXCSRL4_STALL 0x00000010 |
| #define USB_TXCSRL4_STALLED 0x00000020 |
| #define USB_TXCSRL4_TXRDY 0x00000001 |
| #define USB_TXCSRL4_UNDRN 0x00000004 |
| #define USB_TXCSRL5_CLRDT 0x00000040 |
| #define USB_TXCSRL5_ERROR 0x00000004 |
| #define USB_TXCSRL5_FIFONE 0x00000002 |
| #define USB_TXCSRL5_FLUSH 0x00000008 |
| #define USB_TXCSRL5_NAKTO 0x00000080 |
| #define USB_TXCSRL5_SETUP 0x00000010 |
| #define USB_TXCSRL5_STALL 0x00000010 |
| #define USB_TXCSRL5_STALLED 0x00000020 |
| #define USB_TXCSRL5_TXRDY 0x00000001 |
| #define USB_TXCSRL5_UNDRN 0x00000004 |
| #define USB_TXCSRL6_CLRDT 0x00000040 |
| #define USB_TXCSRL6_ERROR 0x00000004 |
| #define USB_TXCSRL6_FIFONE 0x00000002 |
| #define USB_TXCSRL6_FLUSH 0x00000008 |
| #define USB_TXCSRL6_NAKTO 0x00000080 |
| #define USB_TXCSRL6_SETUP 0x00000010 |
| #define USB_TXCSRL6_STALL 0x00000010 |
| #define USB_TXCSRL6_STALLED 0x00000020 |
| #define USB_TXCSRL6_TXRDY 0x00000001 |
| #define USB_TXCSRL6_UNDRN 0x00000004 |
| #define USB_TXCSRL7_CLRDT 0x00000040 |
| #define USB_TXCSRL7_ERROR 0x00000004 |
| #define USB_TXCSRL7_FIFONE 0x00000002 |
| #define USB_TXCSRL7_FLUSH 0x00000008 |
| #define USB_TXCSRL7_NAKTO 0x00000080 |
| #define USB_TXCSRL7_SETUP 0x00000010 |
| #define USB_TXCSRL7_STALL 0x00000010 |
| #define USB_TXCSRL7_STALLED 0x00000020 |
| #define USB_TXCSRL7_TXRDY 0x00000001 |
| #define USB_TXCSRL7_UNDRN 0x00000004 |
| #define USB_TXDPKTBUFDIS_EP1 0x00000002 |
| #define USB_TXDPKTBUFDIS_EP2 0x00000004 |
| #define USB_TXDPKTBUFDIS_EP3 0x00000008 |
| #define USB_TXDPKTBUFDIS_EP4 0x00000010 |
| #define USB_TXDPKTBUFDIS_EP5 0x00000020 |
| #define USB_TXDPKTBUFDIS_EP6 0x00000040 |
| #define USB_TXDPKTBUFDIS_EP7 0x00000080 |
| #define USB_TXFIFOADD_ADDR_M 0x000001FF |
| #define USB_TXFIFOADD_ADDR_S 0 |
| #define USB_TXFIFOSZ_DPB 0x00000010 |
| #define USB_TXFIFOSZ_SIZE_1024 0x00000007 |
| #define USB_TXFIFOSZ_SIZE_128 0x00000004 |
| #define USB_TXFIFOSZ_SIZE_16 0x00000001 |
| #define USB_TXFIFOSZ_SIZE_2048 0x00000008 |
| #define USB_TXFIFOSZ_SIZE_256 0x00000005 |
| #define USB_TXFIFOSZ_SIZE_32 0x00000002 |
| #define USB_TXFIFOSZ_SIZE_512 0x00000006 |
| #define USB_TXFIFOSZ_SIZE_64 0x00000003 |
| #define USB_TXFIFOSZ_SIZE_8 0x00000000 |
| #define USB_TXFIFOSZ_SIZE_M 0x0000000F |
| #define USB_TXFUNCADDR0_ADDR_M 0x0000007F |
| #define USB_TXFUNCADDR0_ADDR_S 0 |
| #define USB_TXFUNCADDR1_ADDR_M 0x0000007F |
| #define USB_TXFUNCADDR1_ADDR_S 0 |
| #define USB_TXFUNCADDR2_ADDR_M 0x0000007F |
| #define USB_TXFUNCADDR2_ADDR_S 0 |
| #define USB_TXFUNCADDR3_ADDR_M 0x0000007F |
| #define USB_TXFUNCADDR3_ADDR_S 0 |
| #define USB_TXFUNCADDR4_ADDR_M 0x0000007F |
| #define USB_TXFUNCADDR4_ADDR_S 0 |
| #define USB_TXFUNCADDR5_ADDR_M 0x0000007F |
| #define USB_TXFUNCADDR5_ADDR_S 0 |
| #define USB_TXFUNCADDR6_ADDR_M 0x0000007F |
| #define USB_TXFUNCADDR6_ADDR_S 0 |
| #define USB_TXFUNCADDR7_ADDR_M 0x0000007F |
| #define USB_TXFUNCADDR7_ADDR_S 0 |
| #define USB_TXHUBADDR0_ADDR_M 0x0000007F |
| #define USB_TXHUBADDR0_ADDR_S 0 |
| #define USB_TXHUBADDR1_ADDR_M 0x0000007F |
| #define USB_TXHUBADDR1_ADDR_S 0 |
| #define USB_TXHUBADDR2_ADDR_M 0x0000007F |
| #define USB_TXHUBADDR2_ADDR_S 0 |
| #define USB_TXHUBADDR3_ADDR_M 0x0000007F |
| #define USB_TXHUBADDR3_ADDR_S 0 |
| #define USB_TXHUBADDR4_ADDR_M 0x0000007F |
| #define USB_TXHUBADDR4_ADDR_S 0 |
| #define USB_TXHUBADDR5_ADDR_M 0x0000007F |
| #define USB_TXHUBADDR5_ADDR_S 0 |
| #define USB_TXHUBADDR6_ADDR_M 0x0000007F |
| #define USB_TXHUBADDR6_ADDR_S 0 |
| #define USB_TXHUBADDR7_ADDR_M 0x0000007F |
| #define USB_TXHUBADDR7_ADDR_S 0 |
| #define USB_TXHUBPORT0_PORT_M 0x0000007F |
| #define USB_TXHUBPORT0_PORT_S 0 |
| #define USB_TXHUBPORT1_PORT_M 0x0000007F |
| #define USB_TXHUBPORT1_PORT_S 0 |
| #define USB_TXHUBPORT2_PORT_M 0x0000007F |
| #define USB_TXHUBPORT2_PORT_S 0 |
| #define USB_TXHUBPORT3_PORT_M 0x0000007F |
| #define USB_TXHUBPORT3_PORT_S 0 |
| #define USB_TXHUBPORT4_PORT_M 0x0000007F |
| #define USB_TXHUBPORT4_PORT_S 0 |
| #define USB_TXHUBPORT5_PORT_M 0x0000007F |
| #define USB_TXHUBPORT5_PORT_S 0 |
| #define USB_TXHUBPORT6_PORT_M 0x0000007F |
| #define USB_TXHUBPORT6_PORT_S 0 |
| #define USB_TXHUBPORT7_PORT_M 0x0000007F |
| #define USB_TXHUBPORT7_PORT_S 0 |
| #define USB_TXIE_EP0 0x00000001 |
| #define USB_TXIE_EP1 0x00000002 |
| #define USB_TXIE_EP2 0x00000004 |
| #define USB_TXIE_EP3 0x00000008 |
| #define USB_TXIE_EP4 0x00000010 |
| #define USB_TXIE_EP5 0x00000020 |
| #define USB_TXIE_EP6 0x00000040 |
| #define USB_TXIE_EP7 0x00000080 |
| #define USB_TXINTERVAL1_NAKLMT_M 0x000000FF |
| #define USB_TXINTERVAL1_NAKLMT_S 0 |
| #define USB_TXINTERVAL1_TXPOLL_M 0x000000FF |
| #define USB_TXINTERVAL1_TXPOLL_S 0 |
| #define USB_TXINTERVAL2_NAKLMT_M 0x000000FF |
| #define USB_TXINTERVAL2_NAKLMT_S 0 |
| #define USB_TXINTERVAL2_TXPOLL_M 0x000000FF |
| #define USB_TXINTERVAL2_TXPOLL_S 0 |
| #define USB_TXINTERVAL3_NAKLMT_M 0x000000FF |
| #define USB_TXINTERVAL3_NAKLMT_S 0 |
| #define USB_TXINTERVAL3_TXPOLL_M 0x000000FF |
| #define USB_TXINTERVAL3_TXPOLL_S 0 |
| #define USB_TXINTERVAL4_NAKLMT_M 0x000000FF |
| #define USB_TXINTERVAL4_NAKLMT_S 0 |
| #define USB_TXINTERVAL4_TXPOLL_M 0x000000FF |
| #define USB_TXINTERVAL4_TXPOLL_S 0 |
| #define USB_TXINTERVAL5_NAKLMT_M 0x000000FF |
| #define USB_TXINTERVAL5_NAKLMT_S 0 |
| #define USB_TXINTERVAL5_TXPOLL_M 0x000000FF |
| #define USB_TXINTERVAL5_TXPOLL_S 0 |
| #define USB_TXINTERVAL6_NAKLMT_M 0x000000FF |
| #define USB_TXINTERVAL6_NAKLMT_S 0 |
| #define USB_TXINTERVAL6_TXPOLL_M 0x000000FF |
| #define USB_TXINTERVAL6_TXPOLL_S 0 |
| #define USB_TXINTERVAL7_NAKLMT_M 0x000000FF |
| #define USB_TXINTERVAL7_NAKLMT_S 0 |
| #define USB_TXINTERVAL7_TXPOLL_M 0x000000FF |
| #define USB_TXINTERVAL7_TXPOLL_S 0 |
| #define USB_TXIS_EP0 0x00000001 |
| #define USB_TXIS_EP1 0x00000002 |
| #define USB_TXIS_EP2 0x00000004 |
| #define USB_TXIS_EP3 0x00000008 |
| #define USB_TXIS_EP4 0x00000010 |
| #define USB_TXIS_EP5 0x00000020 |
| #define USB_TXIS_EP6 0x00000040 |
| #define USB_TXIS_EP7 0x00000080 |
| #define USB_TXMAXP1_MAXLOAD_M 0x000007FF |
| #define USB_TXMAXP1_MAXLOAD_S 0 |
| #define USB_TXMAXP2_MAXLOAD_M 0x000007FF |
| #define USB_TXMAXP2_MAXLOAD_S 0 |
| #define USB_TXMAXP3_MAXLOAD_M 0x000007FF |
| #define USB_TXMAXP3_MAXLOAD_S 0 |
| #define USB_TXMAXP4_MAXLOAD_M 0x000007FF |
| #define USB_TXMAXP4_MAXLOAD_S 0 |
| #define USB_TXMAXP5_MAXLOAD_M 0x000007FF |
| #define USB_TXMAXP5_MAXLOAD_S 0 |
| #define USB_TXMAXP6_MAXLOAD_M 0x000007FF |
| #define USB_TXMAXP6_MAXLOAD_S 0 |
| #define USB_TXMAXP7_MAXLOAD_M 0x000007FF |
| #define USB_TXMAXP7_MAXLOAD_S 0 |
| #define USB_TXTYPE1_PROTO_BULK 0x00000020 |
| #define USB_TXTYPE1_PROTO_CTRL 0x00000000 |
| #define USB_TXTYPE1_PROTO_INT 0x00000030 |
| #define USB_TXTYPE1_PROTO_ISOC 0x00000010 |
| #define USB_TXTYPE1_PROTO_M 0x00000030 |
| #define USB_TXTYPE1_SPEED_DFLT 0x00000000 |
| #define USB_TXTYPE1_SPEED_FULL 0x00000080 |
| #define USB_TXTYPE1_SPEED_LOW 0x000000C0 |
| #define USB_TXTYPE1_SPEED_M 0x000000C0 |
| #define USB_TXTYPE1_TEP_M 0x0000000F |
| #define USB_TXTYPE1_TEP_S 0 |
| #define USB_TXTYPE2_PROTO_BULK 0x00000020 |
| #define USB_TXTYPE2_PROTO_CTRL 0x00000000 |
| #define USB_TXTYPE2_PROTO_INT 0x00000030 |
| #define USB_TXTYPE2_PROTO_ISOC 0x00000010 |
| #define USB_TXTYPE2_PROTO_M 0x00000030 |
| #define USB_TXTYPE2_SPEED_DFLT 0x00000000 |
| #define USB_TXTYPE2_SPEED_FULL 0x00000080 |
| #define USB_TXTYPE2_SPEED_LOW 0x000000C0 |
| #define USB_TXTYPE2_SPEED_M 0x000000C0 |
| #define USB_TXTYPE2_TEP_M 0x0000000F |
| #define USB_TXTYPE2_TEP_S 0 |
| #define USB_TXTYPE3_PROTO_BULK 0x00000020 |
| #define USB_TXTYPE3_PROTO_CTRL 0x00000000 |
| #define USB_TXTYPE3_PROTO_INT 0x00000030 |
| #define USB_TXTYPE3_PROTO_ISOC 0x00000010 |
| #define USB_TXTYPE3_PROTO_M 0x00000030 |
| #define USB_TXTYPE3_SPEED_DFLT 0x00000000 |
| #define USB_TXTYPE3_SPEED_FULL 0x00000080 |
| #define USB_TXTYPE3_SPEED_LOW 0x000000C0 |
| #define USB_TXTYPE3_SPEED_M 0x000000C0 |
| #define USB_TXTYPE3_TEP_M 0x0000000F |
| #define USB_TXTYPE3_TEP_S 0 |
| #define USB_TXTYPE4_PROTO_BULK 0x00000020 |
| #define USB_TXTYPE4_PROTO_CTRL 0x00000000 |
| #define USB_TXTYPE4_PROTO_INT 0x00000030 |
| #define USB_TXTYPE4_PROTO_ISOC 0x00000010 |
| #define USB_TXTYPE4_PROTO_M 0x00000030 |
| #define USB_TXTYPE4_SPEED_DFLT 0x00000000 |
| #define USB_TXTYPE4_SPEED_FULL 0x00000080 |
| #define USB_TXTYPE4_SPEED_LOW 0x000000C0 |
| #define USB_TXTYPE4_SPEED_M 0x000000C0 |
| #define USB_TXTYPE4_TEP_M 0x0000000F |
| #define USB_TXTYPE4_TEP_S 0 |
| #define USB_TXTYPE5_PROTO_BULK 0x00000020 |
| #define USB_TXTYPE5_PROTO_CTRL 0x00000000 |
| #define USB_TXTYPE5_PROTO_INT 0x00000030 |
| #define USB_TXTYPE5_PROTO_ISOC 0x00000010 |
| #define USB_TXTYPE5_PROTO_M 0x00000030 |
| #define USB_TXTYPE5_SPEED_DFLT 0x00000000 |
| #define USB_TXTYPE5_SPEED_FULL 0x00000080 |
| #define USB_TXTYPE5_SPEED_LOW 0x000000C0 |
| #define USB_TXTYPE5_SPEED_M 0x000000C0 |
| #define USB_TXTYPE5_TEP_M 0x0000000F |
| #define USB_TXTYPE5_TEP_S 0 |
| #define USB_TXTYPE6_PROTO_BULK 0x00000020 |
| #define USB_TXTYPE6_PROTO_CTRL 0x00000000 |
| #define USB_TXTYPE6_PROTO_INT 0x00000030 |
| #define USB_TXTYPE6_PROTO_ISOC 0x00000010 |
| #define USB_TXTYPE6_PROTO_M 0x00000030 |
| #define USB_TXTYPE6_SPEED_DFLT 0x00000000 |
| #define USB_TXTYPE6_SPEED_FULL 0x00000080 |
| #define USB_TXTYPE6_SPEED_LOW 0x000000C0 |
| #define USB_TXTYPE6_SPEED_M 0x000000C0 |
| #define USB_TXTYPE6_TEP_M 0x0000000F |
| #define USB_TXTYPE6_TEP_S 0 |
| #define USB_TXTYPE7_PROTO_BULK 0x00000020 |
| #define USB_TXTYPE7_PROTO_CTRL 0x00000000 |
| #define USB_TXTYPE7_PROTO_INT 0x00000030 |
| #define USB_TXTYPE7_PROTO_ISOC 0x00000010 |
| #define USB_TXTYPE7_PROTO_M 0x00000030 |
| #define USB_TXTYPE7_SPEED_DFLT 0x00000000 |
| #define USB_TXTYPE7_SPEED_FULL 0x00000080 |
| #define USB_TXTYPE7_SPEED_LOW 0x000000C0 |
| #define USB_TXTYPE7_SPEED_M 0x000000C0 |
| #define USB_TXTYPE7_TEP_M 0x0000000F |
| #define USB_TXTYPE7_TEP_S 0 |
| #define USB_TYPE0_SPEED_FULL 0x00000080 |
| #define USB_TYPE0_SPEED_LOW 0x000000C0 |
| #define USB_TYPE0_SPEED_M 0x000000C0 |
| #define USB_VDC_VBDEN 0x00000001 |
| #define USB_VDCIM_VD 0x00000001 |
| #define USB_VDCISC_VD 0x00000001 |
| #define USB_VDCRIS_VD 0x00000001 |
| #define USB_VPLEN_VPLEN_M 0x000000FF |
| #define USB_VPLEN_VPLEN_S 0 |
| #define WATCHDOG0_CTL_R (*((volatile uint32_t *)0x40000008)) |
| #define WATCHDOG0_ICR_R (*((volatile uint32_t *)0x4000000C)) |
| #define WATCHDOG0_LOAD_R (*((volatile uint32_t *)0x40000000)) |
| #define WATCHDOG0_LOCK_R (*((volatile uint32_t *)0x40000C00)) |
| #define WATCHDOG0_MIS_R (*((volatile uint32_t *)0x40000014)) |
| #define WATCHDOG0_RIS_R (*((volatile uint32_t *)0x40000010)) |
| #define WATCHDOG0_TEST_R (*((volatile uint32_t *)0x40000418)) |
| #define WATCHDOG0_VALUE_R (*((volatile uint32_t *)0x40000004)) |
| #define WATCHDOG1_CTL_R (*((volatile uint32_t *)0x40001008)) |
| #define WATCHDOG1_ICR_R (*((volatile uint32_t *)0x4000100C)) |
| #define WATCHDOG1_LOAD_R (*((volatile uint32_t *)0x40001000)) |
| #define WATCHDOG1_LOCK_R (*((volatile uint32_t *)0x40001C00)) |
| #define WATCHDOG1_MIS_R (*((volatile uint32_t *)0x40001014)) |
| #define WATCHDOG1_RIS_R (*((volatile uint32_t *)0x40001010)) |
| #define WATCHDOG1_TEST_R (*((volatile uint32_t *)0x40001418)) |
| #define WATCHDOG1_VALUE_R (*((volatile uint32_t *)0x40001004)) |
| #define WDT_CTL_INTEN 0x00000001 |
| #define WDT_CTL_INTTYPE 0x00000004 |
| #define WDT_CTL_RESEN 0x00000002 |
| #define WDT_CTL_WRC 0x80000000 |
| #define WDT_ICR_M 0xFFFFFFFF |
| #define WDT_ICR_S 0 |
| #define WDT_LOAD_M 0xFFFFFFFF |
| #define WDT_LOAD_S 0 |
| #define WDT_LOCK_LOCKED 0x00000001 |
| #define WDT_LOCK_M 0xFFFFFFFF |
| #define WDT_LOCK_UNLOCK 0x1ACCE551 |
| #define WDT_LOCK_UNLOCKED 0x00000000 |
| #define WDT_MIS_WDTMIS 0x00000001 |
| #define WDT_RIS_WDTRIS 0x00000001 |
| #define WDT_TEST_STALL 0x00000100 |
| #define WDT_VALUE_M 0xFFFFFFFF |
| #define WDT_VALUE_S 0 |
| #define WTIMER0_CFG_R (*((volatile uint32_t *)0x40036000)) |
| #define WTIMER0_CTL_R (*((volatile uint32_t *)0x4003600C)) |
| #define WTIMER0_ICR_R (*((volatile uint32_t *)0x40036024)) |
| #define WTIMER0_IMR_R (*((volatile uint32_t *)0x40036018)) |
| #define WTIMER0_MIS_R (*((volatile uint32_t *)0x40036020)) |
| #define WTIMER0_PP_R (*((volatile uint32_t *)0x40036FC0)) |
| #define WTIMER0_RIS_R (*((volatile uint32_t *)0x4003601C)) |
| #define WTIMER0_RTCPD_R (*((volatile uint32_t *)0x40036058)) |
| #define WTIMER0_SYNC_R (*((volatile uint32_t *)0x40036010)) |
| #define WTIMER0_TAILR_R (*((volatile uint32_t *)0x40036028)) |
| #define WTIMER0_TAMATCHR_R (*((volatile uint32_t *)0x40036030)) |
| #define WTIMER0_TAMR_R (*((volatile uint32_t *)0x40036004)) |
| #define WTIMER0_TAPMR_R (*((volatile uint32_t *)0x40036040)) |
| #define WTIMER0_TAPR_R (*((volatile uint32_t *)0x40036038)) |
| #define WTIMER0_TAPS_R (*((volatile uint32_t *)0x4003605C)) |
| #define WTIMER0_TAPV_R (*((volatile uint32_t *)0x40036064)) |
| #define WTIMER0_TAR_R (*((volatile uint32_t *)0x40036048)) |
| #define WTIMER0_TAV_R (*((volatile uint32_t *)0x40036050)) |
| #define WTIMER0_TBILR_R (*((volatile uint32_t *)0x4003602C)) |
| #define WTIMER0_TBMATCHR_R (*((volatile uint32_t *)0x40036034)) |
| #define WTIMER0_TBMR_R (*((volatile uint32_t *)0x40036008)) |
| #define WTIMER0_TBPMR_R (*((volatile uint32_t *)0x40036044)) |
| #define WTIMER0_TBPR_R (*((volatile uint32_t *)0x4003603C)) |
| #define WTIMER0_TBPS_R (*((volatile uint32_t *)0x40036060)) |
| #define WTIMER0_TBPV_R (*((volatile uint32_t *)0x40036068)) |
| #define WTIMER0_TBR_R (*((volatile uint32_t *)0x4003604C)) |
| #define WTIMER0_TBV_R (*((volatile uint32_t *)0x40036054)) |
| #define WTIMER1_CFG_R (*((volatile uint32_t *)0x40037000)) |
| #define WTIMER1_CTL_R (*((volatile uint32_t *)0x4003700C)) |
| #define WTIMER1_ICR_R (*((volatile uint32_t *)0x40037024)) |
| #define WTIMER1_IMR_R (*((volatile uint32_t *)0x40037018)) |
| #define WTIMER1_MIS_R (*((volatile uint32_t *)0x40037020)) |
| #define WTIMER1_PP_R (*((volatile uint32_t *)0x40037FC0)) |
| #define WTIMER1_RIS_R (*((volatile uint32_t *)0x4003701C)) |
| #define WTIMER1_RTCPD_R (*((volatile uint32_t *)0x40037058)) |
| #define WTIMER1_SYNC_R (*((volatile uint32_t *)0x40037010)) |
| #define WTIMER1_TAILR_R (*((volatile uint32_t *)0x40037028)) |
| #define WTIMER1_TAMATCHR_R (*((volatile uint32_t *)0x40037030)) |
| #define WTIMER1_TAMR_R (*((volatile uint32_t *)0x40037004)) |
| #define WTIMER1_TAPMR_R (*((volatile uint32_t *)0x40037040)) |
| #define WTIMER1_TAPR_R (*((volatile uint32_t *)0x40037038)) |
| #define WTIMER1_TAPS_R (*((volatile uint32_t *)0x4003705C)) |
| #define WTIMER1_TAPV_R (*((volatile uint32_t *)0x40037064)) |
| #define WTIMER1_TAR_R (*((volatile uint32_t *)0x40037048)) |
| #define WTIMER1_TAV_R (*((volatile uint32_t *)0x40037050)) |
| #define WTIMER1_TBILR_R (*((volatile uint32_t *)0x4003702C)) |
| #define WTIMER1_TBMATCHR_R (*((volatile uint32_t *)0x40037034)) |
| #define WTIMER1_TBMR_R (*((volatile uint32_t *)0x40037008)) |
| #define WTIMER1_TBPMR_R (*((volatile uint32_t *)0x40037044)) |
| #define WTIMER1_TBPR_R (*((volatile uint32_t *)0x4003703C)) |
| #define WTIMER1_TBPS_R (*((volatile uint32_t *)0x40037060)) |
| #define WTIMER1_TBPV_R (*((volatile uint32_t *)0x40037068)) |
| #define WTIMER1_TBR_R (*((volatile uint32_t *)0x4003704C)) |
| #define WTIMER1_TBV_R (*((volatile uint32_t *)0x40037054)) |
| #define WTIMER2_CFG_R (*((volatile uint32_t *)0x4004C000)) |
| #define WTIMER2_CTL_R (*((volatile uint32_t *)0x4004C00C)) |
| #define WTIMER2_ICR_R (*((volatile uint32_t *)0x4004C024)) |
| #define WTIMER2_IMR_R (*((volatile uint32_t *)0x4004C018)) |
| #define WTIMER2_MIS_R (*((volatile uint32_t *)0x4004C020)) |
| #define WTIMER2_PP_R (*((volatile uint32_t *)0x4004CFC0)) |
| #define WTIMER2_RIS_R (*((volatile uint32_t *)0x4004C01C)) |
| #define WTIMER2_RTCPD_R (*((volatile uint32_t *)0x4004C058)) |
| #define WTIMER2_SYNC_R (*((volatile uint32_t *)0x4004C010)) |
| #define WTIMER2_TAILR_R (*((volatile uint32_t *)0x4004C028)) |
| #define WTIMER2_TAMATCHR_R (*((volatile uint32_t *)0x4004C030)) |
| #define WTIMER2_TAMR_R (*((volatile uint32_t *)0x4004C004)) |
| #define WTIMER2_TAPMR_R (*((volatile uint32_t *)0x4004C040)) |
| #define WTIMER2_TAPR_R (*((volatile uint32_t *)0x4004C038)) |
| #define WTIMER2_TAPS_R (*((volatile uint32_t *)0x4004C05C)) |
| #define WTIMER2_TAPV_R (*((volatile uint32_t *)0x4004C064)) |
| #define WTIMER2_TAR_R (*((volatile uint32_t *)0x4004C048)) |
| #define WTIMER2_TAV_R (*((volatile uint32_t *)0x4004C050)) |
| #define WTIMER2_TBILR_R (*((volatile uint32_t *)0x4004C02C)) |
| #define WTIMER2_TBMATCHR_R (*((volatile uint32_t *)0x4004C034)) |
| #define WTIMER2_TBMR_R (*((volatile uint32_t *)0x4004C008)) |
| #define WTIMER2_TBPMR_R (*((volatile uint32_t *)0x4004C044)) |
| #define WTIMER2_TBPR_R (*((volatile uint32_t *)0x4004C03C)) |
| #define WTIMER2_TBPS_R (*((volatile uint32_t *)0x4004C060)) |
| #define WTIMER2_TBPV_R (*((volatile uint32_t *)0x4004C068)) |
| #define WTIMER2_TBR_R (*((volatile uint32_t *)0x4004C04C)) |
| #define WTIMER2_TBV_R (*((volatile uint32_t *)0x4004C054)) |
| #define WTIMER3_CFG_R (*((volatile uint32_t *)0x4004D000)) |
| #define WTIMER3_CTL_R (*((volatile uint32_t *)0x4004D00C)) |
| #define WTIMER3_ICR_R (*((volatile uint32_t *)0x4004D024)) |
| #define WTIMER3_IMR_R (*((volatile uint32_t *)0x4004D018)) |
| #define WTIMER3_MIS_R (*((volatile uint32_t *)0x4004D020)) |
| #define WTIMER3_PP_R (*((volatile uint32_t *)0x4004DFC0)) |
| #define WTIMER3_RIS_R (*((volatile uint32_t *)0x4004D01C)) |
| #define WTIMER3_RTCPD_R (*((volatile uint32_t *)0x4004D058)) |
| #define WTIMER3_SYNC_R (*((volatile uint32_t *)0x4004D010)) |
| #define WTIMER3_TAILR_R (*((volatile uint32_t *)0x4004D028)) |
| #define WTIMER3_TAMATCHR_R (*((volatile uint32_t *)0x4004D030)) |
| #define WTIMER3_TAMR_R (*((volatile uint32_t *)0x4004D004)) |
| #define WTIMER3_TAPMR_R (*((volatile uint32_t *)0x4004D040)) |
| #define WTIMER3_TAPR_R (*((volatile uint32_t *)0x4004D038)) |
| #define WTIMER3_TAPS_R (*((volatile uint32_t *)0x4004D05C)) |
| #define WTIMER3_TAPV_R (*((volatile uint32_t *)0x4004D064)) |
| #define WTIMER3_TAR_R (*((volatile uint32_t *)0x4004D048)) |
| #define WTIMER3_TAV_R (*((volatile uint32_t *)0x4004D050)) |
| #define WTIMER3_TBILR_R (*((volatile uint32_t *)0x4004D02C)) |
| #define WTIMER3_TBMATCHR_R (*((volatile uint32_t *)0x4004D034)) |
| #define WTIMER3_TBMR_R (*((volatile uint32_t *)0x4004D008)) |
| #define WTIMER3_TBPMR_R (*((volatile uint32_t *)0x4004D044)) |
| #define WTIMER3_TBPR_R (*((volatile uint32_t *)0x4004D03C)) |
| #define WTIMER3_TBPS_R (*((volatile uint32_t *)0x4004D060)) |
| #define WTIMER3_TBPV_R (*((volatile uint32_t *)0x4004D068)) |
| #define WTIMER3_TBR_R (*((volatile uint32_t *)0x4004D04C)) |
| #define WTIMER3_TBV_R (*((volatile uint32_t *)0x4004D054)) |
| #define WTIMER4_CFG_R (*((volatile uint32_t *)0x4004E000)) |
| #define WTIMER4_CTL_R (*((volatile uint32_t *)0x4004E00C)) |
| #define WTIMER4_ICR_R (*((volatile uint32_t *)0x4004E024)) |
| #define WTIMER4_IMR_R (*((volatile uint32_t *)0x4004E018)) |
| #define WTIMER4_MIS_R (*((volatile uint32_t *)0x4004E020)) |
| #define WTIMER4_PP_R (*((volatile uint32_t *)0x4004EFC0)) |
| #define WTIMER4_RIS_R (*((volatile uint32_t *)0x4004E01C)) |
| #define WTIMER4_RTCPD_R (*((volatile uint32_t *)0x4004E058)) |
| #define WTIMER4_SYNC_R (*((volatile uint32_t *)0x4004E010)) |
| #define WTIMER4_TAILR_R (*((volatile uint32_t *)0x4004E028)) |
| #define WTIMER4_TAMATCHR_R (*((volatile uint32_t *)0x4004E030)) |
| #define WTIMER4_TAMR_R (*((volatile uint32_t *)0x4004E004)) |
| #define WTIMER4_TAPMR_R (*((volatile uint32_t *)0x4004E040)) |
| #define WTIMER4_TAPR_R (*((volatile uint32_t *)0x4004E038)) |
| #define WTIMER4_TAPS_R (*((volatile uint32_t *)0x4004E05C)) |
| #define WTIMER4_TAPV_R (*((volatile uint32_t *)0x4004E064)) |
| #define WTIMER4_TAR_R (*((volatile uint32_t *)0x4004E048)) |
| #define WTIMER4_TAV_R (*((volatile uint32_t *)0x4004E050)) |
| #define WTIMER4_TBILR_R (*((volatile uint32_t *)0x4004E02C)) |
| #define WTIMER4_TBMATCHR_R (*((volatile uint32_t *)0x4004E034)) |
| #define WTIMER4_TBMR_R (*((volatile uint32_t *)0x4004E008)) |
| #define WTIMER4_TBPMR_R (*((volatile uint32_t *)0x4004E044)) |
| #define WTIMER4_TBPR_R (*((volatile uint32_t *)0x4004E03C)) |
| #define WTIMER4_TBPS_R (*((volatile uint32_t *)0x4004E060)) |
| #define WTIMER4_TBPV_R (*((volatile uint32_t *)0x4004E068)) |
| #define WTIMER4_TBR_R (*((volatile uint32_t *)0x4004E04C)) |
| #define WTIMER4_TBV_R (*((volatile uint32_t *)0x4004E054)) |
| #define WTIMER5_CFG_R (*((volatile uint32_t *)0x4004F000)) |
| #define WTIMER5_CTL_R (*((volatile uint32_t *)0x4004F00C)) |
| #define WTIMER5_ICR_R (*((volatile uint32_t *)0x4004F024)) |
| #define WTIMER5_IMR_R (*((volatile uint32_t *)0x4004F018)) |
| #define WTIMER5_MIS_R (*((volatile uint32_t *)0x4004F020)) |
| #define WTIMER5_PP_R (*((volatile uint32_t *)0x4004FFC0)) |
| #define WTIMER5_RIS_R (*((volatile uint32_t *)0x4004F01C)) |
| #define WTIMER5_RTCPD_R (*((volatile uint32_t *)0x4004F058)) |
| #define WTIMER5_SYNC_R (*((volatile uint32_t *)0x4004F010)) |
| #define WTIMER5_TAILR_R (*((volatile uint32_t *)0x4004F028)) |
| #define WTIMER5_TAMATCHR_R (*((volatile uint32_t *)0x4004F030)) |
| #define WTIMER5_TAMR_R (*((volatile uint32_t *)0x4004F004)) |
| #define WTIMER5_TAPMR_R (*((volatile uint32_t *)0x4004F040)) |
| #define WTIMER5_TAPR_R (*((volatile uint32_t *)0x4004F038)) |
| #define WTIMER5_TAPS_R (*((volatile uint32_t *)0x4004F05C)) |
| #define WTIMER5_TAPV_R (*((volatile uint32_t *)0x4004F064)) |
| #define WTIMER5_TAR_R (*((volatile uint32_t *)0x4004F048)) |
| #define WTIMER5_TAV_R (*((volatile uint32_t *)0x4004F050)) |
| #define WTIMER5_TBILR_R (*((volatile uint32_t *)0x4004F02C)) |
| #define WTIMER5_TBMATCHR_R (*((volatile uint32_t *)0x4004F034)) |
| #define WTIMER5_TBMR_R (*((volatile uint32_t *)0x4004F008)) |
| #define WTIMER5_TBPMR_R (*((volatile uint32_t *)0x4004F044)) |
| #define WTIMER5_TBPR_R (*((volatile uint32_t *)0x4004F03C)) |
| #define WTIMER5_TBPS_R (*((volatile uint32_t *)0x4004F060)) |
| #define WTIMER5_TBPV_R (*((volatile uint32_t *)0x4004F068)) |
| #define WTIMER5_TBR_R (*((volatile uint32_t *)0x4004F04C)) |
| #define WTIMER5_TBV_R (*((volatile uint32_t *)0x4004F054)) |